JPH06140904A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the delay time by connecting an end of an n-channel MOS transistor (TR) not connecting to a p-channel MOS TR to ground so as to reduce number of longitudinal stacks of TRs. CONSTITUTION:The integrated circuit consists of n-channel MOS TRs 10-17, 20-23, a p-channel MOSTR 30, and 2-input AND gates 50-53. Drains or sources of n-channel MOS TRs 20-23 are connected directly to ground. When any of input signals P1-P4 is at a high level, a p-channel MOS TR to which an output of the 2-input AND gate is connected is turned on. Furthermore, n-channel MOS TRs 10-11, 12-13, 14-15 or 16-17 forming the n-channel MOS circuit are turned on, a charge on a node (a) is discharged to ground and an output OUT goes to a high level. Thus, a ground level is obtained by only the n-channel MOS circuit in which n-channel MOS TRs are connected in cascade and number of longitudinal stack stages of the TRs is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high speed operation of a semiconductor integrated circuit. [0002]

2. Description of the Related Art As shown in FIG. 3, a conventional semiconductor integrated circuit has n-type MOS transistors 10-17 and 20-2.
3, p-type MOS transistor 30, inverter gate 4
It was composed of 0-44. Here, n-type MOS transistors 20 to 23 and p-type MOS transistor 30
Is an additional circuit for precharging, and the input signal P1
~ P4 is input via the inverter gates 40-44.

FIG. 4 shows operation waveforms. When the clock input signal Φ is at a low level, the p-type MOS transistor 30 is “on”, the n-type MOS transistors 20 to 23 are “off”, and the node a is precharged. Output OUT is L
ow level.

Further, while the clock input signal Φ is at the Low level, the input signals A, -A, B, -B and P1 to P4 are input.
To decide. When the clock input signal Φ is High level, the p-type MOS transistor 30 is “off”, and the n-type MO transistor is
The S transistors 20 to 23 turn on, and the input signal P1
To P4 are High level, the n-type MOS transistors 10 to 11, 12 to 13, and 14 to 15 which form the cascade connected nMOS circuit to which the inverter gates 41 to 44 to which the input signal is input are connected. Or 1
If 6 to 17 are “on”, the charge accumulated in the node a is n.
It is discharged to the ground through the n-type MOS transistor in the MOS circuit and the inverter gate, and the output OUT is High.
It becomes the h level. Therefore, the basic operation is to transmit the output of the inverter gate to the output through the cascade connection circuit of the n-type MOS transistors.

[0005]

However, in this conventional semiconductor integrated circuit, the accumulated charges are accumulated in the cascade connection of the n-type MOS transistors and the n-type MO in the inverter gate.
Since it is intended to discharge to the ground via the S-transistor, there is a problem that the delay time is long because the number of vertically stacked transistors is deep and the discharge is slow.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel semiconductor integrated circuit capable of solving the above problems inherent in the conventional art. Especially.

[0007]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention does not use an n-type MOS transistor in an inverter gate to discharge the accumulated charge, and uses a clock signal. The n-type MOS transistor, which is input to and is turned off during precharge, is directly connected to the ground and its gate is controlled.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings with reference to the accompanying drawings.

FIG. 1 is a circuit configuration diagram showing a first embodiment according to the present invention.

Referring to FIG. 1, a first embodiment according to the present invention is an n-type MOS transistor 10-17 and 20-.
23, a p-type MOS transistor 30, and 2-input AND gates 50 to 53. Where n-type MO
The drains or sources of the S transistors 20 to 23 are directly connected to the ground, and the gates thereof include the clock input Φ and the signal P1 from the 2-input AND gates 50 to 53.
To P4 are input, and the clock input Φ is Low level, that is, the outputs of the two-input AND gates 50 to 53 are Low level regardless of the input signals of P1 to P4 at the time of precharge, and n Type MOS transistors 20 to 23 are turned off, and p type MOS transistor 3
The node a is precharged by 0. When the clock input Φ is High level, the p-type MOS transistor 30 is “off”, the two-input AND gates 50 to 53 are “on”, and the input signals P1 to P4 are transmitted to the n-type MOS transistors 20 to 23. If any of the input signals P1 to P4 is High level, the n-type MOS transistor to which the output of the 2-input AND gate is connected is turned on,
Further, an n-type MOS forming a cascade-connected nMOS circuit connecting the node a and this n-type MOS transistor
When the transistors 10 to 11, 12 to 13, 14 to 15 or 16 to 17 are "on", the electric charge accumulated at the node a is discharged to the ground, and the output OUT becomes High level. Therefore, only the nMOS circuit in which n-type MOS transistors are connected in cascade can be formed up to the ground, and the number of stages of vertically stacked transistors is reduced to accelerate discharge, so that the delay time can be shortened (decreased).

FIG. 2 is a circuit configuration diagram showing a second embodiment according to the present invention, which is an example in which a domino circuit is used for the input portion of the input signals P1 to P4.

Referring to FIG. 2, the clock signal Φ is LO
At the W level, that is, at the time of precharge, the nodes b, c, d,
e is set to High by the p-type MOS transistors 31 to 34.
Precharged to the h level and the inverter gate 45 to
Low level n-type MOS transistor 2 via 48
It is input to the gates of 0 to 23 and turned "off", and at the same time, the node a is precharged by the p-type MOS transistor 30. When the clock input Φ is at the high level, the p-type MOS transistors 30 and 30 to 34 are “off”, the n-type MOS transistors 24 to 27 are “off”, and the input signals P1 to P4 are at the high level, so that the n-type MOS transistors are turned on. Transistors 60-63 are "on"
However, the nodes b, c, d, and e become low level, and the high level is input to the n-type MOS transistors 20 to 23 via the inverter gates 45 to 48, and the same operation as in the first embodiment described above is performed. It can be carried out. With such a configuration, the delay from the clock signal can be made faster (smaller).

[0013]

As described above, according to the present invention,
Since the nMOS circuit in which the n-type MOS transistors are connected in cascade can be directly connected to the ground, the number of stacked stages of the transistors is reduced, and the discharge time of the charges is accelerated, so that the delay time can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 3 is a circuit diagram of a conventional semiconductor integrated circuit.

FIG. 4 is an operation waveform.

[Explanation of symbols]

10-17, 20-27, 60-63 ... N-type MOS transistor 30-34 ... P-type MOS transistor 40-48 ... Inverter gate 50-53 ... 2-input AND gate

Claims (1)

[Claims] 1. A plurality of nMOS circuits in which a plurality of n-type MOS transistors are cascade-connected, one end of each of the nMOS circuits is connected, and a p-type MOS transistor is connected between this connection point and a power supply. In the precharge type pass transistor logic circuit described above, an end of an n-type MOS transistor which is not connected to the p-type MOS transistor is connected to the ground.