KR19990016198A - Method for manufacturing field emission device using silicide process - Google Patents

Abstract

The present invention provides a method of sharply forming a silicon emitter tip or a metal emitter tip capable of emitting electrons to a field emission device using a silicide process at a low temperature. The emitter tip is sharp to facilitate field emission. In addition, the tip can be sharpened at a lower temperature than the conventional manufacturing method, and uniformity and symmetry are high, and an emitter tip can be formed on the glass plate. In addition, the present invention can not only vacuum-pack the fabricated array on a glass plate but also make a large area flat panel display at low cost.

Description

Method for manufacturing field emission device using silicide process

The present invention relates to a method of manufacturing a field emission device, and more particularly, to a method of forming an emitter tip of a field emission device at a low temperature.

The field emission device is a vacuum device that applies an electric field to emit electrons from a emitter tip in a vacuum or a specific gas atmosphere, and is used as a microwave device, a flat panel display, a sensor, or the like. Among these, researches on applying such field emission devices to field emission displays (FEDs) have been actively conducted in recent years.

1 is a cross-sectional view showing a conventional FED structure, in which a lower plate 100 having an arrayed field emission device and an upper plate 200 having phosphor 201 are vacuumed in parallel to each other by a spacer 300. It is packaged and configured to emit electrons from the emitter tip 101 by controlling the gate electrode of the field emission device, and the emitted electrons collide with the phosphor 201 of the upper plate 200 to cause the cathode of the phosphor 201. It is a device for displaying an image by cathode luminescence. That is, the operation principle of the FED is an anode electrode in which a phosphor is applied by applying a voltage to the gate and the cathode (the emitter electrode connected to the emitter tip) to emit electrons, and to be accelerated by the anode voltage. In this case, the excited phosphor material receives energy from the electrons and is used in a display using the principle of emitting light.

2A through 2E are cross-sectional views illustrating a method of manufacturing a field emission device according to the related art. First, as shown in FIG. 2A, a silicon oxide film 203 is formed on a silicon film 202, and then a photoresist 204 is formed. After patterning and etching, the silicon oxide film 203 is patterned, the photoresist 204 pattern is removed, and the silicon film 202 isotropically dried using the patterned silicon oxide film 203 as a mask as shown in FIG. 2B. Etch it. Subsequently, as shown in FIG. 2C, the exposed silicon film 202 is thermally oxidized to grow the oxide film 210, and as shown in FIG. 2D, the gate insulating film 208 and the gate conduction are formed by an electron beam deposition (e-beam) method. After the deposition of the film 209, as shown in FIG. 2E, the oxide film 210 is partially etched to lift off the electrode on the tip.

When using the prior art as shown in Figures 2a to 2e, there is a disadvantage that the emitter array can not be produced on the glass plate because the process is performed at a high temperature.

3A and 3E are cross-sectional views illustrating another method of manufacturing a field emission device according to the related art. First, as shown in FIG. 3A, a silicon oxide film 303 is formed on a silicon film 302, and then a photoresist 304 is formed. Patterning and etching the silicon oxide film 303, removing the photoresist 304 pattern, and isotropically forming the silicon film 302 using the patterned silicon oxide film 303 as a mask, as shown in FIG. 3B. Dry etch. 3C, the exposed silicon film 302 is wet etched to form a silicon tip. Subsequently, as shown in FIG. 3D, after the gate insulating film 308 and the gate conductive film 309 are deposited on the entire surface, as shown in FIG. 3E, the gate conductive film 309 and the gate insulating film 308 are partially formed to expose the silicon tip. Wet etch.

In the case of using the prior art as shown in FIGS. 3A and 3E, the process can be performed at a low temperature, but the etching uniformity of the large area becomes worse due to the nature of the wet etching.

As described above, in manufacturing the emitter tip of the field emission device, silicon or polycrystalline silicon is formed by using dry etching and wet etching, or after dry etching or wet etching, in order to form a sharp shape thereof. The growth process is used, but it is difficult to etch uniformly pointedly. In addition, after isotropic etching of silicon or polysilicon by dry etching, an oxide film is grown at a high temperature of 800 ° C. or higher to make it pointed. However, such a manufacturing method uses a high temperature process and cannot be manufactured on a glass plate. In case of vacuum packaging the FEA (Field Emission Array) produced later, the packaging yield is lowered because the packaging is attached to the glass plate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a field emission device capable of low temperature processing, and increasing the uniformity and symmetry of the top of the emitter tip.

1 is a cross-sectional view showing a conventional field emission display (FED) structure.

2A to 2E are cross-sectional views illustrating a method of manufacturing a field emission device according to the related art.

3A to 3E are cross-sectional views illustrating another method of manufacturing a field emission device according to the related art.

4A to 4H are cross-sectional views illustrating a method of manufacturing a field emission device according to an embodiment of the present invention.

5A to 5H are cross-sectional views illustrating a method of manufacturing a field emission device according to another exemplary embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

401, 501: glass substrate 402: emitter conductive film of silicon series

403: hard mask layer 405, 505: metal layer

404: photoresist pattern 406, 506: silicide layer

407 emitter tip 408, 508 gate insulating film

409 and 509: gate conductive film 511: buffer film

502: amorphous silicon film

One characteristic field emission device manufacturing method of the present invention for achieving the above object comprises the steps of forming a silicon-based thin film for the emitter on the substrate; Forming a mask pattern on the silicon based thin film; Etching the silicon-based thin film to a predetermined thickness to form a neck portion of the emitter tip, and removing the mask pattern; Forming a high melting point metal film for silicide on the silicon-based thin film on which the neck of the emitter tip is formed; Forming a silicide film by reacting the silicon-based thin film with the metal film by heat treatment in order to sharply form an emitter tip neck of the silicon-based thin film; And removing the silicide film.

In addition, another characteristic field emission device manufacturing method of the present invention, forming a buffer film on a substrate, and forming a metal film for the emitter on the buffer film; Forming a mask pattern on the metal film; Etching the metal film to a predetermined thickness to form a neck portion of the emitter tip, and removing the mask pattern; Forming an amorphous silicon film for silicide on the metal film on which the neck of the emitter tip is formed; Forming a silicide film by reacting the metal film with the amorphous silicon film by a heat treatment to sharply form an emitter tip neck of the metal film; And removing the silicide film.

As such, the present invention is to form a tip sharply by a low-temperature silicide process, there is an advantage that the glass can be used with the substrate in addition to other processes, there is an advantage that can make a large area flat panel display at a low price. In addition, such a manufacturing method has the advantage of using the existing semiconductor process equipment and can be manufactured to be compatible with the integrated circuit manufacturing process.

4A to 4H and FIGS. 5A to 5H will be described in detail with reference to preferred embodiments of the present invention.

4A through 4H are cross-sectional views illustrating a method of manufacturing a field emission device according to an exemplary embodiment of the present invention, and illustrate a method of manufacturing a silicon or polycrystalline silicon emitter tip.

First, as shown in FIG. 4A, a silicon-based emitter conductive film 402 such as silicon, polysilicon, or amorphous silicon is deposited on the glass substrate 401 or a glass substrate including a resistive layer thereon. For example, a hard mask layer 403 such as an oxide film or a nitride film / oxide film / nitride film is deposited between 50 nm and 300 nm. The hard mask layer 403 maximizes the masking effect during silicon etching.

Subsequently, as illustrated in FIG. 4B, after defining the photoresist pattern 404 which is a tip mask pattern, the hard mask layer 403 is etched and patterned.

Subsequently, as shown in FIG. 4C, after the photoresist pattern 404 is removed, the emitter conductive layer 402 is isotropically etched using the patterned hard mask layer 403 as an etch mask or etched in two steps of isotropic / anisotropy. In order to form the neck of the emitter tip, when the etching is performed in two steps of isotropic / anisotropy, the remaining part of silicon to form the tip is controlled by adjusting the etching time of the first isotropic etching and the second anisotropy. The thickness of the neck and tip height can be adjusted independently of each other. In other words, using this two-step etching process, the tip can be made higher than the size of a given hard mask layer 403. If the tip is high, etch-back or chemical / mechanical polishing (to form the gate later) is performed. During the chemical mechanical polishing (CMP) process, the gate opening to be etched becomes uniform, the size of the electric field applied to the tip is increased, and the parasitic capacitance between the gate and the cathode is reduced, resulting in a RC delay of the device. It works in time. In addition, when the tip height is high, the thickness of the dielectric under the gate dielectric and the focusing electrode is increased to effectively prevent leakage current.

Subsequently, as shown in FIG. 4D, the hard mask 403 is etched, and, for example, silicides such as Ti, Co, Ta, Pd, Pt, W, Mo, and the like for silicide by e-beam or sputtering. Melting point metal layer 405 is deposited to a thickness of 10nm ~ 500nm. The thickness of this metal layer 5 determines the thickness of the silicide layer.

Subsequently, FIG. 4E shows that the metal layer 405 deposited on the emitter conductive film 402 is heat-treated using an electric furnace or rapid thermal annealing (RTP) equipment, for example, TiSi ₂ , CoSi, TaSi _2. The silicide layer 406 such as PdSi, PtSi, WSi, MoSi, or the like is formed to a thickness of 20 nm to 1000 nm. At this time, the silicon-based emitter conductive film 402 reacting with the high melting point metal layer becomes sharp at the tip of the neck.

Subsequently, as shown in FIG. 4F, the silicide layer 406 is removed by wet etching to expose the emitter tip 407. At this time, the silicide film is typically removed from the etchant. When the surface of the metal layer 405 is exposed to heat treatment for silicide formation, the surface of the metal layer 405 is oxidized to form a metal oxide layer. In the case, the silicide film is not removed by the metal oxide layer on the surface. Therefore, in FIG. 4E, preferably, a protective film (not shown) is formed at a low temperature of 400 ° C. or lower to prevent surface oxidation of the metal layer during heat treatment on the metal layer 405, and then heat treatment for silicide formation is performed. After that, the protective film and the silicide film are simultaneously or sequentially removed. In addition, a low work function material (not shown) such as metal, metal nitride, metal carbide, and diamond is coated on the emitter tip 407 exposed by the removal of the silicide film, thereby reducing the operating voltage of the tip. It can be unfamiliar and has the advantage of prolonging its life when used for a long time.

Subsequently, as shown in FIG. 4G, the gate insulating film 408 is formed to be 100 nm to 1000 nm by a plasma chemical vapor deposition method (PECVD) or a low pressure chemical vapor deposition method (LPCVD) capable of processing at a low temperature of 600 ° C. to 700 ° C. or less. At 409, a metal layer such as Ti, Co, Ta, W, Mo, Au, a silicide layer, or a polysilicon layer is formed.

Subsequently, as shown in FIG. 4H, the gate conductive layer 409 is etched by a chemical / mechanical polishing method or an etch-back method to etch a portion of the upper portion of the gate conductive layer protruding by the emitter tip. The wet-etched insulating film for the focusing electrode is partially etched to form a gate opening. A portion of the gate insulating film 408 is then wet etched to expose the tip, and then the gate conductive film is patterned and etched to complete the present structure.

5A to 5H are cross-sectional views illustrating a method of manufacturing a field emission device according to another exemplary embodiment of the present invention, illustrating a case of manufacturing a metal emitter tip.

First, FIG. 5A shows a buffer film 511 and a resistive layer (not shown) on the glass substrate 501, and then Ti, Co, Ta, Pd, Pt, W, Mo, etc. are deposited.

Next, as shown in FIG. 5B, a photoresist pattern 504 that is a tip mask pattern is defined.

Subsequently, as shown in FIG. 5C, the metal layer 505 is isotropically etched using the photoresist pattern 504 as an etch mask, or etching is performed in two steps of isotropic / anisotropy to form the neck of the emitter tip. The etching method has the advantage of independently controlling the thickness and tip height of the remaining portion (neck) of silicon where the tip will be formed by adjusting the etching time of the first step and the anisotropic step of the second step, respectively.

Subsequently, as shown in FIG. 5D, the photoresist pattern 504 is removed, and the amorphous silicon film 502 for silicide formation is formed by e-beam deposition, sputtering, plasma chemical vapor deposition (PECVD), etc. ˜500 nm deposition. The thickness of this amorphous silicon layer 502 will later determine the thickness of the silicide layer.

Subsequently, as shown in FIG. 5E, the amorphous silicon 502 film deposited on the metal layer 505 is heat-treated using an electric furnace or a rapid heat treatment equipment, thereby producing yarns such as TiSi ₂ , CoSi, TaSi ₂ , PdSi, PtSi, WSi, MoSi, and the like. The side layer 506 is formed to a thickness of 20 nm to 1000 nm. At this time, the tip of the neck of the metal layer becomes sharp.

Subsequently, as shown in FIG. 5F, the silicide 506 is etched away by wet etching to expose the metal emitter emitter tip 507. In this case, a low work function material (not shown) such as metal, metal nitride, metal carbide, and diamond is coated on the emitter tip 507 exposed by the removal of the silicide film, thereby reducing the operating voltage of the tip. It can be unfamiliar and has the advantage of prolonging its life when used for a long time.

Subsequently, as shown in FIG. 5G, the gate insulating film 508 is formed to have a thickness of 100 nm to 1000 nm by a plasma chemical vapor deposition method (PECVD) or a low pressure chemical vapor deposition method (LPCVD) that can be processed at a low temperature of 600 ° C. to 700 ° C. or less. As the conductive film 509, a metal layer, a silicide layer, or a polysilicon layer such as Ti, Co, Ta, W, Mo, Au, or the like is formed.

Subsequently, as shown in FIG. 5H, the gate conductive layer 509 is etched by a chemical / mechanical polishing method or an etch-back method to etch the upper portion of the gate conductive layer protruding from the emitter tip. The wet-etched insulating film for the focusing electrode is partially etched to form a gate opening. A portion of the gate insulating film 408 is then wet etched to expose the tip, and then the gate conductive film is patterned and etched to complete the present structure.

The present invention provides a method of sharply forming a silicon emitter tip or a metal emitter tip capable of emitting electrons to a field emission device using a silicide process at a low temperature. The emitter tip is sharp to facilitate field emission. In addition, the tip can be sharpened at a lower temperature than the conventional manufacturing method, and uniformity and symmetry are high, and an emitter tip can be formed on the glass plate. In addition, the present invention can not only vacuum-pack the fabricated array on a glass plate but also make a large area flat panel display at low cost.

Claims (19)

Forming a silicon based thin film on the substrate for the emitter; Forming a mask pattern on the silicon based thin film; Etching the silicon-based thin film to a predetermined thickness to form a neck portion of the emitter tip, and removing the mask pattern; Forming a high melting point metal film for silicide on the silicon-based thin film on which the neck of the emitter tip is formed; Forming a silicide film by reacting the silicon-based thin film with the metal film by heat treatment in order to sharply form an emitter tip neck of the silicon-based thin film; And Removing the silicide layer Field emission device manufacturing method comprising a. The method of claim 1, Sequentially forming a gate insulating film and a gate conductive film on the resultant of removing the silicide film; And And opening a predetermined portion of the gate insulating film and the gate conductive film thereon to expose the emitter tip having a sharp tip. The method of claim 1, Forming the mask pattern, Forming a hard mask thin film on the silicon based thin film; Forming a photoresist pattern on the hard mask thin film; And And etching the hard mask thin film using the photoresist pattern as an etching mask. The method of claim 3, The hard mask thin film is a field emission device manufacturing method characterized in that the oxide film or nitride film / oxide film / nitride film. The method of claim 1, Etching a predetermined thickness of the silicon-based thin film, A method for manufacturing a field emission device, characterized in that the thickness and height of the emitter tip neck are independently controlled by performing isotropic etching and anisotropic etching in sequence. The method of claim 1, The metal film is formed in a thickness of 10nm ~ 500nm and the silicide film is formed in a thickness of 20nm ~ 1000nm method of manufacturing a field emission device. The method of claim 2, And opening the predetermined portions of the gate insulating film and the gate conductive film by chemical / mechanical polishing or etch back. The method of claim 1, The substrate is a glass, or a field emission device manufacturing method characterized in that the glass comprising a resistance layer formed thereon. The method according to claim 1 or 2, Before the heat treatment step for forming the silicide, forming a protective film on the high melting point metal film to prevent oxidation of the surface of the high melting point metal film. The method of claim 9, The protective film is a field emission device manufacturing method characterized in that formed at 400 ℃ or less. The method of claim 1, And coating a low work function material on the pointed emitter tip of the silicon-based thin film exposed by removing the silicide film. Forming a metal film for the emitter on the substrate; Forming a mask pattern on the metal film; Etching the metal film to a predetermined thickness to form a neck portion of the emitter tip, and removing the mask pattern; Forming an amorphous silicon film for silicide on the metal film on which the neck of the emitter tip is formed; Forming a silicide film by reacting the metal film with the amorphous silicon film by a heat treatment to sharply form an emitter tip neck of the metal film; And Removing the silicide layer Field emission device manufacturing method comprising a. The method of claim 12, Sequentially forming a gate insulating film and a gate conductive film on the resultant of removing the silicide film; And And opening a predetermined portion of the gate insulating film and the gate conductive film thereon to expose the emitter tip having a sharp tip. The method of claim 12, And the mask pattern is a photoresist pattern. The method of claim 12, Etching the metal film a predetermined thickness, A method for manufacturing a field emission device, characterized in that the thickness and height of the emitter tip neck are independently controlled by performing isotropic etching and anisotropic etching in sequence. The method of claim 12, The amorphous silicon film is formed to a thickness of 10nm ~ 500nm and the silicide film is formed to a thickness of 20nm ~ 1000nm method of manufacturing a field emission device. The method of claim 12, And opening the predetermined portions of the gate insulating film and the gate conductive film by chemical / mechanical polishing or etch back. The method of claim 12, The substrate is a glass, or a field emission device manufacturing method characterized in that the glass comprising a buffer layer and a resistance layer formed thereon. The method of claim 12, And coating a low work function material on the pointed emitter tip of the metal film exposed by removing the seal side film.