JPH06275189A - Self-aligned gate structure and formation method of focusing ring - Google Patents

Abstract

PURPOSE: To provide a selective etching method and a chemical mechanical planarization method for the purpose of forming a self-aligned gate structure and a focusing ring around a pointed end of an electron emitter used for a field emission display. CONSTITUTION: (i) An end 13 of an electron emitter is pointed by oxidation when occasion demands, and (ii) a primary insulation layer 18 is accumulated, and (iii) a conduction layer 15 is accumulated, and (iv) a secondary insulation layer 14 is accumulated, (v) a focusing electrode ring layer 19 is accumulated, and (vi) a buffer material is accumulated when occasion demands, and (vii) a part of the secondary insulation layer 14 is exposed by being made flat with a process for a chemical mechanical planarization(CMP), and (viii) a self-aligned gate and a focusing ring 19 are formed by etching and accordingly the pointed end 13 of the emitter is exposed, and then (ix) the pointed end 13 of the emitter is covered with a material having a low work function.

Description

Detailed Description of the Invention

[0001]

[Industrial application] Gates and focusing rings (focus
ring) structure.

[0002]

BACKGROUND OF THE INVENTION Cathode Ray Tube (CRT) displays, such as those used in desktop computer screens, typically consist of electron guns impinging on phosphors on screens that are relatively far apart. It functions as a result of the scanning electron beam. The electrons increase the energy level of the phosphor. When the phosphor returns to its steady energy level, it emits energy from the electrons as photons, which are transmitted to the viewer through the glass screen of the display.

Flat panel displays are becoming more and more important in devices that require lightweight portable screens. Currently, such screens use electroluminescent or liquid crystal technology. A promising technology in the future is the use of matrix-addressable arrays of cold cathode emission devices that excite the phosphors on the screen.

"Display panel" by Wasa et al.
U.S. Pat. No. 3,875,442, entitled U.S. Pat. No. 3,875,442, is a transparent gas-tight envelope, a display consisting of two main planar electrodes arranged parallel to each other in the gas-tight envelope and a cathode-emitting panel. A panel is disclosed. One of the two main electrodes is the cold cathode and the other is the low potential anode, gate or grid. The cathode light emitting panel may include a transparent glass plate, a transparent electrode formed on the transparent glass plate, and a phosphor layer applied on the transparent electrode. The phosphor layer is composed of, for example, zinc oxide that can be excited by low energy electrons.

Spindt et al., US Pat.
No. 65,241, No. 3,755,704, No. 3,
Field emission cathode structures are disclosed in 812,559 and 4,874,981. To obtain the desired field emission, the potential source has its positive terminal connected to the gate or grid and its negative terminal connected to the emitter electrode (cathode conductor substrate). The potential source can be varied to control the electron emission current. Application of a potential between the electrodes creates an electric field between the tip of the emitter and the low potential anode grid, which causes electrons to be emitted from the cathode tip through the holes in the grid electrode. This structure is shown in FIG.

The array of points coincident with the holes in the low potential anode grid can be adapted to the fabrication of a cathode which is subdivided into regions containing one or more tips, from which regions an appropriate potential can be applied. Can be released separately.

The sharpness or resolution of a field emission display has several factors, such as the sharpness of the tip of the emitter, the alignment and spacing of the gate or grating openings surrounding it, the pixel size, and the cathode-gate and cathode-screen. Is a function of the voltage across. These factors are also interrelated. Another factor that affects image sharpness is the angle at which the emitted electrons strike the phosphor of the display screen.

The distance (d) that emitted electrons have to travel from the bottom plate to the face plate is typically on the order of a few hundred microns. The contrast and brightness of the display are optimal when the emitted electrons strike a phosphor located on the cathodoluminescent screen or faceplate at an angle of substantially 90 °. However, the contrast and brightness of the display are currently not optimal as the first electron trajectories emanating from the tip of the emitter are considered to be a substantially conical pattern with an apex angle of about 30 °. Moreover, the repulsive force of the clone is generated between the emitted electrons due to the space-charge effect, and the electron beam is further dispersed as shown in FIG.

US Pat. No. 5,070,282 entitled "Field Emission Electron Source" describes a "controlling electrode" located downstream of an "extracting electrode".
Is disclosed. U.S. Pat. No. 4,943,343, entitled "Self-Aligned Gate Process for Manufacturing Field Emissive Arrays," discloses the use of photoresist in the formation of self-aligned gate structures.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to improve image sharpness in flat panel displays by using self-aligned gate and focusing ring structures in the fabrication of cold cathode emitter tips. Chemical mechanical planarization (CMP) and selective etching techniques are basic elements of this manufacturing method. The focusing ring of the present invention is similar to the focusing structure of a CRT and is shown in FIG.
As can be seen, the beam collimates the emitted electrons and serves to impinge the beam on a smaller spot on the display screen.

One of the advantages of the method of the present invention is that the focusing ring can be incorporated into the cold cathode manufacturing process, which enhances the collimation of the electrons emitted from the tip of the cathode emitter and thus the display. The contrast and sharpness of the are improved.

Another advantage of the method according to the invention is that the focusing ring is manufactured in a self-aligned manner, which considerably reduces the process variations and the manufacturing costs. The method of the present invention will be better understood by reading the following description of non-limiting aspects with reference to the accompanying drawings. In the drawings, the same parts are indicated by the same numbers.

Referring to FIG. 1, a field emission display using cold cathodes is illustrated. Substrate 11 can be constructed of, for example, glass or any of a variety of other suitable materials. In the preferred embodiment, a single crystal silicon layer on which a conductor layer 12 such as doped polycrystalline silicon is deposited serves as the substrate 11.

At the field emission site, the micro cathode 13
A (also referred to herein as the tip of the emitter) is built on top of the substrate 11. The micro cathode 13 has various shapes,
For example, pyramids, cones or projections that are other shapes with fine micro dots for electron emission. A low potential anode gate structure 15 surrounds the microelectrode 13.

When a differential voltage is applied between the cathode 13 and the gate 15 by the potential source 20, the electron stream 17 is emitted toward the phosphor coated on the screen 16. The screen 16 functions as an anode. The electron stream 17 tends to diverge and becomes wider as the distance from the tip of the cathode 13 increases.

The electron emission tip 13 is integrated with the semiconductor substrate 11 and functions as a cathode conductor. The gate 15 acts as a grid structure for the low potential anode or its respective cathode 13. Dielectric insulating layer 14 is deposited on conductive cathode layer 12. The insulator 14 also has an opening at the field emission site.

The cathode structure of FIG. 2 is similar to that of FIG. However, a beam collimating focusing ring structure 19 made by the method of the present invention is also shown. Focusing ring 19 collimates the electron beam 17 emitted from each emitter 13 to reduce the area of the spot where the beam impinges on the phosphor coated on screen 16, thereby improving image resolution.

The present invention can be better understood with reference to FIGS. 3-10 which illustrate the initial, intermediate and final structures produced by the series of manufacturing steps of the present invention.

There are several methods of forming the tip 13 of the electron emitter used in the method of the present invention (step A in FIG. 10). An example of such a method is described in US Pat. No. 3,970,887 entitled "Microstructured Field Emission Electron Source".

In practice, a P-type silicon wafer has a series of elongated parallel extending opposite N-type conductive regions or wells formed therein (by suitable known doping pretreatment). ) Has. Each N-type conductive strip is about 10 microns wide and about 3 deep.
It is micron. The spacing between the strips is arbitrary and can be adjusted to accommodate a desired number of field emission cathode sites that can be formed on a silicon wafer substrate 11 of a predetermined size (P-type and N-type conductive regions). The processing of the substrate providing the substrate can be done by any well known semiconductor processing technique, such as diffusion and / or epitaxial growth). If desired, P-type and N-
The mold regions can be reversed by using a suitable substrate 11 and a suitable dopant.

The ion-implanted depression is the tip 1 of the emitter.
3 parts. The field emission cathode microstructure 13 can be manufactured using the semiconductor substrate 11. It is desirable that the semiconductor substrate 11 be P-type or N-type, and one of the surfaces thereof be selectively masked to form a field emission cathode site there. The masking is done in such a way that islands are defined on the surface of the semiconductor substrate 11 with the masked areas underneath. Then, by selectively removing the lateral side of the peripheral region surrounding the semiconductor substrate 11 below the end of the masked island region, the region immediately below each masked island region that defines a field emission cathode site is selected. The center is exposed in the region of and the tip 13 of the raised semiconductor field emitter is formed. Preferably, the removal of the underlying peripheral region surrounding the semiconductor substrate 11 is strictly controlled by the oxidation of the surface of the semiconductor substrate 11 surrounding the masked island region, the oxidation phase being below the peripheral edge of the masked region. It is long enough to promote lateral growth of some generated oxide layer, and long enough to leave only the non-oxidized tip 13 of the substrate 11 underneath the island mask. After that, the oxide film layer is selectively etched at least in the region directly surrounding the masked island region, and the center integrated with the underlying semiconductor substrate 11 is exposed at each desired field emission cathode portion, and the raised semiconductor is raised. The tip 13 of the field emitter is formed.

Before starting the gate formation process, the tip 13 of the electron emitter can be sharpened by an oxidation process (process A'in FIG. 8). The surfaces of the silicon wafer (Si) 11 and the tip 13 of the emitter are oxidized to form an oxide layer of SiO ₂ (not shown), which is then etched to sharpen the tip 13. Form SiO ₂ and tip 1
Any of the conventional and well known oxidation methods can be used to etch 3.

The next step (step B in FIG. 10) is the deposition of an insulator 18 that is selectively etchable with respect to the gate conductor 15. In a preferred embodiment, silicon dioxide layer 1
8 is used. Other suitable selectively etchable materials such as, but not limited to, silicon nitride and silicon oxynitride can also be used.

The thickness of the first insulating layer 18 is substantially the distance between the gate 15 and the cathode 13 and the thickness of the gate 15 and the substrate 11.
Both the interval between and. Therefore, the insulating layer 18 needs to be as thin as possible because the driving voltage of the emitter decreases when the distance between the gate 15 and the cathode 13 is small. at the same time,
The insulating layer 18 must be large enough to prevent the oxide film from breaking if the gate is not sufficiently separated from the cathode conductor 12.

As shown in FIG. 3, the oxide film insulating layer 18 is formed.
Is preferably a conformal insulating layer. The oxide film is deposited on the emitter tip 13 in such a way that the oxide layer 18 conforms to the shape of the cathode emitter tip 13.

The next step in the method (step C in FIG. 10) is the deposition of the gate conductor 15 (FIG. 3). The gate 15 is formed of the conductive layer 15. The conductor layer 15 may contain a metal such as chromium or molybdenum, but the preferred material for the present method is doped polysilicon or silicided polysilicon.

At this stage of manufacturing (step D of FIG. 10), the second insulating layer 14 is deposited (FIG. 3). The second insulating layer 14 is substantially the same as the first insulating layer 18, eg the layer 14 is also preferably conformal in nature. The second insulating layer 14 may also be composed of silicon dioxide, silicon nitride, silicon oxynitride and other suitable selectively etchable materials. The second insulating layer 14 is substantially the gate 1
The distance between 5 and the focusing ring 19 is defined (FIGS. 2 and 3).

In the next step of the method (step E of FIG. 10), the focusing electrode layer 19 is deposited (FIG. 3). Focusing ring 19 (FIG. 2) is formed from focusing electrode layer 19. Focusing electrode material layer 19 is also a conductive layer, which may be composed of a metal such as chromium or molybdenum, but as with gate conductor layer 15 the preferred material is doped polysilicon or silicided polysilicon. is there.

At this stage of manufacturing (step E'in FIG. 10), it is desirable for the portion of the underside of the focusing electrode material layer 19 during the next chemical mechanical polishing (CMP) step (step F in FIG. 10). A cushion 21 may be deposited to prevent non-etching. Note that the buffer layer 21 deposition is an optional step. Si is a suitable cushioning material
A thin layer of ₃ N ₄ or polyimide, or other suitable cushioning material known in the art is included. The nitride buffer layer 21 has the effect of increasing the strength of the tip 13, which is one of the advantages of performing this optional step. The buffer layer 21 substantially impedes the progress of CMP to the layer on which the buffer material 21 is deposited.

The step following the gate forming step (step F in FIG. 10) is the chemical mechanical planarization (CM).
P), which is also referred to in the art as chemical mechanical polishing (CMP). Cushioning and other layers that extend in front of the emitter tip 13 (eg, the apex of the focusing electrode layer 19, the conformal insulating layers 14, 18 and the gate conductive layer 15) are scraped off using chemical and polishing techniques. .

CMP generally involves holding or rotating a wafer of semiconductor material against a wet polishing surface under controlled chemical slurry, pressure and temperature conditions. A chemical slurry containing an abrasive such as alumina or silica can be used as the polishing medium.
Therefore, the chemical slurry may contain a chemical etchant. This operation is used to form a surface of desired endpoint or thickness, which has a polished and planarized surface. Such devices for polishing are disclosed in US Pat. Nos. 4,193,226 and 4,811,5.
No. 22. Another such device is manufactured by Westech Engineering and is referred to as the Model 372 Polisher.

CMP is performed over substantially the entire wafer surface and at high pressure. First, CMP
Moves very fast as the vertices are removed,
The speed is then considerably slower after the vertices are substantially removed. The removal rate of CMP is proportional to the pressure and hardness of the surface to be planarized.

FIG. 5 shows an intermediate step after the chemical mechanical planarization (CMP) in the step of forming the gate 15. A substantially planar surface is achieved, which exposes the second conformal insulating layer 14. At this point (step G in FIG. 10), various layers are selectively etched using any of the etching techniques known in the art, such as wet etching, to tip the emitter tip 1.
3 can be exposed to define the self-aligned gate 15 and focusing ring 19 structures. The order of layer removal can also be changed as a result of the CMP process.

In a preferred embodiment, the second insulating layer 14
Are selectively etched to expose gate 15. FIG. 5 shows the means by which the second conformal insulating layer 14 defines the spacing between the gate 15 and the focusing ring 19 and the means by which the gate 15 and the focusing ring 19 are self-aligned.

Next, as shown in FIG. 7, the gate material layer 1 is formed.
5 is etched. After the gate material layer 15 is removed, the first conformal insulating layer 18 covering the emitter tip 13 is exposed. The next step in the method is wet etching of the selectively etchable first insulating layer 18, exposing the tip 13 of the emitter. FIG. 7 shows the field emission device after the insulating cavity has been etched.

In another aspect (not shown), the gate material layer 15 may be removed first to expose the first insulating layer 18. Then, both the selectively etchable insulating layers 14 and 18 are simultaneously removed to remove the emitter tip 1.
3 can be exposed.

If desired, the cathode tip 13 may optionally be coated with a low work function material (step G'in FIG. 10). Cermet (Cr ₃ Si is used for low work function materials.
+ SiO ₂ ), cesium, rubidium, tantalum nitride,
Included, but not limited to, barium, chrome silicide, titanium carbide, molybdenum and niobium.

The coating of the tip of the emitter can be done in many ways. A low work function material or precursor thereof may be deposited on the tip 13 by sputtering or other suitable means. Certain metals (eg, titanium or chromium) react with the tip silicon during the rapid thermal processing (RTP) process to form silicide. After the RTP step, any unreacted metal is removed from the tip 13.
Under a nitrogen atmosphere, the deposited tantalum can be converted to tantalum nitride, a material with a particularly low work function, during RTP.

The variations of the coating process are almost limitless. As a result, the tip 13 of the emitter is not only sharper than a flat silicon tip, but also more erosion resistant and has a lower work function. In the annealing process, silicide is formed by the reaction between the refractory metal and the underlying polysilicon.

It will be apparent to those skilled in the art that the above manufacturing method is quite variable. For example, FIGS. 3A and 7A
, A continuous insulating layer 14, 1 prior to the CMP step (the relative level of the planarization step is shown in dashed lines).
Several focusing ring structures can be formed by adding 4a etc. and conductive layers 19, 19a etc. and then selectively etching each layer to expose the tip 13 of the emitter.

All of the above cited US patents are incorporated herein by reference. As exemplified herein,
It will be appreciated that the particular methods described in detail are merely representative of aspects of the invention and the invention is not limited thereto.

[0042]

As described above, according to the present invention,
Methods are provided for forming self-aligned gate and focusing ring structures at the tip of an emitter using chemical mechanical planarization (CMP) and selective etching techniques. Also, the use of self-aligning gates and focusing ring structures in the fabrication of cold cathode emitter tips improves the image clarity of flat panel displays.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a flat panel display showing a field emission cathode without the self-aligned focusing ring of the present invention.

2 is a cross-sectional view of the flat panel display of FIG. 1 further depicting the focusing ring structure of the present invention.

FIG. 3 is a cross-sectional view of a field emission cathode having a substantially conical emitter tip with a first insulating layer, a conductive layer, a second insulating layer, a focusing electrode layer and a buffer layer deposited thereon. .

4 is a cross-sectional view of the field emission cathode of FIG. 3 further depicting a plurality of insulating layers and focusing electrode layers.

Figure 5: Chemical mechanical planarization (CM
4 is a cross-sectional view of the multilayer structure of FIG. 3 after performing P).

FIG. 6 is a cross-sectional view of the structure of FIG. 5 after first etching.

7 is a cross-sectional view of the structure of FIG. 6 after the second etching.

8 is a cross-sectional view of the structure of FIG. 7 after etching.

9 is a cross-sectional view of the structure of FIG. 4 after etching.

FIG. 10 is a flow chart of steps involved in forming a self-aligned gate and focusing ring structure.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tyler A. Lowry United States, 83712 Idaho, Boyes, East Plato 2599 (72) Inventor David A. Cathay United States, 83703-6238 Idaho, Boise, Apartment 304, Wister Lane 3374 (72) Inventor Jay Brett Rolfson, 83709-7236, Hollylin Drive, Boyes, Idaho, USA 6225

Claims (10)

[Claims] 1. The next step is to planarize at least one electron emitter 13 overlaid with insulating layers 14, 18 and conductive layers 15, 19.
The planarization includes chemical mechanical means, and optionally the insulating layers 14, 18 and the conductive layers 15, 1
Removing 9 thereby exposing at least a portion of the electron emitter 13 to form a self-aligned gate 15 and a focusing ring 19 around the electron emitter 13. 2. The next step, at least one cathode 13 is formed on the substrate 11, at least two insulating layers 14 and 18 are formed on the cathode 13, and each of the insulating layers 14 and 18 is formed. On top of conductor layers 15, 1
9 is deposited, the layers 14, 15, 18, 19 are planarized by chemical mechanical planarization (CMP), and the layers 14, 15, 18, 19 are removed to expose at least a portion of the cathode 13. An electron emitter 1 including
A method of forming multi-grating structures 15 and 19 around 3. 3. Next step, forming at least one cathode 12 having a tip 13 of the emitter on the substrate 11, forming a first insulating layer 18 on the tip 13 of the emitter, and forming a conductive layer. 15 is deposited on the first insulating layer 18, a second insulating layer 14 is deposited on the conductive layer 15, and a focusing electrode layer 19 is deposited on the second insulating layer 14; , 15, 18, 19 are polished to form the conductive layer 1
Self-aligning gate around the electron emitter tip 13 including exposing at least a portion of 5 and selectively removing the layers 14, 15, 18, 19 to expose the tip 13 of the emitter. 15 and a method of forming the focusing ring 19 structure. 4. The next step is to process the wafer to form at least one cathode 12 having an emitter tip 13 on the substrate 11, depositing a first insulating layer 18 on the cathode 12, and conducting. A layer 15 is deposited on the first insulating layer 18, a second insulating layer 14 is deposited on the conductive layer 15, a focusing electrode layer 19 is deposited on the second insulating layer 14, and the wafer is Chemical mechanical planarization (C
MP) to expose at least a portion of the conductor layer 15, the layers 14 and 18 are etched to expose the tip 13 of the emitter, and the tip 13 is coated with a material having a low work function. A self-aligning gate 15 and a focusing ring structure around the cathode emitter 13. 5. The next step, forming at least one emitter tip 13 on the substrate 11, depositing at least two insulating layers 14, 18 on said tip 13 and at least two conductive layers. The layers 15 and 19 are connected to the insulating layer 14,
18 and the wafer is chemically mechanically planarized (C
MP) and the chemical mechanical planarization is performed using an abrasive compound in an abrasive slurry,
And forming a self-aligned gate 15 and focusing ring 19 structure around the cathode tip 13 including simultaneously etching the first and second insulating layers 14, 18 thereby exposing the tip 13 of the emitter. . 6. The next step, wafer processing to form at least one cathode 12 having a tip 13 of the emitter, said tip 13 being sharpened by oxidation and a first insulating layer 18 being provided on said tip 13. A conductive layer 15 is deposited on the first insulating layer 18, a second insulating layer 14 is deposited on the conductive layer 15, and a focusing electrode layer 19 is deposited on the second insulating layer 14. The wafer is deposited and the chemical mechanical planarization (C
MP) to expose at least a part of the second insulating layer 14, and the second insulating layer 14 is etched to form the conductive layer 15
A cavity is formed between the focusing electrode layer 19 and the focusing electrode layer 19, and the conductive layer 15 is etched to form a gate 15.
And removing at least a portion of the first insulating layer 18 surrounding the tip 13 thereby exposing the tip 13 to form a self-aligned gate 15 and focusing ring 19 structure around the electron emitter 13. Method. 7. The method according to claim 1, wherein the first and second insulating layers 14, 18 are selectively etchable with respect to the conductive layer 15 and the focusing electrode layer 19. 8. The buffer layer 2 prior to subjecting the wafer to a chemical mechanical planarization (CMP) process.
1 includes a step of depositing on the layer 19, the buffer material layer 21 The method of claim 6 any one of claims is made of a thin layer of Si ₃ N _4. 9. A method as claimed in any one of the preceding claims, wherein the tip 13 is incorporated into an array of similar tips 13, an optical display transmitter. 10. The method according to claim 1, wherein a plurality of said layers 19 and a plurality of said second insulating layers 14 are deposited.