KR19990009580A - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

The present invention relates to a device isolation method of a semiconductor device, comprising: forming a first mask layer on a semiconductor substrate, the first mask layer defining a wide area of the first device isolation region and a narrow area of the second device isolation region; Forming a second mask layer exposing the isolation region, forming a trench in the second device isolation region of the semiconductor substrate using the second mask layer as a mask, and a silicon layer filling the trench And forming a first field oxide film in the first device isolation region of the semiconductor substrate using the second mask layer as a mask and filling the trench in the second device isolation region. A step of forming a second field oxide film on the surface is provided. Therefore, the flatness of the surface can be improved irrespective of the area of the first and second device isolation regions, and the occurrence of the dishing phenomenon in the first device isolation region of the wide field region can be prevented.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method capable of preventing the active area from being reduced by preventing the device isolation region from increasing.

As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

In general, semiconductor devices have isolated devices by a local oxide of silicon (LOCOS) method. The LOCOS method is a device isolation region by forming and oxidizing a pad oxide film between the nitride film and the semiconductor substrate in order to solve the stress caused by the thermal characteristics of the nitride film and the semiconductor substrate, which are the oxide masks defining the active region. A field oxide film to be used is formed. Since the field oxide film is grown not only in the vertical direction of the semiconductor substrate but also in the oxidant (Oxidant: O ₂ ) in the horizontal direction along the pad oxide film, the field oxide film is grown under the pattern edge of the nitride film.

The phenomenon in which the field oxide film encroaches on the active region is called Bird's Beak because its shape is similar to that of a bird's beak. This bird beak is half the thickness of the field oxide film. Therefore, the length of the buzz bek should be minimized to reduce the size of the active area.

In order to reduce the length of the buzz beak, a method of reducing the thickness of the field oxide film was introduced. However, when the thickness of the field oxide film is reduced in the 16M DRAM class or higher, the capacitance between the wiring and the semiconductor substrate increases and the signal transmission speed decreases. Is generated. In addition, there is a problem that the threshold voltage Vt of the parasitic transistor formed in the isolation region between the elements is lowered by the wiring used as the gate of the element, thereby lowering the isolation characteristic between the elements.

Thus, a method for device isolation while reducing the length of the buzz bee has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the pad buffer oxide film is reduced and the polysilicon buffered polysilicon layer (PBLOCOS) between the semiconductor substrate and the nitride film and the sidewall of the pad oxide film are nitrided. There are shielded interface LOCOS (SILO) to protect, and recessed LOCOS techniques to form a field oxide film in a semiconductor substrate.

However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.

Accordingly, a BOX (buride oxide) trench trench isolation technology has been developed to overcome the problems of various device isolation technologies. BOX type device isolation technology A trench is formed in a semiconductor substrate and a coral film is buried by chemical vapor deposition (hereinafter referred to as CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.

1A to 1C are process diagrams illustrating a device isolation method according to the prior art.

Referring to FIG. 1A, a pad oxide film 13 is formed on a semiconductor substrate 11 by a thermal oxidation method, and a nitride film 15 is formed on the pad oxide film 13 by a CVD method. The device isolation region and the active region are defined by selectively removing the nitride layer 15 and the pad oxide layer 13 so that the semiconductor substrate 11 is exposed by photolithography.

Referring to FIG. 1B, a trench 17 is formed by dry etching the semiconductor substrate 11 exposed to the device isolation region and etching the semiconductor substrate 11 to a predetermined depth. Then, the oxide film 19 is deposited on the entire surface of the structure described above so as to fill the trench 17 by the CVD method. At this time, the trench 17 in the wide region is formed to be concave by the depth of the trench 17 because the oxide film 19 is deposited along the surface. Then, the planarization layer 21 is formed by applying a photosensitive film or SOG (Spin On Glass) to the surface of the oxide film 19.

Referring to FIG. 1C, the planarization layer 21 and the oxide film 19 may be formed by a reactive ion etching (hereinafter referred to as RIE) method or a chemical mechanical polishing (hereinafter referred to as CMP) method. Etch back so that the etching speed is the same. At this time, the nitride film 15 and the pad oxide film 13 are also removed to expose the semiconductor substrate 11 in the active region. The semiconductor substrate 11 of the exposed active region is thermally oxidized to form a gate oxide layer 23.

However, in the aforementioned device isolation method of the conventional semiconductor device, the oxide film and the planarization layer are not only uniformly applied in thickness depending on the degree of integration of the device, but the etching rates of the oxide film and the planarization layer are different from each other in the wide and narrow portions of the device isolation region. Since the surface is not completely flattened by the etch back process because it is different. In addition, a large amount of etching in a large field area than the narrow field area has a problem that the dishing (dishing) phenomenon occurs.

Accordingly, it is an object of the present invention to provide a device isolation method of a semiconductor device capable of improving the flatness of a surface even if the device isolation region is uneven in width.

Another object of the present invention is to provide a device isolation method for a semiconductor device which can prevent the phenomenon of digging in a wide field area.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first mask layer defining a wide area of a first device isolation region and a narrow area of a second device isolation region on a semiconductor substrate; Forming a second mask layer exposing the second device isolation region, forming a trench in the second device isolation region of the semiconductor substrate using the second mask layer as a mask, and forming the trench Forming a filling silicon layer, and forming a first field oxide film in the first device isolation region of the semiconductor substrate using the second mask layer as a mask to fill the trench in the second device isolation region. And forming a second field oxide film on the surface of the silicon layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are process diagrams illustrating a device isolation method of a semiconductor device according to the prior art.

2A to 2D are process diagrams showing a device isolation method according to the present invention.

2A to 2D are manufacturing process diagrams of a semiconductor device according to the present invention.

Referring to FIG. 2A, a pad oxide film 23 having a thickness of about 80 to 150 GPa is formed on the semiconductor substrate 21 by a thermal oxidation method, and a thickness of about 1000 to 1500 GPa is formed on the pad oxide film 23 by a CVD method. The nitride film 25 is formed. The nitride layer 25 is patterned by a photolithography method so that the pad oxide layer 13 is exposed, and the device isolation region includes a first device isolation region 11 having a large area and a second device isolation region 12 having a small area. And the active area.

2B, silicon oxide is deposited on the pad oxide film 23 and the nitride film 25 by a bias-electron cyclotron resonance (hereinafter referred to as ECR) CVD method, which is one of the CVD methods. The mask layer 37 is formed. The layer formed by the bias-ECR CVD method has a pattern effect in which a thick pattern is formed in a large pattern area and a thin pattern is formed in a small pattern area.

Therefore, the mask layer 37 is thickly formed in the first device isolation region I1 and thinly formed in the second device isolation region I2.

The mask element 37 is exposed to the second device isolation region I2 by a reactive ion etching method (hereinafter referred to as RIE). At this time, the mask layer 37 in the first device isolation region I1 is not removed and remains.

Using the mask layer 37 remaining in the first device isolation region I1 as a mask, the pad oxide film 33 in the second device isolation region I2 was removed, and then subjected to an anisotropic etching method such as reactive ion etching. A trench 39 of depth is formed.

The diffusion barrier layer 41 is formed on the inner surface of the trench 39 by a thermal oxidation method.

Referring to FIG. 2C, the mask layer 39 remaining in the first device isolation region I1 is removed. Then, the silicon layer 43 is formed by depositing polysilicon or amorphous silicon that is not doped with impurities so as to fill the trench 39 on the pad oxide film 33 and the nitride film 35 by the CVD method. The silicon layer 43 is etched back so as to remain only in the trench 39. At this time, since the silicon layer 43 remains only in the trench 39 formed in the second device isolation region I2 having a narrow area, it is possible to prevent the occurrence of the dipping phenomenon.

Referring to FIG. 2D, the first device isolation region I1 is oxidized on the semiconductor substrate 31 using the nitride film 35 as a mask to form the first field oxide film 45. At this time, the surface of the silicon layer 43 filling the trench 39 in the second device isolation region I2 is also oxidized to form a second field oxide film 47. The first field oxide layer 45 is formed by thermal oxidation in the first device isolation region I1 having a large area, and the surface of the silicon layer 43 in the second device isolation region I2 is thermally oxidized. Since the second field oxide film 47 is formed, the flatness of the surface can be improved regardless of the device integration area and the area of the device isolation region. The nitride film 35 and the pad oxide film 33 are removed to expose the active region of the semiconductor substrate 31, and then thermally oxidized to form the gate oxide film 49.

Therefore, the present invention can improve the flatness of the surface irrespective of the area of the first and second device isolation regions, and can prevent the phenomenon of digging in the first device isolation region of the wide field region. There is an advantage.

Claims (3)

Forming a first mask layer defining a wide area of the first device isolation region and a narrow area of the second device isolation region on the semiconductor substrate; Forming a second mask layer exposing the second device isolation region; Forming a trench in the second device isolation region of the semiconductor substrate using the second mask layer as a mask; Forming a silicon layer filling the trench; A second field is formed on the surface of the silicon layer filling the trench in the second device isolation region while forming a first field oxide film in the first device isolation region of the semiconductor substrate using the second mask layer as a mask. A semiconductor device manufacturing method comprising the step of forming an oxide film. The method of claim 1, wherein the step of forming the second mask layer, Depositing silicon oxide to be thickly formed in the first device isolation region and thinly formed in the second device isolation region; And etching back the silicon oxide to expose the second device isolation region. The method according to claim 1, A method for manufacturing a semiconductor device in which the silicon oxide is deposited by a bias-electron cyclotron resonance chemical vapor deposition method.