KR19980034610A - Device isolation method of semiconductor device - Google Patents

Abstract

The present invention relates to a device isolation method for a semiconductor device, comprising: forming a pad oxide film, a nitride film, and a silicon layer on a predetermined portion of a semiconductor substrate to define an active region; and forming a first thermal oxide film on an exposed portion of the semiconductor substrate. Simultaneously oxidizing the silicon layer to form a second thermal oxide film, laterally etching the nitride film under the second thermal oxide film to define an active region of the device, and removing the second thermal oxide film and simultaneously (1) removing a predetermined thickness of the thermal oxide film and an exposed portion of the pad oxide film; forming a trench in the exposed portion of the semiconductor substrate using the nitride film and the remaining first thermal oxide film as a mask; A step of forming an oxide film to be filled is provided. Therefore, since the active area is limited to one photolithography process, the process is simple, and the same planar area of the trench can be used to improve the flatness of the surface regardless of the integration and device isolation area of the device when etching back. have.

Description

Device isolation method of semiconductor device

1 (A) to (C) are process drawings showing a device isolation method according to the prior art.

2 (A) to (E) is a process chart showing a device isolation method according to an embodiment of the present invention

3A to 3C are process diagrams showing a device isolation method according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

31: semiconductor substrate 33: pad oxide film

35: nitride film 37: silicon layer

39, 41: first and second thermal oxide films

43: trench 47: gate oxide film

45, 49, 53: oxide film 51: silicon layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method capable of preventing an active area from being reduced by preventing the device isolation area from increasing.

As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

In general, semiconductor devices have isolated devices by a local oxide of silicon (LOCOS) method. The LOCOS method is a device isolation region by forming and oxidizing a pad oxide film between the nitride film and the semiconductor substrate in order to solve the stress caused by the thermal characteristics of the nitride film and the semiconductor substrate, which are the oxide masks defining the active region. A field oxide film to be used is formed. The field oxide film is not only grown in a vertical direction of the semiconductor substrate but also has an oxide (Oxidant: O ₂ ) diffused in the horizontal direction along the pad oxide film, so that the field oxide film is grown under the pattern edge of the nitride film.

The phenomenon of the field oxide film encroaching on the active region is called Bird's Beak because its shape is similar to that of a bird's beak. This bird beak is half the thickness of the field oxide film. Therefore, the length of the buzz bek should be minimized to reduce the size of the active area.

In order to reduce the length of the buzz beak, a method of reducing the thickness of the field oxide film was introduced. However, in the case of 16M DRAM or higher, reducing the thickness of the field oxide film increases the capacitance between the wiring and the semiconductor substrate, thereby decreasing the signal transmission speed. A problem arises. In addition, the threshold voltage (Vt) of the parasitic transistor formed in the isolation region between the elements is lowered by the wiring used as the gate of the element is a problem that the isolation characteristic between the elements is reduced.

Thus, a method for device isolation while reducing the length of the buzz bee has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the pad buffer oxide film is reduced and the polysilicon buffered polysilicon layer (PBLOCOS) between the semiconductor substrate and the nitride film and the sidewall of the pad oxide film are nitrided. Shielded Interface LOCOS (SILO), and Recessed Oxide LOCOS technologies that form field oxide films in semiconductor substrates.

However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.

Therefore, a buried oxide (BOX) type trench isolation technology has been developed that can overcome the problems of various device isolation techniques. BOX type device isolation technology A trench is formed in a semiconductor substrate and an oxide film is buried by chemical vapor deposition (CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.

1 (A) to (C) are process diagrams showing a device isolation method according to the prior art.

Referring to FIG. 1A, the pad oxide film 13 is formed on the semiconductor substrate 11 by the thermal oxidation method, and the nitride film 15 is formed on the pad oxide film 13 by the CVD method. The device isolation region and the active region are defined by selectively removing the nitride layer 15 and the pad oxide layer 13 so that the semiconductor substrate 11 is exposed by photolithography.

Referring to FIG. 1B, a trench 19 is formed by dry etching the semiconductor substrate 11 exposed to the device isolation region and etching the semiconductor substrate 11 to a predetermined depth. Then, an oxide film 17 is deposited on the entire surface of the above-described structure so that the CVD method trench 19 is filled. At this time, since the oxide film 17 is uniformly deposited on the surface of the trench 19 in the wide region, the oxide film 17 is formed to be concave as much as the depth of the trench 17. Then, the planarization layer 21 is formed by applying a photosensitive film or spin on glass (SOG) to the surface of the oxide film 17.

Referring to FIG. 1 (C), the planarization layer 21 and the oxide film (reactive ion etching (hereinafter referred to as RIE) method or chemical mechanical polishing (hereinafter referred to as CMP) method are used. The etching rate of 19) is etched back to expose the semiconductor substrate 11 in the active region. The semiconductor substrate 11 of the exposed active region is thermally oxidized to form a gate oxide layer 23.

However, the device isolation method of the conventional semiconductor device described above has a problem that the process is complicated because two photolithography processes have to be performed to form trenches and planarize the oxide film. The oxide film and the planarization layer are not only unevenly coated according to the degree of integration of the device, but the etching rate is different between the oxide film and the planarization layer in the wide and narrow parts of the device isolation region. There was a problem.

Accordingly, an object of the present invention is to provide a method for isolating a device of a semiconductor device, in which the process is simplified since the first photolithography process for defining the active region is performed.

Another object of the present invention is to provide a device isolation method of a semiconductor device capable of improving surface flatness regardless of device integration and device isolation area.

The device isolation method of the semiconductor device according to the present invention for achieving the above object is a step of forming a pad oxide film, a nitride film and a silicon layer on a predetermined portion on the semiconductor substrate to define the active region, and Forming a second thermal oxide film by simultaneously oxidizing a silicon layer and forming a second thermal oxide film, laterally etching the nitride film under the second thermal oxide film to define an active region of the device, and the second thermal oxide film. Simultaneously removing the predetermined thickness of the first thermal oxide film and the exposed portion of the pad oxide film, and forming a trench in the exposed portion of the semiconductor substrate using the nitride film and the remaining first thermal oxide film as a mask. And forming an oxide film so that the trench is filled.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are process diagrams showing a device isolation method according to an embodiment of the present invention.

Referring to FIG. 2A, the pad oxide film 33 is formed on the semiconductor substrate 31 by a thermal oxidation method to a thickness of about 100 to about 200 microseconds. The nitride film 35 is formed on the pad oxide film 33 by a low pressure CVD method to a thickness of 1000 to 1500 kPa. Next, polysilicon or amorphous silicon is deposited on the nitride film 35 to a thickness of about 50 to 1000 Å to form a silicon layer 37. The silicon layer 37, the nitride film 35, and the pad oxide film 33 of the predetermined portion are removed by a photolithography method to expose the semiconductor substrate 31 to define the device isolation region and the active region. At this time, the active region is limited to 500 to 1000 넓 wider than the width of the active region of the actual device.

Referring to FIG. 2B, the exposed portion of the semiconductor substrate 31 is thermally oxidized to form the first thermal oxide film 39. At this time, the silicon layer 37 is oxidized on the nitride film 35 to form a second thermal oxide film 41. In the above, the second thermal oxide film 41 is formed to a thickness of about 100 to 2000 microseconds so that the silicon layer 37 is completely oxidized, and the first thermal oxide film 39 is about 200 to 4000 microns thicker than the second thermal oxide film 41. It is formed to the thickness of. The nitride film 35 is laterally etched with phosphoric acid (H ₃ PO ₄ ) to a width of about 500 to 1000 Å to define the active region of the actual device.

Referring to FIG. 2C, the second thermal oxide film 41 on the nitride film 35 is removed with hydrofluoric acid (HF). At this time, the thickness of the first thermal oxide film 39 is also removed, as well as the exposed portion of the pad oxide film 33 is removed. Then, using the nitride film 35 and the remaining first thermal oxide film 39 as a mask, the exposed portion of the semiconductor substrate 31 is trench 43 having a depth of about 4000 ~ 7000Å by an anisotropic etching method such as RIE. To form.

Referring to FIG. 2D, the oxide film 45 is formed by the CVD method so that the trench 43 is filled in the entire surface of the above-described structure. The remaining oxide film 45 is etched and removed except for filling the trench 43 by a dry etching method including an isopic component and an isotropic component. At this time, since the planar area of the trench 43 is the same, the oxide film 45 may be etched at the same speed to improve flatness regardless of the integration degree of the device.

Referring to FIG. 2E, the nitride film 35 and the pad oxide film 33 are sequentially removed to expose the semiconductor substrate 31 in the active region. The exposed portion of the semiconductor substrate 31 is thermally oxidized to form a gate oxide film 47.

3A to 3C are process diagrams showing a device isolation method according to another embodiment of the present invention. In the device isolation method according to another embodiment of the present invention, since the process before FIG. 3A is the same as the process of FIGS. 2A and 2B, the same reference numerals are used for the same parts.

Referring to FIG. 3A, the second thermal oxide film 41 on the nitride film 35 is removed with hydrofluoric acid (HF). At this time, the thickness of the first thermal oxide film 39 is also removed, as well as the exposed portion of the pad oxide film 33 is removed. Then, using the nitride film 35 and the remaining first thermal oxide film 39 as a mask, the exposed portion of the semiconductor substrate 31 is trench 43 having a depth of about 4000 ~ 7000Å by an anisotropic etching method such as RIE. To form. Next, a thin oxide film 49 is formed on the inner surface of the trench 43 by a thermal oxidation method.

Referring to FIG. 3B, the silicon layer 51 is formed by depositing polysilicon or amorphous silicon by CVD to fill the trench 43 on the entire surface of the structure described above. The remaining silicon layer 51 is etched and removed except for filling the trench 43 by a dry etching method including an isopic component and an isotropic component. At this time, since the planar area of the trench 43 is the same, the silicon layer 51 may be etched at the same speed to improve flatness regardless of the integration degree of the device.

Referring to FIG. 3C, the surface of the silicon layer 51 in the trench 43 is thermally oxidized to form the oxide film 53. At this time, since the volume of the oxide film 53 is increased and the step difference with the first thermal oxide film 39 is reduced, the flatness of the surface is increased. The nitride film 35 and the pad oxide film 33 are sequentially removed to expose the semiconductor substrate 31 in the active region. Next, the exposed portion of the semiconductor substrate 31 is thermally oxidized to form a gate oxide film 47. The oxide film 53 may be formed at the same time as the gate oxide film 47 after the nitride film 35 and the pad oxide film 33 are removed.

As described above, the device isolation method according to the present invention forms a pad oxide film, a nitride film, and a silicon film on a semiconductor substrate by a thermal oxidation method, and a semiconductor such that the active area is wider than the active area of the actual device by a photolithography method. After exposing the substrate, a first thermal oxide film is formed on the exposed portion of the semiconductor substrate and the nitride film is laterally etched to define the active region of the actual device. Using the nitride film and the first thermal oxide film as a mask, anisotropic etching of the exposed portion of the semiconductor substrate is performed to form a trench, and an oxide film or a silicon layer is formed to fill the trench on the entire surface, and then the rest is etched except for filling the trench. Remove it by white.

Therefore, since the active area is limited to one photolithography process, the process is simple, and the same planar area of the trench can be used to improve the flatness of the surface regardless of the integration and device isolation area of the device when etching back. There is an advantage.

Claims (11)

Forming a pad oxide film, a nitride film and a silicon layer on a predetermined portion of the semiconductor substrate to define an active region; Forming a first thermal oxide film on the exposed portion of the semiconductor substrate and oxidizing a silicon layer to form a second thermal oxide film; Defining the active region of the device by laterally etching the nitride film under the second thermal oxide film; Removing the second thermal oxide film and simultaneously removing a predetermined thickness of the first thermal oxide film and an exposed portion of the pad oxide film; Forming a trench in the exposed portion of the semiconductor substrate using the nitride film and the remaining first thermal oxide film as a mask; And forming an oxide film so that the trench is filled. The method of claim 1, A device isolation method for a semiconductor device, wherein the silicon layer is formed of polycrystalline silicon or amorphous silicon. The method of claim 2, A device isolation method for forming a semiconductor device, the silicon layer having a thickness of 50 ~ 1000 50. The method of claim 1, A method of isolating a semiconductor device, wherein the yellow region is defined to be 500 to 1000 microns wider than the active region of the device. The method of claim 1, The method of claim 1, wherein the first thermal oxide film is formed thicker than the second thermal oxide film. The method of claim 5, A method of isolating a semiconductor device, wherein the first thermal oxide film is formed to a thickness of 200 to 4000 GPa and the second thermal oxide film is formed to a thickness of 100 to 2000 GPa. The method of claim 1, A device isolation method for forming a semiconductor device with a depth of 4000 to 7000 Å. Forming a pad oxide film, a nitride film and a silicon layer on a predetermined portion of the semiconductor substrate to define an active region; Forming a first thermal oxide film on the exposed portion of the semiconductor substrate and oxidizing a silicon layer to form a second thermal oxide film; Defining the active region of the device by laterally etching the nitride film under the second thermal oxide film; Removing the second thermal oxide film and simultaneously removing a predetermined thickness of the first thermal oxide film and an exposed portion of the pad oxide film; Forming a trench in the exposed portion of the semiconductor substrate using the nitride film and the remaining first thermal oxide film as a mask; Forming an oxide film on the inner surface of the trench and forming a silicon layer on the oxide film to fill the trench. The method of claim 8, And depositing and etching back polycrystalline silicon or amorphous silicon on the oxide film to form a silicon layer filling the trench. The method of claim 9, Oxidizing the surface of the silicon layer; Removing the nitride film and the pad oxide film to expose the semiconductor substrate; And forming a gate oxide film on the exposed portion of the semiconductor substrate. The method of claim 10, Removing the nitride film and the pad oxide film to expose the semiconductor substrate; And forming a gate oxide film on the exposed portion of the semiconductor substrate and simultaneously oxidizing the surface of the silicon layer.