KR19990006064A - Method of forming interlayer insulating film of semiconductor device - Google Patents
Method of forming interlayer insulating film of semiconductor device Download PDFInfo
- Publication number
- KR19990006064A KR19990006064A KR1019970030286A KR19970030286A KR19990006064A KR 19990006064 A KR19990006064 A KR 19990006064A KR 1019970030286 A KR1019970030286 A KR 1019970030286A KR 19970030286 A KR19970030286 A KR 19970030286A KR 19990006064 A KR19990006064 A KR 19990006064A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- interlayer insulating
- semiconductor device
- forming
- forming interlayer
- Prior art date
Links
Abstract
본 발명은 반도체소자의 층간절연막 형성방법에 관한 것으로, 반도체소자에 구비되는 도전층 간의 층간절연막을 형성하는 방법에 있어서, TEOS 액체와 C2F6가스를 이용한 PECVD 공정으로 저유전율을 가지며 단차피복성이 양호하고 습기에 강한 층간절연막을 형성하여 후속공정을 용이하게 함으로써 소자의 특성 및 신뢰성을 향상시키고 반도체소자의 수율 및 생산성을 향상시키며 그에 따른 소자의 고집적화을 가능하게 하는 기술이다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, the method of forming an interlayer insulating film between conductive layers included in a semiconductor device, the PECVD process using a TEOS liquid and C 2 F 6 gas has a low dielectric constant and step By forming an interlayer insulating film having good properties and moisture resistance, the subsequent process is facilitated, thereby improving the characteristics and reliability of the device, improving the yield and productivity of the semiconductor device, and thereby enabling high integration of the device.
Description
본 발명은 반도체소자의 층간절연막 형성방법에 관한 것으로, 특히 미세패턴간의 공정을 평탄화시켜 후속공정을 용이하게 실시할 수 있도록 우수한 단차피복성(step-coverage)과 저유전율을 갖는 층간절연막을 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and in particular, to form an interlayer insulating film having excellent step-coverage and low dielectric constant so as to planarize a process between fine patterns so that subsequent processes can be easily performed. It's about technology.
종래 금속배선 간의 절연막은 화학기상증착 (Chamical Vapor Deposition, 이하에서 CVD 라 함) 방법에 의한 산화막 또는 상기 산화막에 B, P 등의 불수물을 첨가한 비.피.에스.지. (Boro Phospho Silicate Glass, 이하에서 BPSG라 함)절연막을 사용하였다.Conventionally, an insulating film between metal wirings is an oxide film by chemical vapor deposition (CVD), or B.P.G. (Boro Phospho Silicate Glass, hereinafter referred to as BPSG) An insulating film was used.
그러나, 상기와 같은 막들은 공정 진행 중 많은 파티클(particle)을 동반하거나, 고집적 소자가 요구하는 정도의 유전율은 갖고 있지 못해서, 이를 해결할 수 있는 새로운 방법이 갈수록 더욱 절실해 지고 있다.However, such films do not have a large amount of particles during the process or do not have the dielectric constant required by the high-density device, and new methods for solving these problems are increasingly needed.
그리하여, 최근에는 절연막을 형성할때, 단차피복성을 향상시키기 위하여 에.스.오.지.(Spin On Glass, 이하에서 SOG라 함)용액을 이용하였으나, 이 용액을 이용한 막은 습기에 대단히 약하여 보우잉(bowing) 현상이 유발되어 소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.Therefore, in recent years, when forming an insulating film, a solution of spin on glass (hereinafter referred to as SOG) has been used to improve step coverage, but the film using this solution is very weak to moisture. Bowing phenomenon is caused to deteriorate the characteristics and reliability of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 단차피복성이 우수하고, 습기에 강하며 저유전율을 갖는 절연막을 형성하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 층간절연막 형성방법을 제공하는 데 그 목적이 있다.In order to solve the above problems of the related art, an interlayer insulating film of a semiconductor device can be formed to improve the characteristics and reliability of the semiconductor device by forming an insulating film having excellent step coverage, resistant to moisture, and having a low dielectric constant. The purpose is to provide a method.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 층간절연막 형성 방법은,In order to achieve the above object, an interlayer insulating film forming method of a semiconductor device according to the present invention,
반도체소자에 구비되는 도전층 간의 층간절연막을 형성하는 방법에 있어서,In the method of forming an interlayer insulating film between conductive layers provided in a semiconductor device,
TEOS액체와 C2H6가스를 이용한 PECVD공정으로 층간절연막을 형성하는 것을 특징으로 한다.An interlayer insulating film is formed by a PECVD process using TEOS liquid and C 2 H 6 gas.
한편, 이상의 목적을 달성하기 위한 본 발명의 원히는, TEOS 액체에 C2F6가스를 이용하여 PECVD 방법으로 절연막을 형성함으로써 습기에 강하며, 우수한 단차피복성을 가지며, C2F6가스 첨가로 저 유전율을 갖는 절연막을 형성하여 결함없는 소자를 형성할 수 있도록 함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있도록 하는 것이다.On the other hand, the present invention for achieving the above object is resistant to moisture by forming an insulating film by PECVD method using C 2 F 6 gas in TEOS liquid, has excellent step coverage, addition of C 2 F 6 gas By forming an insulating film having a low dielectric constant to form a defect-free device, it is possible to improve the characteristics and reliability of the semiconductor device.
이하, 도시되진 않았으나 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, although not shown, embodiments of the present invention will be described in detail.
먼저, 반도체기판 상부에 하부구조물을 형성하고 그 상부를 평탄화시키는 하부절연막을 형성한다. 이때, 상기 하부구조물은 소자분리막, 워드라인, 비트라인 또는 캐패시터를 말한다.First, a lower insulating layer is formed on the semiconductor substrate and the top of the lower substrate is planarized. In this case, the substructure refers to an isolation layer, a word line, a bit line, or a capacitor.
그 다음에, 금속배선 형서공정으로 제 1금속배선을 형성한다.Next, the first metal wiring is formed by a metal wiring forming process.
그리고, 상기 제 1금속배선이 형성된 반도체기판의 전체요면상부에 층간절연막을 형성한다.An interlayer insulating film is formed over the entire surface of the semiconductor substrate on which the first metal wiring is formed.
이 때, 상기 층간절연막은 TEOS : 1~2sccm, O2: 4~6sccm, 온도 : 300~500℃ , 두께 : 6000~10000Å , C2F6: 3~5sccm,전력 : 0.3~0.6의 HF와 0.3~0.6의 LF로 하는 조건으로 형성된다.At this time, the interlayer insulating film is TEOS: 1 ~ 2sccm, O 2 : 4 ~ 6sccm, temperature: 300 ~ 500 ℃, thickness: 6000 ~ 10000Å, C 2 F 6 : 3 ~ 5sccm, power: 0.3 ~ 0.6 HF It is formed under the condition of LF of 0.3-0.6.
그 다음에, 상기 층간절연막 상부에 제 2금속배선을 형성한다.Next, a second metal wiring is formed on the interlayer insulating film.
아울러, 상기 본 발명의 실시예와 같이 형성된 층간절연막은, 금속배선 간의 층간절연 뿐만 아니라 각각의 도전층 사이를 매립하여 소자의 특성을 향상시키는데 사용될 수 있다.In addition, the interlayer insulating film formed as in the embodiment of the present invention may be used to improve the characteristics of the device by filling the gaps between the conductive layers as well as the interlayer insulation between the metal wires.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 층간절연막 형서방법은, 반도체소자의 도전층 사이에 단차피복성이 양호하고, 습기에 강하며 저유전율을 갖는 절연막을 층간절연막으로 형성하여 후속공정을 용이하게 함으로써 소자의 득성 및 신뢰성을 향상시키고 그에 따른 소자의 고집적화를 가능하게 하는 효과가 있다.As described above, the method for forming an interlayer insulating film of a semiconductor device according to the present invention comprises forming an insulating film having good step coverage, resisting moisture, and having a low dielectric constant as an interlayer insulating film between conductive layers of the semiconductor device. By making it easy, there is an effect of improving the profitability and reliability of the device and thereby enabling high integration of the device.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970030286A KR19990006064A (en) | 1997-06-30 | 1997-06-30 | Method of forming interlayer insulating film of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970030286A KR19990006064A (en) | 1997-06-30 | 1997-06-30 | Method of forming interlayer insulating film of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR19990006064A true KR19990006064A (en) | 1999-01-25 |
Family
ID=66039014
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970030286A KR19990006064A (en) | 1997-06-30 | 1997-06-30 | Method of forming interlayer insulating film of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR19990006064A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5324690A (en) * | 1993-02-01 | 1994-06-28 | Motorola Inc. | Semiconductor device having a ternary boron nitride film and a method for forming the same |
JPH06240459A (en) * | 1993-02-16 | 1994-08-30 | G T C:Kk | Formation of silicon oxide thin film |
KR960032641A (en) * | 1995-02-17 | 1996-09-17 | 세키사와 다다시 | Semiconductor device and method of forming insulating film |
JPH1064899A (en) * | 1996-08-16 | 1998-03-06 | Nec Corp | Plasma cvd insulating film and its formation method |
-
1997
- 1997-06-30 KR KR1019970030286A patent/KR19990006064A/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5324690A (en) * | 1993-02-01 | 1994-06-28 | Motorola Inc. | Semiconductor device having a ternary boron nitride film and a method for forming the same |
JPH06240459A (en) * | 1993-02-16 | 1994-08-30 | G T C:Kk | Formation of silicon oxide thin film |
KR960032641A (en) * | 1995-02-17 | 1996-09-17 | 세키사와 다다시 | Semiconductor device and method of forming insulating film |
JPH1064899A (en) * | 1996-08-16 | 1998-03-06 | Nec Corp | Plasma cvd insulating film and its formation method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6214719B1 (en) | Method of implementing air-gap technology for low capacitance ILD in the damascene scheme | |
JP4733261B2 (en) | Method for reducing unwanted insulator etching due to increased boron concentration | |
US6057226A (en) | Air gap based low dielectric constant interconnect structure and method of making same | |
US6187662B1 (en) | Semiconductor device with low permittivity interlayer insulating film and method of manufacturing the same | |
JP2003045959A (en) | Semiconductor device and method of manufacturing same | |
US20060166514A1 (en) | TEOS deposition method | |
KR19990006064A (en) | Method of forming interlayer insulating film of semiconductor device | |
US20020000664A1 (en) | Silicon nitride composite hdp/cvd process | |
KR19990054912A (en) | Method of forming interlayer insulating film of semiconductor device | |
US6358845B1 (en) | Method for forming inter metal dielectric | |
JPH04311059A (en) | Decreasing method of wiring capacity | |
KR100905828B1 (en) | Metal line of semiconductor device and forming method thereof | |
KR100399903B1 (en) | Interlayer planarization method of semiconductor device | |
JP4747755B2 (en) | Organic insulating film, manufacturing method thereof, and semiconductor device using organic insulating film | |
KR0149468B1 (en) | A method for forming a semiconductor device | |
KR100567021B1 (en) | Method for forming inter metal dielectric layer utilizing FSG material | |
KR100588636B1 (en) | Method for manufacturing inter-metal dielectric layer of the semiconductor device | |
KR100367499B1 (en) | Method for manufacturing semiconductor device | |
KR100331272B1 (en) | Formation method of inter layer dielectric in semiconductor device | |
KR100392896B1 (en) | Method for forming a semiconductor metal line | |
KR100257151B1 (en) | Method of forming intermetal dielectrics of semiconductor device | |
KR20040059466A (en) | Method for forming gap fill of metal line for semiconductor | |
KR100717823B1 (en) | Method for forming inter metal dielectric layer in semiconductor device | |
KR100459063B1 (en) | Method for manufacturing intermetal dielectric layer of semiconductor device | |
KR100552810B1 (en) | Metal line formation method of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |