KR19990005854A - Repair circuit - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

The present invention relates to a repair circuit capable of electrically checking whether a repair is performed when a defective cell of a memory device is repaired into a redundant cell.

2. Technical problem that the invention tries to solve

This is to solve the difficulty of checking whether there is a repair due to the defective open of the poly fuse.

3. Summary of the solution of the invention

A first and second NMOS transistors are connected in series between the power supply terminal and the first node, and a PMOS transistor having an output signal of the control circuit as an input is connected between the first node and the write enable pad to check whether the repair is possible. box.

4. Important uses of the invention

Repair confirmation circuit for memory devices such as DRAM and SRM.

Description

Repair circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair circuit, and more particularly, to a repair circuit capable of electrically checking whether a defective cell of a memory device is repaired into a redundancy cell.

FIG. 1 is a conventional repair circuit diagram, in which 0V is applied to the power supply terminal 3 and 5V is applied to the write enable pad (/ WE PAD) 1, respectively. The poly fuse 2 connected between the enable pads 1 is not disconnected. At this time, the write enable pad 1 and a power supply terminal (3) between the NMOS transistors (N1 and N2) of about 3V by; the potential difference (5V-2V _TN threshold voltage (V _TN) of the transistor is about 1V Im) generated Therefore, a current of several tens of mA flows from the light enable pad 1 to the power supply terminal 3.

On the other hand, when the memory cell is defective, the poly fuse 2 connected between the NMOS transistor N1 and the write enable pad 1 is cut off. At this time, no current flows from the light enable pad 1 to the power supply terminal 3.

As described above, according to the related art, a repair or repair is not performed depending on whether a poly fuse is opened to repair a defective memory cell. However, there is a disadvantage in that it is difficult to check whether a repair is performed due to an open failure of the poly fuse.

Accordingly, an object of the present invention is to provide a repair circuit capable of eliminating the above-mentioned disadvantages by connecting a PMOS transistor having an output of a control circuit as an input between a write enable pad and a power supply terminal.

The repair circuit according to the present invention for achieving the above object is connected between the first and second NMOS transistors connected in series between a power supply terminal and a first node, the first node and the write enable pad and the output of the control circuit. It is characterized by consisting of a PMOS transistor whose signal is a gate input.

1 is a conventional repair circuit diagram.

2 is a repair circuit diagram according to the present invention.

Explanation of symbols for the main parts of the drawings

11: Light enable pad 12: Power terminal

13: poly fuse 14 and 15: first and second inverter

16: Control Circuit 17: Ground Terminal

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a repair circuit diagram according to the present invention, in which first and second NMOS transistors N1 and N2 are connected in series between a power supply terminal 12 and a first node K1, and the first node K1 and The PMOS transistor P1 for inputting the output of the control circuit 16 is connected between the write enable pads 11.

The control circuit 16 includes a poly fuse 13 connected between the power supply terminal 12 and the second node K2, and a first inverter connected between the second node K2 and the third node K3. 14, a third NMOS transistor N3 connected between the second node K2 and the ground terminal 17 and receiving the third node K3, the third node K3 and the control circuit. It consists of the 2nd inverter 15 connected between 4th node K4 which is the output of (16).

Referring to the operation of the repair circuit of the present invention configured as described above in detail as follows.

For example, when a voltage of about 4 V is applied to the power supply terminal 12 and a high voltage of about 8 V is applied to the write enable pad 11, when the memory cell is normal, the poly fuse 13 of the control circuit 16 is applied. ) Will not be blown. At this time, the second node K2 is in a high potential state of a constant voltage (about 4V), the third node K3 is in a low potential state by the first inverter 14, and the fourth node K4 is The second inverter 15 is brought back into a high potential state (about 4V). At this time, the third NMOS transistor N3 having the third node K3 as an input maintains a turn off state. Therefore, a voltage of 4V is applied to the input of the PMOS transistor P1, and a high voltage of about 8V is applied to the write enable pad 11, so that the voltage V _GS applied to the node K1 is applied at a voltage of 4V. do. Therefore, the first node K1 and the power supply terminal 12 become in phase so that no current flows and no repair is performed.

On the other hand, when the memory cell is a defective cell, the poly fuse 13 of the control circuit 16 is blown with a laser beam. At this time, the second node K2 is in a low potential state (0V), the third node K3 is in a high potential state by the first inverter 14, and the fourth node K4 is a second inverter ( 15), the low potential state (about 0V) is brought back. At this time, the third NMOS transistor N3 having the third node K3 as an input maintains a turn on state. Accordingly, a voltage having a low potential (0 V) is applied to the input of the PMOS transistor P1, and a high voltage of about 8 V is applied to the write enable pad 11 to apply the voltage V _GS applied to the first node K1. ) Takes a voltage of 8V. Therefore, a potential difference of 2V {8V-(2V _TN- 4V)} is generated between the first node K1 and the power supply terminal 12, and the power supply terminal 12 has several tens of kHz from the light enable pad 11. Current flows and repairs.

As described above, according to the present invention, a PMOS transistor for inputting the output of the control circuit is connected between the write enable pad and the power supply terminal to allow several tens of electric currents to flow from the write enable pad to the power supply terminal during repair. If the cell is defective, the PMOS transistor is blocked to control the flow of current, thereby having an excellent effect of electrically checking whether a repair is performed.

Claims (2)

First and second NMOS transistors connected in series between the power supply terminal and the first node; And a PMOS transistor connected between the first node and the write enable pad and having an output signal of a control circuit as a gate input. The control circuit of claim 1, wherein the control circuit comprises: a poly fuse connected between a power supply terminal and a second node; A first inverter connected between the second node and a third node; A third NMOS transistor connected between the second node and the ground terminal and receiving the third node as an input; And a second inverter connected between the third node and a fourth node which is an output of the control circuit.