KR100313938B1 - Circuit for Supplying Power of Eprom Cell - Google Patents

Abstract

The present invention provides a power supply voltage supply circuit for a pyromium cell that prevents a voltage drop from occurring when a supply current is supplied to the pyro cell due to leakage current in the power supply voltage supply circuit.

In order to achieve the above object, a power supply voltage supply circuit of an epitaxial cell includes a driving voltage VPP applying terminal for a data writing operation, a driving voltage VPP detecting unit formed between the driving voltage applying terminal and a ground terminal, and the driving unit. An inverter unit for delaying and inverting an output signal of the voltage detector, a first PMOS transistor for supplying a driving voltage to a memory cell when a high voltage is applied to the driving voltage applying terminal and performing a write operation, and the driving voltage When a high voltage is applied to the application terminal and the read operation is performed, a second PMOS transistor for supplying a power supply voltage (VCC) to the pyramid cell and a driving voltage when the high voltage is applied to the driving voltage application terminal are inputted. A third MOS transistor for preventing leakage current from being generated from the driving voltage applying terminal to the power supply voltage terminal, and applying the driving voltage A fourth PMOS transistor, a third PMOS transistor, and a node 1 for preventing a leakage current from being generated from a power supply voltage terminal to a driving voltage applying terminal when a low voltage is applied to the inverter; A fifth PMOS transistor formed between and operated by receiving a signal of the node 2, a sixth PMOS transistor formed between the fourth PMOS transistor and the node 2 and operated by receiving a signal of the node 1; A first NMOS transistor formed between the node 2 and the ground terminal to operate by receiving a write signal, an inverter for inverting and outputting the light signal, and formed between the node 1 and the ground terminal and the inverter signal; It characterized in that it is configured to include a second NMOS transistor to receive and operate.

Description

Circuit for Supplying Power of Eprom Cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a power supply voltage supply circuit for an epitaxial cell for supplying a power supply voltage to the pyro cell.

Referring to the accompanying drawings, a power supply voltage supply circuit of a conventional pyrom cell will be described below.

FIG. 1 is a circuit diagram showing a power supply voltage supply circuit of a conventional pyromium cell, and FIG. 2 is an operation timing diagram of a power supply voltage supply circuit of a conventional pyromium cell.

As shown in FIG. 1, the power supply voltage supply circuit of the conventional pyromium cell includes a VPP terminal 11 for applying a high voltage (12V or more) for data writing to the pyromium cell, and is formed between the VCC terminal and the VCON terminal. And a first PMOS transistor which operates by receiving a signal of the node 1 (N1). A second PMOS transistor PM2 is formed between the VPP terminal 11 and the VCON terminal and operates by receiving a signal of the node 2 N2.

The VPP terminal is a driving voltage applying terminal for data writing.

And a third PMOS transistor PM3 formed between the VCC terminal and the node 1 and operated by receiving a signal of the node 2, and a signal formed between the VPP terminal 11 and the node 2 and inputting the signal of the node 1. There is a fourth PMOS transistor PM4 that receives and operates.

Here, the signal of node 1 is input to the gate terminal of PM1, and the signal of node 2 is input to the gate terminal of PM2.

The first NMOS transistor NM1 is formed between the node 2 and the ground terminal VSS and operates by receiving a write signal Wt, and an inverter 12 that inverts the write signal Wt. And a second NMOS transistor NM2 formed between the node 1 and the ground terminal VSS and operated by receiving a signal from the inverter 12.

The first resistor R1 is present between the VPP terminal 11 and the drain terminal of the fourth PMOS transistor, and the second resistor R2 is present between the VCC terminal and the drain terminal of the third PMOS transistor. A third resistor R3 is formed between each of the drain terminals of the third PMOS transistor and the fourth PMOS transistor. At this time, R1 is 1kΩ, R2 is 2kΩ, and R3 has a value of 200Ω.

The first to fourth PMOS transistors PM1 to PM4 are high voltage PMOS transistors, and the first and second NMOS transistors NM1 and NM2 are high voltage NMOS transistors.

Referring to the operation of the power supply voltage supply circuit of the prior art pyrom cells configured as described above are as follows.

First, as shown in FIG. 2, a voltage of 12.75 V is applied to the VPP terminal 11. As a result, a high voltage is applied to the drain terminal of the fourth PMOS transistor PM4.

Subsequently, the write signal Wt is enabled to turn on the first NMOS transistor NM1 in order to perform a write operation for writing data to the epitaxial cell. Accordingly, a low voltage is applied to the node 2 (N2), PM2 is turned on, and the VPP voltage is applied to the epitaxial cell through the VCON terminal.

At this time, NM2 is turned off, PM3 is turned on, and node 1 (N1) has a high level. PM1 is thus turned off.

Next, when the write operation is stopped, the write signal Wt is disabled, the MN2 is turned on, and a low voltage is applied to the node 1 N1. Accordingly, PM1 is turned on, and the VCC voltage is applied to the epitaxial cell through the VCON terminal. At this time, PM4 is also turned on to apply a high voltage to node 2, and PM3 and PM2 are turned off.

As shown in FIG. 2, when the voltage of 12.75 V is applied to the VPP terminal 11, the VPP terminal 11 is provided through the first, second, and third resistors R1, R2, and R3. Leakage current (approximately 2.1 mA) can be generated at the VCC terminal. Also, when a low voltage (0 V) is applied to the VPP terminal, the VPP terminal is connected to the VCC terminal through the first, second and third resistors R1, R2 and R3. Leakage current (approximately 1.8 mA) occurs.

As the leakage current is generated as described above, when the write signal is enabled, the VPP voltage transferred to the pyrom cell through the VCON terminal is lowered from 12.75V to 12.44V due to the first resistor R1.

As described above, the power supply voltage supply circuit of the conventional pyrom cell has the following problems.

First, when a VPP voltage (12.75V) is applied to the VPP terminal, a leakage current is generated to the VCC through the first resistor, thereby lowering the voltage transferred to the pyrom cell through the VCON terminal.

Second, when a low level voltage is applied to the VPP terminal, a leakage current is generated from the VCC to the VPP terminal through the first resistor.

Third, the layout margin of the circuit is reduced due to the resistance formed in the power supply voltage supply circuit of the pyromium cell.

The present invention has been made to solve the above problems, and in particular, when supplying the power voltage to the pyrom cell, a leakage current is generated in the power voltage supply circuit to prevent a voltage drop to be supplied to the pyrom cell. It is an object of the present invention to provide a power supply voltage supply circuit of a pyrom cell.

1 is a circuit diagram showing a power supply voltage supply circuit of a conventional pyrom cell

2 is an operation timing diagram of a power supply voltage supply circuit of a conventional pyrom cell.

3 is a circuit diagram showing a power supply voltage supply circuit of the present invention pyrom cell

4 is an operation timing diagram of a power supply voltage supply circuit of the present invention pyrom cell.

Explanation of symbols for the main parts of the drawings

21: VPP terminal 22: VPP voltage detector

In order to achieve the above object, the power supply voltage supply circuit of the present invention pyrom cell includes a driving voltage (VPP) applying terminal for data writing operation, a driving voltage (VPP) detecting unit formed between the driving voltage applying terminal and a ground terminal; An inverter unit delaying and inverting an output signal of the driving voltage detection unit, a first PMOS transistor for supplying a driving voltage to a memory cell when a high voltage is applied to the driving voltage applying terminal and performing a write operation; When the high voltage is applied to the driving voltage applying terminal and the read operation is performed, a second PMOS transistor for supplying a power supply voltage (VCC) to the pyrom cell, and the driving voltage when a high voltage is applied to the driving voltage applying terminal. A third PMOS transistor for preventing leakage current from being generated from the driving voltage applying terminal to the power supply voltage terminal by receiving the A fourth PMOS transistor for preventing leakage current from being generated from the power supply voltage terminal to the driving voltage applying terminal when a low voltage is applied to the voltage applying terminal; A fifth PMOS transistor formed between node 1 and operated by receiving a signal of node 2, and a sixth PMOS transistor formed between the fourth PMOS transistor and node 2 and operated by receiving a signal of node 1; A first NMOS transistor formed between the node 2 and the ground terminal and operated by receiving a write signal, an inverter for inverting and outputting the write signal, and formed between the node 1 and the ground terminal, And a second NMOS transistor configured to receive and operate an inverter signal.

Referring to the accompanying drawings, a power supply voltage supply circuit of the present invention pyrom cell will be described.

3 is a circuit diagram showing a power supply voltage supply circuit of the present invention pyrom cell, and FIG. 4 is an operation timing diagram of the power supply voltage supply circuit of the present invention pyrom cell.

As shown in FIG. 3, the power supply voltage supply circuit of the present invention pyramid cell has a VPP terminal 21 for applying a high voltage (12V or more) during data write operation to the pyromium cell, and a VPP voltage is applied to the drain terminal. The VPP voltage detector 22 receives the VCC voltage at the gate terminal and outputs the VPP voltage.

In the above, the VPP terminal 21 is a driving voltage application terminal for data writing.

The VPP voltage detector 22 receives the power supply voltage VCC and receives the first NMOS transistor NM1 and the first PMOS transistor PM1 connected in series between the VPP terminal 21 and the ground terminal VSS. It is composed.

The first inverter 23 which receives the output signal of the VPP voltage detector 22 and inverts the second inverter 24 that inverts and outputs the output signal of the first inverter 23 and the second inverter. There is a third inverter 24 for inverting and outputting the output signal of (24).

There is a second PMOS transistor PM2 that receives the VCC voltage at the drain terminal, receives the signal of the node 1 N1 at the gate terminal, and outputs the VCC voltage to the epitaxial cell through the VCON terminal during the read operation.

There is a third PMOS transistor PM3 that applies a VCC voltage to a drain terminal, receives a VPP voltage at a gate terminal, and outputs a VCC voltage. In this case, PM3 serves to prevent leakage current from being generated from the VPP terminal 21 to the VCC terminal when a high voltage is applied to the VPP terminal.

There is a fourth PMOS transistor PM4 that applies a VPP voltage to the drain terminal and receives the output signal VPPEN of the third inverter 25 to supply the VPP voltage to the gate terminal. In this case, the PM4 receives the output signal of the third inverter 25 when the low voltage is applied to the VPP terminal, and prevents leakage current from being generated from the VCC terminal to the VPP terminal.

In this case, the third and fourth PMOS transistors PM3 and PM4 are floating.

A fifth PMOS transistor is applied to the drain terminal and the gate terminal receives the signal of the node 2 (N2) to output the VPP voltage to the EPROM cell through the VCON terminal during a write operation. (PM5).

And a sixth PMOS transistor PM6 formed between the source terminal of the third PMOS transistor PM3 and the node 1 N1 and operated by receiving a signal of the node 2 N2, and the fourth P The seventh PMOS transistor PM7 is formed between the source terminal of the MOS transistor PM4 and the node 2 and operates by receiving a signal of the node 1 N1. At this time, the drain terminals of PM6 and PM7 are connected to each other.

And a second NMOS transistor NM2 formed between the node 2 N2 and the ground terminal VSS and operating by receiving a light signal Wt, and a fourth inverter for inverting and outputting the light signal Wt. And a third NMOS transistor NM3 formed between the node 1 N1 and the ground terminal Vss and operated by receiving the inverted signal of the fourth inverter 26.

The first to seventh MOS transistors PM1 to PM7 are high voltage PMOS transistors, and the first to third NMOS transistors NM1 to NM3 are also high voltage NMOS transistors.

Referring to the operation of the power supply voltage supply circuit of the present invention pyrom cell having the above configuration is as follows.

First, a VPP voltage of 12.75 V is applied to the VPP terminal 21. Accordingly, the VPP voltage detector 22 changes the signal from the low level to the high level, and outputs the output signal VPPEN of the third inverter 25 through the first and second inverters 23 and 24. Is changed from a high level to a low level.

As a result, the fourth PMOS transistor PM4 is turned on and the VPP voltage (12.75 V) is applied to the drain terminals of the sixth and seventh PMOS transistors.

In the above state, when a write operation is performed to write data to the epitaxial cell, that is, when the write signal Wt is enabled, the second NMOS transistor NM2 is turned on. Accordingly, the second NMOS transistor NM2 is turned on. A low level signal is applied. In response to the low level signal of the node 2 N2, the fifth PMOS transistor PM5 is turned on and transmits a VPP voltage (12.75V) to the epitaxial cell through the VCON terminal.

At this time, the sixth PMOS transistor PM6 is turned on in response to the low level signal of the node 2 N2, the high level signal is applied to the node 1 N1, and the second PMOS transistor PM2 is turned off. As described above, since the second PMOS transistor PM2 is turned off, it is possible to prevent the VCC voltage from being supplied to the epitaxial cell.

Next, when the write operation is completed and the read operation execution command is input, the write signal Wt is disabled, and the third NMOS transistor NM3 is turned on to apply the low level signal to the node 1 N1. As a result, the second PMOS transistor PM2 is turned on to supply the VCC voltage (about 5-6V) to each epitaxial cell through the VCON terminal.

The seventh PMOS transistor PM7 is turned on in response to the low level signal of the node 1 N1, and the high level signal is applied to the node 2 N2 so that the sixth and fifth PMOS transistors PM6 and PM5 are turned off. do. As such, since the fifth PMOS transistor PM5 is turned off, it is possible to prevent the VPP voltage from being supplied to the epitaxial cell.

As shown in FIG. 4, when a high level (12.75V) VPP voltage is applied to the VPP terminal to write to the epitaxial cell, the third PMOS transistor PM3 is turned off and the VCC terminal of the VPP terminal is turned off. It is possible to prevent the leakage current from occurring at the terminal, and when the low level VPP voltage is applied to the VPP terminal when the chip is being tested or the read operation, the third inverter 25 is passed through the VPP voltage detector 22. Since the high level voltage is output to the output signal terminal VPPEN, the fourth PMOS transistor PM4 is turned off to prevent the leakage current from being generated from the VCC terminal to the VPP terminal 21.

The power supply voltage supply circuit of the present invention pyrom cell has the following effects.

First, it is possible to prevent unnecessary leakage current when the write operation for writing data to the epitaxial cell or to apply the low level signal to the VPP terminal, thereby eliminating the voltage drop applied to the epitaxial cell. The operating characteristics of the ROMCEL can be improved.

Second, the layout margin can be increased since there is no need to configure a resistor as compared with the conventional art.

Claims (7)

A driving voltage (VPP) applying terminal for data writing operation; A driving voltage (VPP) detecting unit formed between the driving voltage applying terminal and the ground terminal; An inverter unit for delaying and inverting an output signal of the driving voltage detection unit; A first PMOS transistor for supplying a driving voltage to a memory cell when a high voltage is applied to the driving voltage applying terminal and performing a write operation; A second PMOS transistor for supplying a power supply voltage (VCC) to an epitaxial cell when a high voltage is applied to the driving voltage applying terminal and performing a read operation; A third PMOS transistor for receiving a driving voltage when the high voltage is applied to the driving voltage applying terminal and preventing a leakage current from being generated from the driving voltage applying terminal to the power supply voltage VCC terminal; A fourth PMOS transistor for preventing leakage current from being generated from the power voltage terminal to the driving voltage applying terminal by receiving the output signal of the inverter unit when a low voltage is applied to the driving voltage applying terminal; A fifth PMOS transistor formed between the third PMOS transistor and node 1 and operated by receiving a signal of the node 2; A sixth PMOS transistor formed between the fourth PMOS transistor and node 2 and operated by receiving a signal of node 1; A first NMOS transistor formed between the node 2 and the ground terminal and operated by receiving a write signal; An inverter for inverting and outputting the write signal; And a second NMOS transistor formed between the node 1 and the ground terminal to operate by receiving the inverter signal. 2. The power supply voltage supply circuit of claim 1, wherein the third and fourth PMOS transistors are floated. 2. The power supply voltage of claim 1, wherein the driving voltage detector comprises an NMOS transistor and a PMOS transistor connected in series between the driving voltage applying terminal and the ground terminal and operated by receiving a VCC voltage. Circuit. The power supply voltage supply circuit of claim 1, wherein three inverters are connected in series. 2. The power supply voltage supply circuit of claim 1, wherein the signal of the node 1 is applied to an input terminal of the second PMOS transistor. 2. The power supply voltage supply circuit of claim 1, wherein the signal of the node 2 is applied to an input terminal of the first PMOS transistor. 2. The power supply voltage supply circuit of claim 1, wherein the drain terminals of the fifth PMOS transistor and the sixth PMOS transistor are connected to each other.