KR100336785B1 - Voltage supply control circuit - Google Patents

Abstract

The present invention relates to a voltage supply control circuit. In particular, an object of the present invention is to improve a low voltage operating characteristic by supplying a boosted voltage when a power supply voltage supplied to an EPROM cell falls below a specific voltage. According to the present invention, a voltage booster 220 for charging a voltage VCC and boosting it to a predetermined level, and a voltage level detector for enabling the voltage booster 220 when the voltage VCC becomes below a specific voltage. 210, a voltage level detector 230 for detecting a voltage VPP level, a voltage supply unit 290 for supplying a voltage VPP or a boosted voltage to the pyramid cell, and an inverter for inverting the write signal Wten. 270 and a voltage switching unit for controlling the voltage supply unit 290 to supply a voltage VPP or VCC to the gate of the pyramid cell by inputting the output signal of the inverter 270 and the write signal Wten. 280, a voltage supply unit 260 for outputting a voltage VCC or VPP to the voltage switching unit 280, an inverter 240 for inverting an output signal venb of the voltage level detection unit 230, and The output signal of the inverter 240 and the output signal venb of the voltage level detector 230 Power to constitute a voltage switching part 250 for controlling the voltage supply 260.

Description

Voltage supply control circuit {VOLTAGE SUPPLY CONTROL CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a voltage supply control circuit in EPROM.

1 is a circuit diagram of a conventional voltage supply, as shown therein, a voltage detector 110 for detecting a voltage VPP level supplied for writing a pyromium 150, and an operating voltage VCC or a boosted voltage. Supply a voltage supply unit 140 for supplying VPP to the pyramid cell 150, and supply an operating voltage VCC or a boosted voltage VPP to the pyramid cell 150 according to a write signal Wt. It is composed of a voltage switching unit 130 to control the voltage supply unit 140 to.

The voltage detector 110 is configured by applying a PMOS transistor HMP1 and an NMOS transistor HMN1 in series to apply an operating voltage VCC to a gate to divide the boosted voltage VPP.

The voltage supply unit 140 may supply a PMOS transistor HMP2 for supplying an operating voltage VCC to the epitaxial cell 150, and a PMOS transistor for supplying an operating voltage VCC to the voltage switching unit 130. (HMP3), PMOS transistor HMP5 for supplying boosted voltage VPP to said pyromium cell 9150 and PMOS transistor for supplying boosted voltage VPP to said voltage switching unit 130 ( HMP4).

The voltage switching unit 130 is connected to the drains of the PMOS transistors HMP3 and HMP4 having the source of the PMOS transistors HMP6 and HMP7 having their gates connected to the opposite drains, respectively, provided in the voltage supply unit 140. The drains of the PMOS transistors HMP6 and HMP7 are connected to gates of the PMOS transistors HMP2 and HMP5 provided in the voltage supply unit 140, respectively, and the NMOS transistors HMN3 and HMN2 having a source grounded. And a write signal Wt are connected to the gate of the NMOS transistor HMN2 and to the gate of the NMOS transistor HMN3 through an inverter 160.

In the drawing, reference numeral 120 denotes an inverter for inverting the detected voltage in the voltage detector 110 and providing the inverted voltage to the voltage supply unit 140.

Referring to the operation of the conventional circuit as follows.

First, a write operation for writing data to the pyramid cell 150 will be described.

When the boosted voltage VPP is supplied for the write operation of the pyramid cell 150, the voltage detector 110 divides the voltage through the PMOS transistor HMP1 and the NMOS transistor HMN1 to detect whether the voltage is sufficient for the light. The divided voltage is applied to the input terminal of the inverter 120.

At this time, when the boosted voltage VPP is at a predetermined level (for example, 12.5V), the inverter 120 applies a low level signal to the gate of the PMOS transistor HMP4 provided in the voltage supply unit 140.

Accordingly, the voltage supply unit 140 has the PMOS transistor HMP4 turned on to supply the boosted voltage VPP to the drain of the PMOS transistor HMP3 and the PMOS transistor HMP6 (HMP7). Supply to the source of.

In this case, since the write signal Wt is enabled at a high level, the voltage switching unit 130 turns on the NMOS transistor HMN2 by turning on the PMOS transistor HMP5 included in the voltage supply unit 140. The boosted voltage (VPP = VCON) is supplied to the pyrrole cell 150.

Accordingly, it is possible to write desired data in the pyromium 150.

In addition, a read operation for reading data stored in the pyramid cell 150 will be described below.

First, when the boosted voltage VPP is supplied, since the voltage detector 110 outputs a high signal and the inverter 120 outputs a low signal, the PMOS transistor HMP4 provided in the voltage supply unit 140 is turned on to thereby turn on the voltage. The boosted voltage VPP = VCON is supplied to the voltage switching unit 130.

At this time, since the write signal Wt is disabled at a low level, the output signal of the inverter 160 is at a high level to turn on the NMOS transistor HMN3.

Therefore, the voltage supply unit 140 may read the data stored in the pyromium 150 by supplying the operating voltage VCC to the pyromium cell 150 by turning on the PMOS transistor HMP2.

When the boosted voltage VPP is not supplied, the output signal of the voltage detector 110 is at a low level, so the inverter 120 outputs a high signal to the voltage supply 140 to turn off the PMOS transistor HMP4. Since the boosted voltage VPP is low, the PMOS transistor HMP3 is turned on.

At this time, since the voltage VCC is supplied to the power switching unit 130 by turning on the PMOS transistor HMP3 and the write signal Wt is in the low level state, the inverter 160 outputs a high signal so that the voltage switching unit ( The NMOS transistor HMN3 included in 130 is turned on.

Accordingly, since the PMOS transistor HMP2 is turned on to supply the operating voltage VCC = VCON to the pyramid cell 150, the voltage supply unit 140 may read data stored in the pyramid cell 150. .

However, in the conventional technology, when reading the data stored in the pyramid, as shown in the waveform diagram of FIG. 2, if the level of the operating voltage VCC drops, the voltage input to the gate of the pyromium cell is equally reduced. There is a problem that the low-voltage operating characteristics of the cell is degraded.

Accordingly, the present invention provides a voltage supply control circuit devised to improve low voltage operation characteristics by supplying a boosted voltage when a power supply voltage supplied to an EPROM cell falls below a specific voltage in order to improve a conventional problem. The purpose is to provide.

1 is a conventional voltage supply circuit diagram.

Figure 2 is a waveform diagram showing a simulation result in the prior art.

3 is a circuit diagram for an embodiment of the present invention.

4 is a circuit diagram of a voltage booster in FIG.

FIG. 5 is a circuit diagram of the voltage level detector 210 in FIG.

6 is a waveform diagram showing a simulation result in the embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

210,230: voltage level detection block 220: voltage booster

250,280: voltage switching unit 260,290: voltage supply unit

The present invention provides a voltage booster 220 for charging and boosting a voltage VCC to a predetermined level in order to achieve the above object, and pumping the voltage booster 220 when the voltage VCC becomes below a specific voltage. And a first voltage level detector 210 and a voltage switch 280 that determines whether to supply the VPP voltage or the VCC voltage to the gate of the pyromium cell by the write signal Wten.

Hereinafter, the present invention will be described in detail with reference to the drawings.

3 is a voltage supply control circuit diagram for an embodiment of the present invention, as shown therein, a voltage booster 220 for charging and boosting a voltage VCC to a predetermined level, and the voltage VCC being below a specific voltage. Supplying the voltage booster 220 to the voltage level detecting block 210, the voltage level detecting unit 230 detecting the voltage VPP level, and the voltage VPP or the boosted voltage to the pyramid cell. The voltage supply unit 290, the inverter 270 which inverts the write signal Wten, and the output voltage of the inverter 270 and the write signal Wten are inputted to the voltage VPP or VCC or 2VCC. A voltage switching unit 280 for controlling the voltage supply unit 290 to supply the gate of the cell, a voltage supply unit 260 for outputting a voltage VCC or VPP to the voltage switching unit 280, and the voltage level An inverter 240 for inverting the output signal venb of the detector 230 and the in An output signal (venb) of the output signal with the voltage level detector 230 of the emitter 240 and composed of the input voltage switching unit 250 for controlling the voltage supply 260.

As shown in the circuit diagram of FIG. 5, the voltage level detection block 210 includes a constant voltage unit 510 for outputting a constant voltage as an input of a voltage VCC and an output voltage of the constant voltage unit 510 as an input. The voltage VCC level is detected by comparing the voltage drop unit 520, which lowers the voltage VCC level by a specific voltage, with the reference voltage of the constant voltage unit 510, and the output voltage of the voltage drop unit 520. A differential amplifier 530, a control signal isp, and an output signal sout of the differential amplifier 530 to the NOR gate 540 that outputs the control signal Ivdout to the voltage booster 220. Configure.

As illustrated in the circuit diagram of FIG. 4, the voltage booster 220 includes a NAND gate 410 for NAND control signal rden (Ivdout), a control signal PROM, and an output signal of the NAND gate 410. The NOR gate 420 for nealing the NAND gate, the NAND gate 430 for NAND output signals of the control signal Ivdout, and the noah gate 420, the control signal isp and the noah gate 420 The voltage supply unit charges a voltage VCC by the output signal of the NAND gate 440 and the NOR gate 440 that noarizes the output signal, and outputs the voltage VCP by the output signal of the NAND gate 430. A voltage pumping unit 450 output to 290, an inverter 460 for inverting the output signal of the noah gate 440, an output signal of the inverter 460, and an output of the noah gate 440 A voltage switching unit 470 for supplying a voltage VCC to the voltage pumping unit 450 by a signal; And an inverter 480 for inverting the control signal PROM, and a voltage outputting the control signal pcon to the voltage supply unit 290 by the control signal PROM and the output signal of the inverter 480. The switching unit 490 is configured.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

First, a write operation for writing data to an EPROM is described as follows.

First, since the write signal Wten is at a high level, the NMOS transistor HN6 included in the voltage switching unit 280 is turned on so that the PMOS transistor HP7 is turned on and the PMOS transistor provided in the voltage supply unit 290. (HP9) is turned on.

In this case, since the control signal PROM is high, the voltage booster 220 may turn on the NMOS transistor HN45 included in the voltage switching unit 490 to output the control signal pcon at a low level. The PMOS transistor HP10 provided in the device is turned on.

Accordingly, the voltage supply unit 290 outputs the voltage VPP = VCON through the PMOS transistor HP9 and HP10 to write the desired data to the pyromium cell.

In addition, an operation for reading data stored in an EPROM will be described as follows.

First, when the voltage VCC through the PMOS transistor HP51 turned on by the low level control signal isp is input to the voltage level detection block 210, the MOS transistors HP52, HP53, HN51, and HN52 and a resistor are input. The constant voltage unit 510 including the R51 outputs a constant voltage through the input of the voltage VCC, and the voltage drop unit 520 turns on the NMOS transistor HN53 by the constant voltage, thereby forming a PMOS transistor HP54. The voltage VCC is dropped by a specific voltage through the NMOS transistor HN53 and output to the differential amplifier 530.

In this case, the differential amplifier 530 compares the output voltage of the voltage drop unit 520 with the output voltage of the constant voltage unit 510 as a reference value. In the normal operation, the output voltage of the voltage drop unit 520 is greater than the reference value. Since the NMOS transistor HN54 included in the differential amplifier 530 is turned on, the PMOS transistors HP55 and HP56 are turned on.

Therefore, since the output signal sout of the differential amplifier 530 is outputted high, the NOR gate 540 outputs the control signal Ivdout low.

At this time, the voltage booster 220 has the output signal of the NAND gates 410 and 430 high and the output signal of the NOR gate 410 becomes low due to the control signal Ivdout. The signal is output to the voltage pumping unit 450 and the voltage switching unit 470.

Accordingly, since the NMOS transistor HN42 included in the voltage switching unit 470 is turned on to turn on the PMOS transistor HP42 included in the voltage pumping unit 450, the NMOS transistor HN42 is turned on through the PMOS transistor HP42. The voltage VCC to be charged is charged in the capacitor C41.

In this case, when the voltage VPP is input, the voltage level detector 230 divides the voltage VPP through the PMOS transistor HP1 and the NMOS transistor HN1, and the divided signal ven is converted into PMOS. Inverted to a low level in the inverter consisting of a transistor (HP2) and the NMOS transistor (HN2) is output to the gate of the NMOS transistor (HN3) provided in the voltage switching unit 250 and the inverted signal at that time from the inverter 240 Inverted to the high level again and output to the gate of the NMOS transistor HN4 included in the voltage switching unit 250.

Accordingly, since the NMOS transistor HN4 is turned on and the PMOS transistor HP6 included in the voltage supply unit 260 is turned on, the voltage VPP is supplied to the voltage switching unit 280.

At this time, since the write signal Wten is low level and the output signal of the inverter 270 is high level, the NMOS transistor HN5 included in the voltage switching unit 280 is turned on to turn on the PMOS transistor HP8. In addition, the PMOS transistor HP11 provided in the voltage supply unit 290 is turned on.

Accordingly, by turning on the PMOS transistor HP8, the PMOS transistor HP9 included in the voltage supply unit 290 is turned off to cut off the supply of the voltage VPP to the EPROM. The voltage from the voltage booster 220 through the transistor HP11 (cpumpout = VCC) is supplied to the pyrom to read the stored data of the pyrom.

When the voltage VPP is not input, since the output signal venb of the voltage level detector 230 becomes high, the PMOS transistor HP5 provided in the voltage supply unit 260 is turned on to turn on the voltage switching unit 280. ) Is supplied with a voltage VCC.

Subsequent operations are performed in the same manner as above to read the stored data of the ipyrom.

On the other hand, when the voltage VCC falls below a specific voltage, the voltage level detector 210 outputs the voltage of the voltage dropper 520 to be lower than the reference voltage of the constant voltage unit 510, so that the differential amplifier 530 is a low signal. By outputting (sout), the NOR gate 540 outputs the control signal (Ivdout) to a high level.

In this case, in the voltage booster 220, the NAND gate 410 that receives the read signal rden and the control signal Ivdout of the high level outputs a low signal, and the control signal PROM and the NAND gate 410 of the low level. Noah gate 420 receives the low signal of the () to output a high signal.

Accordingly, since the output signal of the NAND gate 430 becomes low and the output signal of the NOR gate 440 that receives the high signal of the NOR gate 420 becomes low, the capacitor C51 provided in the voltage pumping unit 450. The charging potential of is pumped to '2VCC'.

Accordingly, the pumping voltage (cpumpout = 2VCC) of the voltage booster 220 is supplied to the pyramid through the PMOS transistor HP11 included in the voltage supply unit 290, so that the stored data of the pyromium can be read. .

The result of simulating this case is the same as the waveform diagram of FIG.

As described in detail above, when the operating voltage falls below a certain level in the read mode, the present invention has an effect of supplying a boosted voltage to the EPROM to improve the read operation characteristic of the pyromium cell.

In addition, since the present invention directly generates the boost voltage from the circuit embedded in the pyrom, there is no need to add a separate boost circuit, so that the chip design can be easily performed.

Claims (4)

A voltage booster for charging the voltage VCC and outputting the voltage VCC or 2VCC during a read operation, and first voltage level detection means for enabling a boost operation of the voltage booster when the voltage VCC becomes below a specific voltage. First voltage supply means for selecting the voltage VPP during the write operation, selecting the voltage VCC or the boosted voltage 2VCC during the read operation, and supplying the selected voltage to the pyro cell, and the write signal Wten as an input. First voltage switching means for controlling the first voltage supply means, second voltage level detection means for detecting the voltage VPP level, and second voltage for outputting a voltage VCC or VPP to the first voltage switching means. And a second voltage switching means for controlling the second voltage supply means by inputting the supply means and an output signal (venb) of the second voltage level detection means. The voltage reducing device of claim 1, wherein the first voltage level detecting unit comprises: a constant voltage unit for outputting a constant voltage through the input of the voltage VCC; and a voltage drop for dropping the voltage VCC level by a specific voltage through the output voltage of the constant voltage unit. A differential amplifier for detecting a voltage (VCC) level by comparing a lower portion, a reference voltage in the constant voltage section and an output voltage of the voltage drop section, and a control signal (istp) and an output signal (sout) of the differential amplifier. And a Noah gate for outputting a control signal Ivdout to the voltage booster. The voltage booster of claim 1, wherein the voltage booster is configured to output a boost voltage for supplying to the first voltage supply means when the voltage VCC is lower than or equal to a specific voltage during a read operation. And a logic gate section for controlling a boost operation of the voltage pumping section in an output mode as an input, and a first voltage switching section for supplying a voltage VCC to the voltage pumping section under control of the logic gate section. Voltage supply control circuit, characterized in that. 4. The logic gate of claim 3, wherein the logic gate unit comprises: a first NAND gate for outputting a control signal rden (Ivdout); a first NOR gate for nulling a control signal PROM and an output signal of the first NAND gate; A second NAND gate for controlling the voltage boosting operation of the voltage pumping unit by reading the control signal Ivdout and the output signal of the first NOR gate, and a control signal isp and the output signal of the first NOR gate And a second NOR gate configured to ring to control the charging operation of the voltage pumping unit.