KR19990004564A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19990004564A KR19990004564A KR1019970028691A KR19970028691A KR19990004564A KR 19990004564 A KR19990004564 A KR 19990004564A KR 1019970028691 A KR1019970028691 A KR 1019970028691A KR 19970028691 A KR19970028691 A KR 19970028691A KR 19990004564 A KR19990004564 A KR 19990004564A
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- oxide film
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- epitaxy layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02642—Mask materials other than SiO2 or SiN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 반도체 기판상에 산화막을 증착하고 건식식각으로 필드영역에 해당하는 산화막만 남긴 상태에서 급속열처리공정(rapid thermal processing, RTP) 공정으로 암모니아 분위기에서 단시간내에 급속질화공정(rapid thermal nitridation, RTN)을 실시하여 실리콘 에피택시층과 만나는 상기 산화막 측벽을 질화산화막으로 바꿔줌에 의해 에피택시층의 측벽에 작용하는 응력을 감소시켜 줌으로써 누설전류를 감소시켜 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, wherein an oxide film is deposited on a semiconductor substrate and a rapid thermal processing (RTP) process is performed in a short time in an ammonia atmosphere in a state where only an oxide film corresponding to a field region is left by dry etching. The semiconductor device is reduced by reducing the stress applied to the sidewalls of the epitaxy layer by changing the oxide sidewalls to meet the silicon epitaxy layer by performing rapid thermal nitridation (RTN). The present invention relates to a method for manufacturing a semiconductor device capable of improving the production yield and reliability.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자 제조공정 중 선택적 실리콘 에피택시(selective silicon epitaxy) 방법에 의한 반도체 소자의 소자분리 공정시, 선택적 에피택시에 의해 성장한 액티브 영역의 측벽에 가해지는 응력을 최소화하여 반도체 소자의 제조수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a sidewall of an active region grown by selective epitaxy during a device isolation process of a semiconductor device by a selective silicon epitaxy method during a semiconductor device manufacturing process. The present invention relates to a method for manufacturing a semiconductor device capable of minimizing stress to improve manufacturing yield and reliability of the semiconductor device.
선택적 에피택시 방법에 의한 종래의 소자 분리 기술에 대해 첨부도면을 참조하면 살펴보면 다음과 같다.Referring to the accompanying drawings, a conventional device isolation technique using a selective epitaxy method is as follows.
도 1a 내지 도 1c 는 종래 기술에 따른 소자분리 공정단계를 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a device isolation process step according to the prior art.
먼저, 반도체 기판(11) 상부에 산화막(12)을 형성한다.(도 1a)First, an oxide film 12 is formed over the semiconductor substrate 11 (FIG. 1A).
다음 포토/식각 공정으로 통해 상기 산화막(12)을 식각하여 필드 영역에만 상기 산화막(22)이 남도록 한다. 이때, 식각은 건식식각으로 한다.(도 1b)Next, the oxide film 12 is etched through the photo / etch process so that the oxide film 22 remains only in the field region. At this time, the etching is a dry etching (Fig. 1b).
다음 상기 반도체 기판(11)의 노출된 부위에 선택적 실리콘 에피택시층(13)을 형성한다.(도 1c)Next, the selective silicon epitaxy layer 13 is formed on the exposed portion of the semiconductor substrate 11 (FIG. 1C).
상기와 같은 공정으로 이뤄지는 종래의 소자분리 기술에 있어서, 선택적 실리콘 에피택시 공정이 고온 예컨데, 약 850℃ 에서 이루어지므로 선택적 실리콘 에피택시층(13)이 형성된 후, 냉각시 실리콘과 산화막(12)의 열팽창 계수 차이에 의해 에피택시층(13)의 측벽에 응력이 집중되어 결축 에피택시층 측벽에 전위(dislocation) 및 결함이 형성되어 누설전류 증가의 원인이 되므로 결국 반도체 소자의 전기적 특성을 열화시키게 되는 문제점이 있다.In the conventional device isolation technology made of the above-described process, the selective silicon epitaxy process is performed at a high temperature, for example, at about 850 ° C., so that after the selective silicon epitaxy layer 13 is formed, the silicon and the oxide film 12 are cooled. The stress is concentrated on the sidewall of the epitaxy layer 13 due to the difference in coefficient of thermal expansion, so that dislocations and defects are formed on the sidewall of the epitaxy layer, which causes an increase in leakage current, thereby deteriorating the electrical characteristics of the semiconductor device. There is a problem.
따라서 본 발명은 상기의 문제점을 해결하기 위하여 산화막 형성과 건식식각 후에 급속질화공정을 실시함에 의해 에피택시층이 산화막과 접촉하였을 경우 열팽창계수의 차이를 줄여 결함발생을 최소화시켜 반도체 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above problems, the present invention provides a rapid nitriding process after oxide film formation and dry etching to minimize the occurrence of defects by minimizing defects when the epitaxy layer is in contact with the oxide film, thereby minimizing the electrical characteristics of the semiconductor device. Its purpose is to provide a method for manufacturing a semiconductor device that can be improved.
도 1a 내지 도 1c 는 종래 기술에 따른 소자분리 공정단계를 도시한 단면도1A to 1C are cross-sectional views illustrating a device isolation process step according to the prior art.
도 2a 내지 도 2d 는 본 발명의 기술에 따른 소자분리 공정단계를 도시한 단면도2A through 2D are cross-sectional views illustrating device isolation process steps in accordance with the techniques of the present invention.
도면의 주요 부분에 대한 설명Description of the main parts of the drawing
11,21 : 반도체 기판 12,22 : 산화막11,21 semiconductor substrate 12,22 oxide film
13,23 : 선택적 실리콘 에피택시층13,23: Selective Silicon Epitaxy Layer
14,24 : 질화 산화막14,24: nitrided oxide film
상기 목적을 달성하기 위한 본 발명의 방법은, 반도체 기판상에 산화막을 소정두께로 형성하는 단계와, 포토/식각 공정으로 상기 산화막을 식각하여 필드 영역에만 상기 산화막이 남도록 하는 단계와, 암모니아 분위기에서 급속열처리공정을 실시하여 상기 산화막을 질화산화막로 바꾸는 단계와, 반도체 기판의 노출된 부위에 선택적 실리콘 에피택시층을 형성하는 단계를 포함하는 것을 특징으로 한다.The method of the present invention for achieving the above object comprises the steps of forming an oxide film on a semiconductor substrate to a predetermined thickness, etching the oxide film by a photo / etching process so that the oxide film remains only in the field region, and in an ammonia atmosphere. And converting the oxide film into a nitride oxide film by performing a rapid heat treatment process, and forming a selective silicon epitaxy layer on the exposed portion of the semiconductor substrate.
이하 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명의 기술에 따른 소자분리 공정단계를 도시한 단면도이다.2A through 2D are cross-sectional views illustrating device isolation process steps in accordance with the techniques of the present invention.
먼저, 반도체 기판(21) 상부에 산화막(22)을 소정두께로 형성한다. 이때 상기 산화막(22)의 두께는 3000-10,000Å 로 하고, 열적인 방법 또는 화학기상증착법(CVD 법)에 의해 형성한다.(도 2a)First, an oxide film 22 is formed on the semiconductor substrate 21 to have a predetermined thickness. At this time, the thickness of the oxide film 22 is set to 3000-10,000 kPa, and is formed by a thermal method or a chemical vapor deposition method (CVD method) (FIG. 2A).
다음 포토/식각 공정으로 상기 산화막(22)을 식각하여 필드 영역에만 상기 산화막(22)이 남도록 한다. 이때, 식각은 건식식각으로 한다.(도 2b)Next, the oxide film 22 is etched by the photo / etch process so that the oxide film 22 remains only in the field region. At this time, the etching is a dry etching (Fig. 2b).
다음 암모니아 분위기에서 급속 열처리 공정으로 상기 산화막(22)을 질화산화막(24)로 바꾸어 준다.Next, the oxide film 22 is replaced with the nitride oxide film 24 by a rapid heat treatment process in an ammonia atmosphere.
이때 상기 사용되는 암모니아의 양은 1-5 slpm 으로 하고, 열처리시 온도는 800-1100℃ 로 하며, 열처리 시간은 10-120 초로, 목표로 하는 온도까지의 승온 속도는 10-150℃/sec 로 한다.(도 2c)At this time, the amount of ammonia used is 1-5 slpm, the temperature during heat treatment is 800-1100 ℃, the heat treatment time is 10-120 seconds, the temperature increase rate to the target temperature is 10-150 ℃ / sec. (FIG. 2C)
반도체 기판(21)의 노출된 부위에 선택적 실리콘 에피택시층(23)을 형성한다.An optional silicon epitaxy layer 23 is formed on the exposed portion of the semiconductor substrate 21.
상기 선택적 실리콘 에피택시층(23)은 UHV-CVD(Ultra High Vacuum - CVD) 또는 LP-CVD(Low Pressure - CVD) 법에 의해 형성하며, 또한 에피택시층(23)의 높이는 3,000-12,000Å 로 한다.(도 2d)The selective silicon epitaxy layer 23 is formed by UHV-CVD (Ultra High Vacuum-CVD) or LP-CVD (Low Pressure-CVD), and the height of the epitaxy layer 23 is 3,000-12,000 kPa. (FIG. 2D)
한편, 일반적으로 열팽창 계수의 크기는 SiO2가 5 × 10-7/ ℃ 로서, Si (5.8 × 10-7/ ℃)보다 작지만 Si3N4는 Si 보다 다소 큰 값을 가진다.On the other hand, in general, the thermal expansion coefficient of SiO 2 is 5 × 10 −7 / ° C., which is smaller than Si (5.8 × 10 −7 / ° C.), but Si 3 N 4 has a somewhat larger value than Si.
그러므로 Si3N4가 실리콘보다 더 큰 열팽창계수를 갖고 있기 때문에 열산화막을 질화산화막으로 만들어 주면 열산화막이 직접 실리콘을 만났을 때보다 더욱 실리콘의 열팽창계수와 근사된 값을 갖는 막을 형성하게 된다. 이때 만약, 열처리를 노(furnace)에서 실시하게 되면 고온 예컨데, 1000℃ 이상의 고온에서 실시해야 하므로 건식식각에 의해 예리하게 형성된 식각 형상이 완만한 모양으로 변형되는 단점이 있으므로 이를 방지하기 위하여 급속열처리공정을 사용한다.Therefore, since Si 3 N 4 has a larger coefficient of thermal expansion than silicon, when the thermal oxide film is a nitride oxide film, the thermal oxide film has a value closer to that of silicon than when the thermal oxide film directly meets silicon. At this time, if the heat treatment is carried out in a furnace (furnace) high temperature, for example, it must be carried out at a high temperature of 1000 ℃ or more, the etching shape formed by the dry etching is a disadvantage that is deformed into a gentle shape, so to prevent this rapid heat treatment process Use
즉 상기 급속열처리공정은 암모니아 분위기에서 단시간 예컨데, 2분 미만의 시간동안 급속 열처리하는 공정으로서, 상기 급속열처리공정을 진행하게 되면, 건식식각에 의해 형성된 식각 형상을 그대로 유지하면서 측벽의 표면부위만을 질소가 침투하여 질화산화막으로 만들어 주게 되며, 상기와 같이 형성된 질화산화막은 선택적 실리콘 에피택시층(23)과 비슷한 열팽창계수를 가지므로 냉각시 측벽의 응력을 감소시켜 결함이 형성되는 것을 억제시키고 누설전류를 감소시킬 수 있게 된다.That is, the rapid heat treatment process is a rapid heat treatment for a short time, for example, less than 2 minutes in an ammonia atmosphere. When the rapid heat treatment process is performed, only the surface portion of the sidewall is kept in nitrogen while maintaining the etching shape formed by dry etching. Is penetrated into the nitride oxide film, and the nitride oxide film formed as described above has a coefficient of thermal expansion similar to that of the selective silicon epitaxy layer 23, thereby reducing the stress on the sidewalls during cooling to suppress the formation of defects and reducing leakage current. Can be reduced.
이상 상술한 바와같이, 반도체 기판상에 산화막을 증착하고 건식식각으로 필드영역에 해당하는 산화막만 남긴 상태에서 급속열처리공정으로 암모니아 분위기에서 단시간내에 급속질화공정을 실시하여 선택적 실리콘 에피택시층과 만나는 산화막 측벽을 질화산화막으로 바꿔 에피택시층의 측벽에 작용하는 응력을 감소시켜 줌으로써 누설전류를 감소시킬 수 있다.As described above, an oxide film is formed on a semiconductor substrate and is subjected to a rapid nitriding process in a short time in an ammonia atmosphere with a rapid thermal treatment in a state where only the oxide film corresponding to the field region is left by dry etching to meet the selective silicon epitaxy layer. The leakage current can be reduced by changing the sidewalls to the nitride oxide film to reduce the stress applied to the sidewalls of the epitaxy layer.
Claims (9)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030059482A (en) * | 2001-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | Method of forming isolating layer for semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4758531A (en) * | 1987-10-23 | 1988-07-19 | International Business Machines Corporation | Method of making defect free silicon islands using SEG |
| JP2679111B2 (en) * | 1988-05-31 | 1997-11-19 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JPH02181969A (en) * | 1989-01-06 | 1990-07-16 | Nec Corp | Construction of element isolating region and manufacture thereof |
| US5073516A (en) * | 1991-02-28 | 1991-12-17 | Texas Instruments Incorporated | Selective epitaxial growth process flow for semiconductor technologies |
| JPH06120332A (en) * | 1992-10-01 | 1994-04-28 | Nec Corp | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030059482A (en) * | 2001-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | Method of forming isolating layer for semiconductor device |
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