KR19990004565A - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a silicon epitaxial layer is formed in an active region by depositing an oxide layer on a semiconductor substrate and forming a polysilicon spacer layer around the oxide layer while leaving only the oxide layer corresponding to the field region by dry etching. It is a method that improves the yield and reliability of semiconductor devices by reducing the leakage current generated in the silicon epitaxy layer by allowing the taxi layer to meet polysilicon without being directly exposed to the oxide film, thereby causing the polysilicon to act as a stress buffer. .

Description

Manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a sidewall of an active region grown by selective epitaxy during a device isolation process of a semiconductor device by a selective silicon epitaxy method during a semiconductor device manufacturing process. The present invention relates to a method for manufacturing a semiconductor device capable of improving the production yield and reliability of a semiconductor device by reducing the leakage current generated in the silicon epitaxy layer by causing the polysilicon spacer to buffer the losing stress.

Referring to the accompanying drawings, a conventional device isolation technique using a selective epitaxy method is as follows.

1A to 1C are cross-sectional views illustrating a device isolation process step according to the prior art.

First, an oxide film 12 is formed over the semiconductor substrate 11 (FIG. 1A).

Next, the oxide film 12 is etched through the photo / etch process so that the oxide film 12 remains only in the field region. At this time, the etching is a dry etching (Fig. 1b).

Next, the selective silicon epitaxy layer 13 is formed on the exposed portion of the semiconductor substrate 11 (FIG. 1C).

The upper surface is planarized by CMP (Chemical Mechanical Polishing). (FIG. 1D)

In the conventional device isolation technology made of the above-described process, the selective silicon epitaxy process is performed at a high temperature, for example, at about 850 ° C., so that after the selective silicon epitaxy layer 13 is formed, the silicon and the oxide film 12 are cooled. The stress is concentrated on the sidewall of the epitaxy layer 13 due to the difference in coefficient of thermal expansion, so that dislocations and defects are formed on the sidewall of the epitaxy layer, which causes an increase in leakage current, thereby deteriorating the electrical characteristics of the semiconductor device. There is a problem.

Accordingly, in order to solve the above problems, the present invention forms a polysilicon layer after oxide film formation and dry etching, and dry-etches it again to form a polysilicon spacer, so that the thermal expansion coefficient of the single crystal silicon epitaxial layer and the oxide film are directly met. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of improving the electrical characteristics, manufacturing process yield, and reliability of the semiconductor device by minimizing defects by minimizing defects.

1A to 1D are cross-sectional views illustrating a device isolation process step according to the prior art.

2A through 2F are cross-sectional views illustrating device isolation process steps in accordance with the present invention

3A and 3B are cross-sectional views for explaining the principle of the stress relaxation of the polysilicon spacer film according to the technique of the present invention

Description of the main parts of the drawing

11,21 semiconductor substrate 12,22 oxide film

13,23: selective silicon epitaxy layer 24: polysilicon film

25 polysilicon spacer 26 single crystal in polysilicon

27: grain boundary

The method of the present invention for achieving the above object,

Forming an oxide film to a predetermined thickness on the semiconductor substrate acid;

Etching the oxide film by a photo / etch process so that the oxide film remains only in a field region;

Forming a polysilicon layer having a predetermined thickness on the entire structure;

Etching the polysilicon layer to form polysilicon spacers on both sidewalls of the etched oxide layer;

Forming a selective silicon epitaxy layer on the exposed portion of the semiconductor substrate,

And planarizing the top surface.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2F are cross-sectional views illustrating device isolation process steps according to the technology of the present invention.

First, an oxide film 22 is formed on the semiconductor substrate 21 to have a predetermined thickness. At this time, the thickness of the oxide film 22 is set to 3000-10,000 kPa, and is formed by a thermal method or a chemical vapor deposition method (CVD method) (FIG. 2A).

Next, the oxide film 22 is etched by the photo / etch process so that the oxide film 22 remains only in the field region. At this time, the etching is a dry etching. (FIG. 2B)

Next, polysilicon is deposited on the entire structure by low pressure CVD (LPCVD) or PECVD to form a polysilicon layer 24 having a thickness of 50-500 Å. (FIG. 2C)

Next, the polysilicon 24 is dry-etched to form polysilicon spacers 25 on both sidewalls of the etched oxide film 22 (FIG. 2D).

An optional silicon epitaxy layer 23 is formed on the exposed portion of the semiconductor substrate 21.

The selective silicon epitaxy layer 23 is formed by UHV-CVD (Ultra High Vacuum-CVD) or LP-CVD, and the height of the epitaxy layer 23 is set to 3,000-12,000 kPa (FIG. 2E).

The top surface is planarized by the CMP process (Fig. 2f).

3A and 3B are cross-sectional views for explaining the principle of the stress relief of the polysilicon spacer film according to the technique of the present invention.

3A shows an epitaxial layer 24 which is a silicon single crystal. When the layer meets the oxide film 22 directly, atoms in the single crystal have the same directionality, so the difference in thermal expansion coefficient between silicon and the oxide film is 100 upon cooling. It is transferred to the% single crystal silicon epitaxy layer 23 to generate a large stress. However, as shown in FIG. 3B, since the polysilicon spacer film 25 is an aggregate composed of a number of single crystals 26 which are disorderly oriented with each other at the boundary of the grain boundary 27, the polysilicon spacer film 25 is formed of an oxide film ( 22) and the single crystal silicon epitaxy layer 23, the small single crystals 26 having different directionality to offset the difference in the large coefficient of thermal expansion generated during cooling to compensate for the three-dimensional generated stress to buffer Done. As a result, the stress transmitted to the silicon epitaxy layer 23 is minimized to reduce the leakage current.

As described above, in the method of the present invention, a silicon epitaxial layer is formed on an active region by depositing an oxide film on a semiconductor substrate and forming a polysilicon spacer film around the oxide film while leaving only the oxide film corresponding to the field region by dry etching. By allowing the taxi layer to meet the polysilicon without being directly exposed to the oxide film, thereby making the polysilicon act as a stress buffer, the leakage current generated in the silicon epitaxy layer can be reduced to improve the manufacturing yield and reliability of the semiconductor device.

Claims (7)

Forming an oxide film to a predetermined thickness on a semiconductor substrate, etching the oxide film by a photo / etch process so that the oxide film remains only in a field region, and forming a polysilicon layer having a predetermined thickness on the entire structure; And etching the polysilicon layer to form polysilicon spacers on both sidewalls of the etched oxide film, forming a selective silicon epitaxy layer on exposed portions of the semiconductor substrate, and planarizing the top surface. Method for manufacturing a semiconductor device, characterized in that consisting of. The method of claim 1, wherein the oxide film is formed by a thermal method or a CVD method. The method of manufacturing a semiconductor device according to claim 1, wherein the oxide film has a thickness of 3,000-10,000 kPa. The method of claim 1, wherein the polysilicon is deposited by LPCVD or PECVD. The method of manufacturing a semiconductor device according to claim 1, wherein the polysilicon layer has a thickness of 50-500 GPa. The method of claim 1, wherein the selective silicon epitaxy layer is formed by UHV-CVD or LP-CVD. The method of manufacturing a semiconductor device according to claim 1, wherein the height of said selective silicon epitaxy layer is 3,000-12,000 kPa.