KR0172043B1 - Method of fabricating a semiconductor device - Google Patents
Method of fabricating a semiconductor device Download PDFInfo
- Publication number
- KR0172043B1 KR0172043B1 KR1019950046304A KR19950046304A KR0172043B1 KR 0172043 B1 KR0172043 B1 KR 0172043B1 KR 1019950046304 A KR1019950046304 A KR 1019950046304A KR 19950046304 A KR19950046304 A KR 19950046304A KR 0172043 B1 KR0172043 B1 KR 0172043B1
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- KR
- South Korea
- Prior art keywords
- oxide film
- semiconductor device
- polysilicon layer
- manufacturing
- forming
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 229910008484 TiSi Inorganic materials 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000004151 rapid thermal annealing Methods 0.000 claims description 5
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 125000000896 monocarboxylic acid group Chemical group 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 게이트 전극이 형성된 액티브 영역 영역상에 선택적으로 에피택셜-실리콘(Epitaxial Silicon)을 증착시킨 후, TiSi2층을 형성하므로서 소오스 및 드레인 저항 감소, 접합 영역에서의 누설 전류 감소 및 콘택 저항을 감소시킬 수 있는 반도체 소자 제조 방법이 개시된다.The present invention selectively deposits epitaxial silicon on the active region where the gate electrode is formed, and then forms a TiSi 2 layer to reduce source and drain resistance, reduce leakage current in the junction region, and contact resistance. Disclosed is a method of manufacturing a semiconductor device that can be reduced.
Description
제1a 내지 1d도는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 : 게이트 산화막 4 : 제1차 폴리 실리콘층3: gate oxide film 4: primary polysilicon layer
5 : 게이트 전극 6: 제2차 폴리 실리콘층5: gate electrode 6: secondary polysilicon layer
7 : 에피택셜 실리콘층 8 : 산화막7: epitaxial silicon layer 8: oxide film
9 : Ti막 10 : TiSi2층9: Ti film 10: TiSi 2 layer
11 : 소오스 및 드레인 영역11: source and drain regions
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 액티브 영역에 선택적으로 에피택셜-실리콘층을 형성하도록 한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an epitaxial-silicon layer is selectively formed in an active region.
일반적으로 반도체 소자의 액티브 영역에 증착되는 실리사이드층의 형성 공정은 여러 가지 방법이 있으나 소자의 고집적화 및 소형화 추세에 따라 저항 및 누설 전류를 감소시킬 수 있는 반도체 소자가 요구된다. 그러나, 종래의 액티브 영역상에 실리사이드층으로 형성되는 TiSi2막은 소오스 및 드레인간의 저항 및 누설 전류를 최소한으로 감소시킬 수 없는 단점이 있다.In general, there are various methods of forming the silicide layer deposited on the active region of the semiconductor device, but a semiconductor device capable of reducing resistance and leakage current is required according to the trend toward higher integration and miniaturization of the device. However, a TiSi 2 film formed of a silicide layer on a conventional active region has a disadvantage in that resistance and leakage current between a source and a drain cannot be reduced to a minimum.
따라서, 본 발명은 게이트 전극이 형성된 액티브 영역상에 선택적으로 에피택셜-실리콘(Epitaxial Silicon)층을 형성할 수 있도록 한 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for fabricating a semiconductor device capable of selectively forming an epitaxial silicon layer on an active region in which a gate electrode is formed.
상기한 목적을 달성하기 위한 본 발명은 필드 산화막이 형성된 실리콘 기판상의 액티브 영역에 게이트 산화막 및 제1차 폴리 실리콘층이 적층된 게이트 전극을 형성하는 단계와, 상기 게이트 전극이 형성된 액티브 영역에 에피택셜-실리콘층이 선택적으로 형성된 후, 상기 전체 구조 상부에 제2차 폴리 실리콘층을 형성하는 단계와, 상기 제2차 폴리 실리콘층이 선택적으로 식각된 후, 산화막이 증착되는 단계와, 상기 소오스 및 드레인 영역을 형성하고, 상기 전체 소자를 열 공정을 실시하는 단계와, 상기 산화막이 식각 공정에 의해 식각되어 제거된 후, Ti막을 형성하는 단계와, 상기 전체 소자를 RTA(Rapid Thermal Anneal)공정으로 TiSi2층을 형성하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate electrode in which a gate oxide film and a first polysilicon layer are stacked in an active region on a silicon substrate on which a field oxide film is formed, and epitaxially in an active region on which the gate electrode is formed. Forming a secondary polysilicon layer over the entire structure after the silicon layer is selectively formed, depositing an oxide film after the secondary polysilicon layer is selectively etched, the source and Forming a drain region, performing a thermal process on the entire device, forming a Ti film after the oxide film is etched and removed by an etching process, and forming the Ti film, and subjecting the entire device to a rapid thermal annealing (RTA) process. Forming a TiSi 2 layer is characterized by.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a 내지 1d도는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
제1a도와 관련하여, 필드 산화막(2)이 형성된 실리콘 기판(1)상의 액티브 영역에 게이트 산화막(3) 및 제1차 폴리 실리콘층(4)이 적층된 게이트 전극(5)이 형성된다. 상기 게이트 전극(5)이 형성된 액티브 영역(12)에 에피택셜-실리콘층(7)이 선택적으로 형성된다. 상기 전체 구조 상부에 LP(Low Pressure)CVD공정으로 온도 620℃에서 SiH4가스를 사용하여 제2차 폴리 실리콘층(6)이 형성된다.Regarding FIG. 1A, a gate electrode 5 in which the gate oxide film 3 and the primary polysilicon layer 4 are stacked is formed in an active region on the silicon substrate 1 on which the field oxide film 2 is formed. An epitaxial-silicon layer 7 is selectively formed in the active region 12 in which the gate electrode 5 is formed. The secondary polysilicon layer 6 is formed on the entire structure by using SiH 4 gas at a temperature of 620 ° C. by a low pressure (CVD) process.
제1b도와 관련하여, 상기 제2차 폴리 실리콘층(6)이 HNO3:CH3COOH:HF=10With respect to FIG. 1B, the secondary polysilicon layer 6 is formed by HNO 3 : CH 3 COOH: HF = 10
:10:1의 비율로 배합된 용액으로 습식 식각 공정에 의해 선택적으로 식각된다. 상기 전체 구조 상부에 산화막(8)이 200Å의 두께로 증착되고, 불순물 주입에 의한 소오스 및 드레인 영역(11)이 형성된다. 상기 전체 소자에 900℃의 온도에서 질소 분위기하에 약 10분간 열 공정이 실시된다.The solution formulated in a ratio of 10: 1 is selectively etched by a wet etching process. An oxide film 8 is deposited to a thickness of 200 mW on the entire structure, and source and drain regions 11 are formed by impurity implantation. The entire device is subjected to a thermal process for about 10 minutes under a nitrogen atmosphere at a temperature of 900 ° C.
제1c도와 관련하여, 상기 산화막(8)이 식각 공정에 의해 식각되어 제거된 후, 전체 구조 상부에 Ti막(9)이 500Å의 두께로 형성된다.In connection with FIG. 1C, after the oxide film 8 is etched and removed by an etching process, a Ti film 9 is formed on the entire structure to a thickness of 500 kPa.
제1d도와 관련하여, 상기 전체 소자가 RTA(Rapid thermal Anneal) 공정으로 600∼650℃ 온도에서, N2분위기하에 20초간 실시되어 TiSi2층(10)이 형성되고, 상기 미 반응된 Ti막(9)은 제거된다.In relation to FIG. 1D, the entire device is subjected to a rapid thermal annealing (RTA) process at a temperature of 600 to 650 ° C. for 20 seconds under an N 2 atmosphere to form a TiSi 2 layer 10 to form the unreacted Ti film ( 9) is removed.
상술한 바와 같이 본 발명에 의하면 게이트 전극이 형성된 액티브 영역상에 선택적으로 에피택셜-실리콘(Epitaxial Silicon)을 증착시킨 후, TiSi2층을 형성하므로서 소오스 및 드레인 저항 감소, 접합 영역에서의 누설 전류 감소 및 콘택 저항을 감소시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, after epitaxial silicon is selectively deposited on the active region where the gate electrode is formed, the TiSi 2 layer is formed to reduce the source and drain resistance, and to reduce the leakage current in the junction region. And an excellent effect of reducing contact resistance.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046304A KR0172043B1 (en) | 1995-12-04 | 1995-12-04 | Method of fabricating a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046304A KR0172043B1 (en) | 1995-12-04 | 1995-12-04 | Method of fabricating a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970054374A KR970054374A (en) | 1997-07-31 |
| KR0172043B1 true KR0172043B1 (en) | 1999-02-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950046304A KR0172043B1 (en) | 1995-12-04 | 1995-12-04 | Method of fabricating a semiconductor device |
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| Country | Link |
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| KR (1) | KR0172043B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980053667A (en) * | 1996-12-27 | 1998-09-25 | 김영환 | Method of forming interlayer insulating film of semiconductor device |
-
1995
- 1995-12-04 KR KR1019950046304A patent/KR0172043B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980053667A (en) * | 1996-12-27 | 1998-09-25 | 김영환 | Method of forming interlayer insulating film of semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR970054374A (en) | 1997-07-31 |
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