KR19990003964A - Data Load Clock Generator of PDP-TV - Google Patents

Abstract

The present invention relates to an apparatus for implementing a display size of a PDP-TV. In particular, the present invention is a data load that can implement a wide screen (853 × 480, Wide Vision, aspect ratio 16: 9) and a general screen (640 × 480, aspect ratio 4: 3) in one PDP-TV system It relates to a clock generator. The display value of a typical PDP-TV is a 640x480 mode for implementing a conventional 4: 3 aspect ratio, and the display value for a wide screen is realized in an 853x480 mode for an aspect ratio of 16: 9. In the present invention, 480 shift clock signals (clk_480) and reference clock signals (clk) are input to the AND gate (10), and the shift clock signals (clk_480) are inputs of 8 counters (20) and 107 counters (40). The input signal is inputted as a set signal, and the output of the AND gate 10 is inputted to the eight counters 20 and simultaneously inputted to each end of the AND gate 30 together with the outputs of the eight counters 20. The output signal of the gate 30 is input to the 107 counter 40 and generates 107 clocks and outputs them to the multiplexer 50 so as to realize a screen value of 853x480 mode in the PDP-TV. The 13 counter 60 is coupled to the output terminal of the 107 counter 40, and the output of the 13 counter 70 is presented to be configured to be input to the multiplexer 50.

Description

A generating apparatus of data load clock for PDP-TV

The present invention relates to an apparatus for implementing a screen display of a specific size in a plasma display panel television (PDP-TV) system comprising a composite image signal input unit, a digital image data processor, and a PDP driver. In particular, the present invention relates to a data load clock generator capable of implementing both a screen size of 640 × 480 mode having an aspect ratio of 4: 3 and an 853 × 480 mode having a wide screen of 16: 9 in one PDP-TV system.

CRT, which is a general TV system, adopts a method in which an electron gun sequentially scans pixel by pixel, and gradation is composed of a simple driving circuit driven by an analog method, and its driving speed is very fast as several tens of nanoseconds (ns). If the number of pixels is increased to millions like HDTV, it is very difficult to implement the driving of millions of pixels by one pixel. However, in the case of the PDP, which is a flat panel display, a matrix driving method using a strong nonlinearity characteristic of gas discharge is used instead of scanning by pixel. Nonlinearity is a characteristic of gas discharge. Since the gas discharge phenomenon is caused by ionization through the ionization process of the gas, the discharge occurs only when a voltage higher than the discharge voltage at which the ionization reaction can occur sufficiently is applied. Is a characteristic of gas discharge in which no discharge occurs. PDPs are generally driven by a series of pulses with a constant voltage, and gradation display is implemented by digital rather than analog. However, since gas discharge usually requires a relatively high voltage of several hundred volts, the video signal is amplified and driven. The reason why the PDP is suitable for the enlargement is that not only the process but also the characteristics useful for the enlargement of the gas discharge can be applied to the driving method. The concept of driving technology of PDP is as follows. PDP is an active light emitting display device in which ultraviolet light generated by gas discharge excites a fluorescent film to implement an image. In other words, since the PDP uses ultraviolet light emitted by gas discharge as a light source corresponding to each pixel, the driving circuit simply functions to form or erase gas discharge for each pixel in order to implement a display image. The driving circuit includes an image signal and signal control unit for each pixel constituting an image, and a high speed high voltage switching control unit that can form or eliminate ultraviolet rays generated from each pixel. The driving operation of the PDP-TV system can be classified into three types: selection operation, holding operation and erasing operation.

The selection operation is a driving operation necessary for initial discharge formation. In the case of Pen + mixture of He + Xe and Ne + Xe commonly used in PDP, potential of 240V ~ 280V is applied. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation.

The holding operation is a driving operation in which discharge is maintained by a holding pulse having a voltage lower than a selection pulse by using the storage function characteristic of gas discharge. In the case of AC type PDP, the memory function effect by wall charge and the self priming effect are used in case of DC type PDP. In the case of the memory type driving method which can separate the selection operation and the holding operation by using the memory function, in the case of high gradation display for realizing a high quality display device, the PDP can operate without deterioration of luminance even for a large display device. It provides a driving method.

In the case of AC-type PDP, the discharge is formed at a low voltage in the period of neutralizing the subordinate charge so that the wall charge is not sufficiently formed, or the wall charge does not reach the normal state due to the erase pulse having a short pulse width. Remove

PDP using gas discharge has a memory function. The memory function is a phenomenon in which the past state affects the present state. In the case of AC PDP, it has a unique memory function due to the wall charges formed in the dielectric. In the case of DC PDP, the charged particle effect is used. Although the PDP adopts the driving method using the row driving method, it would not be possible to apply the large display without the memory function. The memory function is essential for driving a large display element for displaying a high gradation image, and it can be seen that it has a very useful function in gradation display. AC PDPs have a unique memory function because charged particles such as electrons and ions formed during gas discharge form wall charges in the dielectric covering the electrode. In other words, there is no wall charge in the dielectric when there is no discharge, and wall charge is accumulated in the dielectric when a discharge is formed. When the wall charge is present, the potential applied to the external electrode and the potential caused by the wall charge are added together, so that a discharge is formed at a low voltage. Thus, the operation of discharging at a low potential can be separated by the operation of discharging (addressing) without the help of wall charge and the help of the wall charge. In the case of the AC type PDP having the above characteristics, there is a memory function by wall charge, and various driving methods are used according to the method using such wall charge. The present invention relates to an apparatus for generating a clock for loading data in a data interface unit for outputting digital data to the PDP unit in the PDP-TV driven as described above.

In the PDP-TV system, the screen size is 640 × 480 mode at 4: 3 aspect ratio, and the wide screen size is 853 × 480 mode at 16: 9 aspect ratio. Is implemented. Referring to the operation of the PDP-TV system for implementing each of the screen size mode as follows. That is, the R, G, and B data output from the memory unit of the PDP-TV must be rearranged and supplied to the address driver IC according to the RGB pixel arrangement of the panel, which is why a data interface unit is required. In the 640 × 480 mode system, the data interface unit must temporarily store one line of data (640 × 3 = 1920bits) .Because data continuity must be guaranteed (input and output are performed simultaneously), two lines (1920 × 2) are used. = 3840bits) is needed. That is, a total of 24 bits of data of 8 bits each of R, G, and B are sequentially inputted from the memory unit (80 times) into the first temporary storage area (24 bits x 80 = 1920 bits), and at the same time interval, the second temporary storage area is inputted. The previous one-line amount of data is output in the form of a data stream required by the address driver IC. Such an input / output operation alternately occurs in the first and second temporary storage areas. That is, after the first temporary storage area operates in the input mode and the second temporary storage area operates in the output mode, the reverse operation is then repeated. However, in order to realize a wide screen of 853 × 480 mode, a panel having 8 bits accesses 853 ÷ 8 ≒ 107, that is, one weight of data can be loaded when addressing 107, so the 640 × 480 mode of the conventional apparatus can be loaded. There was a problem that can not be used as the data load clock generator of. Therefore, in the conventional PDP-TV system, there is a problem that a separate device that can be implemented for each display size of the above modes can be employed.

The present invention has been invented to solve the above-described defects of the conventional PDP-TV. In one PDP-TV, the display size of the wide screen (16: 9) of 853 × 480 mode and the general screen (4: 3) of 640 are described. It is an object of the present invention to provide a data load clock generator capable of implementing all x480 modes. The present invention provides a data load clock generator capable of accurately generating the above 107 clocks required to load data corresponding to one weight amount in a 150 clock period corresponding to one clock of clk_480. As an embodiment for achieving the above object of the present invention, the present invention first configures a data load clock generator of 853 × 480 mode and processes the clock inputted from the output terminal into a data load clock of 640 × 480 mode. The configuration of the x480 mode data load clock generator is provided to selectively output the output of the two clock generators by the mode control signal input to the multiplexer and input from the outside. That is, 480 shift clock signals clk_480 and reference clock signals clk are input to the AND gate 10, and the shift clock signals clk_480 are reset of the 8 counters 20 and 107 counters 40. A signal is inputted, and the output of the AND gate 10 is inputted to the eight counters 20 and simultaneously inputted to each end of the AND gate 30 together with the outputs of the eight counters 20, and the AND gates described above. The output signal of 30 is input to the 107 counter 40 and outputs valid data to the multiplexer 50, and the 13 counter 60 coupled to the output terminal of the 107 counter 40, and the above 13 The output of the counter 60 presents a data load clock generator having a configuration that is input to the multiplexer 50 through the 80 counter 70.

1 is a block diagram of a data load clock generator according to an embodiment of the present invention.

2 is a clock and data waveform diagram of each part of FIG.

3 is a block diagram showing the overall configuration of a PDP-TV system;

4 is a block diagram of a memory unit as a main part of FIG.

* Explanation of symbols on the main parts of the drawings

1: AV unit 2: ADC unit

3: memory section 4: data interface section

5: timing controller 6: address driving IC

7: holding / scanning driving IC 8: high voltage driving circuit

9: AC / DC switch 10,30: end gate

20: 8 counter 40: 107 counter

50: multiplexer 60: 13 counter

70: 80 counter 80: composite video signal processor

90: digital data processing unit 100: PDP drive unit

110: data rearrangement unit 120: address generation unit

130: control clock generator

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Accompanying drawings, Figure 3 is for explaining the overall operation of the AC-type PDP-TV system. The PDP-TV generally includes a composite video signal processing unit 80 including an AV unit 1 which analog-processes a composite video signal received through an antenna and provides it to an ADC unit, and digitally processes the input analog composite video signal. The ADC unit 2 for performing the operation, the memory unit 3 for rearranging the digital image data input from the composite video signal unit 50, and the rearranged digital image data, and are suitable for PDP gray level processing. Digital data comprising a data interface unit 4 for producing a stream, the memory unit 3, the data interface unit 4, and a timing controller unit 5 for generating and supplying a main clock for controlling the entire system. Maintaining / Notes with the address driver IC 6 receiving the data stream from the processing unit 90 and the data interface unit 4 and supplying data to the plasma panel for gradation processing It consists of the PDP drive part 100 which consists of the four drive | operation IC7. The AV unit 1 receives the NTSC composite signal, separates the analog R, G, and B signals from the horizontal and vertical synchronization signals, and obtains an APL (Average Picture Level) corresponding to the average value of the luminance signal (Y). It supplies to (2). This APL is used to improve the brightness of PDP-TV systems. NTSC composite video signal is interlaced scanning method, and one frame is composed of two fields of Odd / Even, horizontal synchronous signal is about 15.73KHZ, and vertical synchronous signal is about 60Hz. The audio signal separated from the composite video signal is output through the audio amplifier directly to the speaker. The ADC unit 2 receives analog R, G, and B signals as inputs, converts them into digital data, and outputs them to the memory unit 3. At this time, the digital data is converted into shapes for improving the brightness of the PDP-TV system. Video data. The ADC section 2 is divided into an amplifier section, a clock generation section, a sampling area setting section, and a data mapping section. The amplifying section in the ADC section 2 amplifies the analog R, G, B and APL signals to a signal level suitable for quantization, and converts the horizontal and vertical synchronization signals into a constant phase and outputs them. The clock generator must use a clock that is synchronized with the input synchronization signal. To this end, the clock generator generates clocks using phase locked loops (PLLs). The PLL is oscillated by the LF (Loop Filter), which outputs the control voltage of PD (Phase Detector), VCXO (Voltage Controlled Crystal Oscillstor), which compares the phase of the input synchronous signal with the phase of the variable pulse output from the loop. A VCXO and a PC (Programmable Counter) for dividing the output of the VCXO and outputting a phase comparison pulse to output a clock synchronized with the input synchronous signal. If the clock synchronized to the input synchronization signal is not used, the vertical linearity of the displayed image is not guaranteed. In addition, the sampling area is set to a vertical position and a horizontal position. The vertical position section is a pulse for setting only the line with the image information among the input signals, and the horizontal position section is a pulse for setting only the time with the image information among the lines set to the vertical position. The vertical position section and the horizontal position section are the standards for sampling. At this time, a total of 480 lines are selected, each with 240 lines in the Odd / Even field. The horizontal position section should be such that there can be at least 853 sampling clocks per selected line. The data mapping unit of the ADC unit 2 maps the R, G, and B data output from the A / D converter into data corresponding to the brightness characteristics of the PDP. In other words, by arranging several vector tables in the ROM and selecting the optimal vector table according to the digitized APL data, the R, G, B, and R: It is provided to the memory unit 3 in the form of B data.

In the memory unit 3, for the PDP gradation processing, it is necessary to reconstruct the video data of one field into a plurality of subfields, and then rearrange from the most significant bit MSB to the least significant bit LSB. In addition, since the image data input by the interlaced scanning method is converted to the progressive scanning method and displayed, an area for storing one frame of image data is required.

4 is a block diagram of a memory unit that performs the above functions. That is, the memory unit 3 can be largely divided into the data rearrangement unit 110 and the address generator 120. The memory unit 3 also includes a control clock generator 130, two frame memories A, B, and a data selector. The data rearrangement unit 110 is composed of shift registers A, B, D-FF MUX. (D flip-flop and multiplexer), and three-state buffers A, B, and the ADC unit 2 in parallel (MSB to LSB). The provided image data is rearranged so as to store bits having the same weight in one address of the frame memory. While the first shift register loads eight samples of image data, in the second shift register, eight samples of image data previously loaded are the least significant bit (LSB, 8) from the most significant bit (MSB, 8 Bits). Bits) are output while sequentially shifting.

In order to continuously rearrange the video data provided by the ADC unit 2, two first and second shift registers are provided, and they alternately load and shift. The D-FF MUX selects the same weighted data (Recordered Data) output in the shift mode and supplies it to the tri-state buffer. In addition, two frame memories are provided for storing one piece of image data (853 x 3 (RGB) x 480 x 8 Bits x 10 Mbit), and they alternately perform write and read operations in units of frames. The video data can be stored and displayed continuously. Therefore, the tri-state buffers A and B serve to connect the rearranged image data provided from the D-FF MUX to the frame memory in the write mode. Since the address generator 120 converts and displays the image data input by the interlaced scanning method in a sequential scanning method, the order of write addressing and read addressing are different. That is, image data of one field stored in the memory is repeatedly read even line data after reading one line of Odd line data. Further, in the PDP gradation process, one field is divided into several subfields, and image data corresponding to each subfield must be read in turn and provided to the data interface unit 4, so that the reading order is structurally very different from the writing order. Will have Therefore, a write address generator and a read address generator according to the designed memory map configuration are required, and the address selector serves to provide a corresponding address according to each operation mode (write and read mode) of the frame memories A and B. The control clock generator 130 receives the vertical and horizontal synchronization signals H and Vsync and the main clock as inputs to generate and supply the write / read address clock and all other logic control pulses required to drive the memory unit 3. . The data selector selects and outputs the image data output in the read mode from the frame memories A and B to the data interface unit 4. The data interface unit 4 temporarily stores R, G and B data from the memory unit 3 and provides the data in the form of data required by the address driver IC 6. It is required to be arranged in accordance with the arrangement of the R, G, and B pixels output from the memory section 3 and supplied to the address driver IC 6, which is why the data interface section 4 is required.

The case where the display size is 853 x 3 (r, g, b) x 480 mode in the above-described PDP-TV system will be described. In the data interface unit 4, one line (853 x 3 = 2559) is used. It is necessary to temporarily store the data of bits. Since the continuity of the data must be guaranteed (input and output are performed simultaneously), a temporary storage place of 2 lines (2559 x 2 = 5118 bits) is required. That is, a total of 24 bits of data of 8 bits each of R, G, and B from the memory unit 3 are sequentially inputted to the first temporary storage area (107 times) (24 bits x 107 = 2598 bits), and at the same time intervals, the second temporary data is stored. The data of the previous one line of the storage area is output in the form of a data stream required by the address driver IC 6. Such an input / output operation alternately occurs in the first and second temporary storage areas. That is, after the first temporary storage area operates in the input mode and the second temporary storage area operates in the output mode, the reverse operation is then repeated. When the data interface 4 outputs the temporarily stored video data to the address driver IC 6, the data interface unit 4 provides 1 bit of data and 48 bits of video data in a stream form to each driver IC. When data is input to the driver IC in turn (75 times) in this manner, when shifted in parallel, one line of image data (48 bits x 75 = 3600 bits) is loaded into the address driver IC 6. Since this process should be the same as the input mode operation time of other temporary storage areas, the input mode should be operated at twice the frequency of the output mode. The high voltage drive circuit section 8 is required by the address, scan and sustain driver ICs by combining the DC high voltage supplied from the AC / DC converter section 9 according to the control pulses of various logic levels output from the timing controller section 5. Generate a control pulse so that the PDP can be driven. In addition, the data stream provided from the data interface unit 4 to the address driver IC 6 is also raised to an appropriate voltage level to enable selective writing on the panel. As described above, the driving method for the PDP gradation process first divides one field (60 Hz) into several subfields (64 gradations: 6 subfields, 256 gradations: 8 subfields), and then divides the image data corresponding to each subfield. Through the address driving IC 6, writing is performed in units of lines. In the subfield to which MSB data is written, the number of discharge sustain pulses is reduced in order from the LSB subfield, and gradation processing is performed in the total discharge sustain period according to a combination thereof. In addition, the driving sequence of all subfields repeats operations of full screen writing and erasing, data writing, and discharge holding (screen display). This process is outlined as follows.

As the operation mode for erasing discharge, in case of AC PDP, the discharge is formed at low voltage in the period of neutralizing the subordinate charge so that the wall charge is not sufficiently formed or the erase charge pulse having short pulse width is applied to the normal state of the wall charge. To prevent the wall charges from being reached, i.e. to erase the wall charges remaining in the selected (discharged) pixels after sustaining the discharge of the previous subfield, the walls on all the pixels for a short period of time that are not visible. A full screen erasing process of initializing the PDP by writing charges and then erasing all the remaining wall charges by erasing all pixels;

In the case of Pen + mixture of He + Xe and Ne + Xe commonly used in PDP, potential of 240V ~ 280V is applied. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation. In the practical application, a selective operation is performed in which a wall charge is selectively formed on a pixel to be discharged by writing the data in line units through the data writing electrode while shifting the scanning pulse sequentially from 1 to 480 to the line scan electrode. In addition, the data writing and scanning process, which is a driving operation required for initial discharge formation,

In the case of AC PDP, the memory driving method that can separate the selection operation and the holding operation by using the memory function effect by wall charge, and the PDP is large in the case of high gradation display to realize high quality display device. A driving method which can operate without deterioration of brightness also in the display element of is provided. In practice, a sustain pulse is alternately applied between the discharge sustain driver electrode and the line scan electrode to start and sustain the discharge of the pixel on which the wall charge is formed. At this time, since the unwritten pixel is affected by the written peripheral pixels, and there is a possibility of causing an error discharge, the discharge sustaining process is performed so that a small amount of erase is performed every time the sustain pulse is applied.

In the AC / DC converter 9, AC power (220V, 60Hz) is input, and the high voltage required to combine the electrode driving pulses shown in FIG. 8 and the DC voltage required by each part constituting the other PDP-TV system. Create and supply

Hereinafter, embodiments of the present invention will be described in detail with reference to the configuration and operation of the entire system of the PDP-TV. 1 is a diagram illustrating a data load clock generator for implementing 853 × 480 mode and a data load clock generator for implementing 640 × 480 mode in series, and an output of each mode is input to a multiplexer. It is a block diagram. In the case of 853 x 480, the display is performed for each weight of data and the discharge maintenance operation is repeated. Since the shift clock (clk_480) is information on line scanning, it is enough to display data for one line of one weight for one period. Therefore, a clock that only loads 853 data is required, and since 8bits are tied together, 853 ÷ 3 ≒ 107, that is, addressing 107 times is required. In addition, in 640x480 mode, 640 ÷ 8 = 80, that is, 80 addressing is required. However, unlike 853 × 480 mode, 640 × 480 mode has blank sections left and right, and the total addressing time is 107 addressing times, so 13 and 14 addressing times are given as blank time, respectively. In the present invention, an apparatus for generating a load clock of each mode in one PDP-TV is implemented as follows.

The clock signal (clk_480) and the reference main clock signal (clk) required for data shifting are input to each end of the AND gate 10, so that one section of eight subfields included in one frame of the vertical synchronization signal is maintained with an addressing section. 480 shift clocks (clk_480) exist in the addressing section, and the shift clock (clk_480) signal and the reference clock coincide in the shift clock section in which 150 reference clocks exist. When the signal is output to the eight counter 20, the eight counter 20 outputs a signal delaying the first eight clocks among the 150 clocks of the clk_480 1 section to one end of the AND gate 30, The output of the AND gate 10 is input to the other end of the AND gate 30, the output corresponding to the AND gate 30 is input to the 107 counter 40 counting 107 clocks, At 107 counter above 107 clock signals required to load my weight amount of data are generated and output to the multiplexer 50, and the output terminal of the 107 counter 40 includes 13 counters 60 corresponding to the 640x480 mode clock generator. Combined, the clock output from the 13 counter (60) is input to the 80 counter 70 is composed of a device for outputting the data load clock of the 640 × 480 mode to the multiplexer (50).

2 is a waveform diagram of the operation of each part according to the configuration of the present invention described above. Referring to Figure 2 will be described in detail the operation of the data load clock generator of the present invention. In the case of the 8-bit access, basically, 480 shift clocks (clk_480) and the main clock (clk), which are the reference clocks, are included in the addressing section of the section corresponding to one subfield including the addressing section and the discharge holding section. The AND gate 10 is input to the AND gate 10, and the AND gate 10 outputs one section of the shift clock CLK_480 and 150 main clocks CLK corresponding thereto to the eight counters 20. The eight counter 20 delays eight clocks from the first clock of the 150 main clocks and then turns on the shift clock CLK_480 to input one end of the AND gate 30. The output of the AND gate 10 is input to one end of the AND gate 30. One load clock (clk_load1) outputs a signal matched by the AND gate 30 to the 107 counter 40, and the 107 counter 40 generates 107 clocks and loads data using the clocks. ) And the valid data (data valid1) and blank signal (blank1) are provided to the multiplexer 50.

3 is a waveform diagram of input and output terminals of the 13 counter 60 and the 80 counter 70 corresponding to the data load clock generation unit in the 640x480 mode. That is, in the 13 counter 40 which receives the load clock (clk_load 1) and the valid data (data valid 1) output from the 107 counter 40, a time delay of 13 clocks is performed at the start of the 107 load clock. And a blank signal (blank 2) for inverting the 80 load clocks (clk_load 2), the valid data (data valid 2) and the signal by counting 80 clocks in the 80 counter 70. To the multiplexer 50, wherein the multiplexer 50 includes a load clock (clk_load 1), valid data (data valid 1) and a blank signal (blank 1) input from the 107 counter. The load clock (clk_load 2), valid data (data valid 2) and blank signal (blank 2) inputted at 70 are selected and output according to the mode control signal inputted from the outside.

As described above, in the generation of a clock for loading data, the present invention receives a wide display size of 853x480 mode and a general display size of 640x480 mode in one PDP-TV. There is an effect that can be displayed on the PDP regardless of the format of the video signal. In addition, in the generation of data load clocks for each 상, it is necessary to load one weight of data using 8 counters 20 and 107 counters 40 in the logic design that 150 main clocks are included in the shift clock address interval. By accurately generating 107 clocks, and accurately generating the 107 clocks back to the 80 clocks required for the 640x480 mode, the data is loaded, thereby preventing errors in data loading due to unnecessary clocks. There is.

Claims (4)

In a PDP-TV (Plasma Display Panel Television) system that receives a composite video signal and provides digitally processed data from the digital data processing unit 90 to the PDP driving unit 100 via the data interface unit 4 to display the screen. An AND gate 10 to which 480 shift clock signals clk_480 and a reference clock signal clk are input at each stage, and an 8 counter 20 that delays and outputs the signals of the AND gate 10 by 8 clocks; The input signal of the AND gate 10 and the eight clock delay signal of the eight counter 20 are input to each stage, and the output signal of the AND gate 30 is received. 107 counter 40 for generating a load clock, 13 counter 60 for receiving the 107 load clock and valid data of the 107 counter 40 and delaying the 107 load clock by 13 clocks, and 13 counter Receives 60 clock 13 delay signals An 80 counter 70 that counts and generates a declock, the load clock clk_load 1 of the 107 counter 40, data valid 1 and a blank signal blank 1, and the 80 counter 70 is a multiplexer 50 for receiving a load clock (clk_load 2), valid data (data valid 2) and a blank signal (blank 2) to select and output according to the mode control signal input from the outside Data load clock generator of PDP-TV. The apparatus of claim 1, wherein the 107 load clock is a signal required to load one weight of data from the PDP-TV having a display size of 853x480 mode. The data load clock generator of claim 1, wherein the 80 load clock is a signal required to load one weight of data from the PDP-TV having a display size of 640x480 mode. 2. The PDP-TV of claim 1, wherein the blank signal blank 2 is configured to give an addressing time of 13 clocks at the front end of the load clock clk_load 1 and 14 clocks at the rear end. Data load clock generator.