KR19990003525A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990003525A KR19990003525A KR1019970027406A KR19970027406A KR19990003525A KR 19990003525 A KR19990003525 A KR 19990003525A KR 1019970027406 A KR1019970027406 A KR 1019970027406A KR 19970027406 A KR19970027406 A KR 19970027406A KR 19990003525 A KR19990003525 A KR 19990003525A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 abstract description 11
- 230000000694 effects Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010000 carbonizing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
본 발명은 사이드월 스페이서를 사용하지 않고 게이트 전극 하부에 LDD 구조를 형성함으로써 전류 구동력을 힝상시킨 LDD 구조의 반도체 소자 제조 방법에 관한 것으로, 반도체 기판에 트렌치 구조의 소자 분리막 및 활성 영역을 형성하는 단계, 전체 구조 상부에 게이트 산화막 및 제 1 폴리실리콘막을 차례로 증착하는 단계, 상기 제 1 폴리실리콘막 상에 사진 공정을 통하여 제 1 게이트 마스크 패턴을 형성하는 단계, 상기 제 1 폴리실리콘막을 식각하여 패턴을 형성하되, 식각되는 영역의 상기 제 1 폴리실리콘막이 소정량 남도록 식각하여 게이트 패턴을 형성한 후 상기 제 1 게이트 마스크 패턴을 제거하는 단계, 전체 구조 상에 저농도 이온 주입 공정을 실시하여 상기 게이트 패턴에 인접한 하부 활성 영역에 저농도 LDD 영역을 형성하는 단계, 전체 구조 상에 제 2 폴리실리콘막을 증착한 후 상기 제 1 폴리실리콘막 패턴의 상부까지 평탄화하는 단계, 전체 구조 상에 금속막과 아크층을 차례로 증착하는 단계, 상기 아크층 상에 제 2 게이트 마스크 패턴을 형성하여 상기 게이트 산화막 상까지 식각하며, 상기 제 1 게이트 마스크 패턴보다 소정 부분 넓게 형성하여 게이트 전극을 형성하는 단계 및 전체 구조 상에 고농도 이온 주입 공정을 실시하여 상기 저농도 LDD 영역에 고농도 접합 영역을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method for fabricating an LDD structure semiconductor device in which the current driving force is subtracted by forming an LDD structure under the gate electrode without using sidewall spacers, and forming a device isolation film and an active region having a trench structure in the semiconductor substrate. Depositing a gate oxide layer and a first polysilicon layer on the entire structure in order, forming a first gate mask pattern on the first polysilicon layer through a photo process, and etching the first polysilicon layer to form a pattern. Forming a gate pattern by etching the first polysilicon layer in an etched region so that a predetermined amount remains, and removing the first gate mask pattern, and performing a low concentration ion implantation process on the entire structure to form a gate pattern. Forming a low concentration LDD region in an adjacent lower active region, the overall structure Depositing a second polysilicon film on the substrate, and then planarizing it to an upper portion of the first polysilicon film pattern, sequentially depositing a metal film and an arc layer on the entire structure, and depositing a second gate mask pattern on the arc layer. And forming a gate electrode by etching the gate oxide layer, forming a predetermined portion wider than the first gate mask pattern, and performing a high concentration ion implantation process on the entire structure to form a high concentration junction region in the low concentration LDD region. Characterized in that it comprises a step.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 사이드월 스페이서를 사용하지 않고 게이트 전극 하부에 LDD 구조를 형성함으로써 전류 구동력을 향상시킨 LDD 구조의 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an LDD structure in which an LDD structure is formed below a gate electrode without using sidewall spacers to improve current driving force.
최근 반도체 산업 전반에 걸쳐 반도체 소자의 빠른 동작과 고집적화를 이루기 위해 반도체 소자의 디자인 룰을 감소시키고 있다. 그러나, 소자의 채널 길이를 축소한 단채널 소자의 경우, 장채널에 비해 소자에 인가하는 전압을 낮추지않는 한, 소오스와 드레인 간에 걸리는 전기장 세기가 증가해 채널의 캐리어를 가속시키고, 이렇게 가속된 캐리어는 게d트 산화막 등으로 주입되어 소자의 특성을 열화시킨다. 이를 핫 캐리어 효과라고 한다.Recently, in order to achieve rapid operation and high integration of semiconductor devices throughout the semiconductor industry, design rules for semiconductor devices have been reduced. However, in the case of a short channel device having a reduced channel length of the device, the electric field strength between the source and the drain increases to accelerate the carrier of the channel, unless the voltage applied to the device is lowered compared to the long channel. Is injected into a get oxide film or the like to deteriorate the characteristics of the device. This is called the hot carrier effect.
이를 개선하기 위하여 LDD(Lightly Doped Drain) 구조가 제안되었는데, 이 구조는 소오스/드레인 접합의 채널과 인접한 영역에 저농도 접합층인 LDD 영역을 형성하는 것을 말한다. 도 1은 종래의 LDD 구조의 반도체 소자를 나타낸 것으로 간략하게 제조 방법을 설명하면, 먼저 반도체 기판(10)의 소자 분리막(11) 사이의 소정의 활성 영역 상에 게이트 산화막(12) 및 게이트 전극(13)을 형성한 다음, 저농도 N형 이온 주입을하여 저농도 LL)D 영역(14a)을 형성한다. 그 다음, 게이트 전극(13) 측면에 사이드월 스페이서(15)를 형성하여 고농도 N형 이온 주입함으로써 상기 저농도 LDD 영역(14a) 상에 고농도 접합 영역(14b)을 형성한다. 이렇게 채널에 인접하여 형성된 저농도 LDD 영역은 전기장의 세기를 낮춰 핫 캐리어의 효과를 방지할 수 있다.In order to improve this, a lightly doped drain (LDD) structure has been proposed, which refers to forming an LDD region, which is a low concentration junction layer, in a region adjacent to a channel of a source / drain junction. FIG. 1 illustrates a conventional LDD structure semiconductor device. In brief, a manufacturing method will be described. First, the gate oxide film 12 and the gate electrode 12 may be formed on a predetermined active region between the device isolation layers 11 of the semiconductor substrate 10. 13), then a low concentration N-type ion implantation is performed to form a low concentration LL) D region 14a. Next, the sidewall spacer 15 is formed on the side of the gate electrode 13 to form a high concentration N-type ion implantation, thereby forming a high concentration junction region 14b on the low concentration LDD region 14a. The low concentration LDD region formed adjacent to the channel may reduce the electric field strength to prevent the effect of hot carriers.
그러나, 상기와 같이 사이드월 스페이서를 이용한 LDD 구조는 접합 영역이 반도체 소자의 사이드월 스페이서 하부에 위치하게 되어 반도체 소자의 전류 구동력을 저하시키는 문제점이 있다.However, as described above, the LDD structure using the sidewall spacer has a problem in that the junction region is located under the sidewall spacer of the semiconductor device, thereby lowering the current driving force of the semiconductor device.
따라서, 본 발명은 종래와 같이 단채널로 인한 핫 캐리어 효과를 개선함과 동시에 사이드월 스페이서를 이용한 접합 구조로 인해 저하된 전류 구동력을 향상시키는 LDD 구조의 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having an LDD structure which improves the current driving force that is reduced due to the junction structure using sidewall spacers while improving the hot carrier effect due to a short channel as in the related art. .
도 1은 종래 기술에 따른 사이드-월을 갖는 LDD 구조의 트랜지스터를 나타내는 단면도1 is a cross-sectional view showing a transistor of an LDD structure having a side-wall according to the prior art.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 LDD 구조의 N형 모스 트랜지스터 제조 공정을 나타내는 단면도.2A to 2D are cross-sectional views illustrating a process for manufacturing an N-type MOS transistor having an LDD structure according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10,20 : 반도체 기판 11,21 : 소자 분리막10,20: semiconductor substrate 11,21: device isolation film
12,22 : 게이트 산화막 13 : 게이트 전극12,22 gate oxide film 13: gate electrode
23a,23b : 폴리실리콘막 14a,24a : 저농도 LDD 영역23a, 23b: polysilicon film 14a, 24a: low concentration LDD region
14b,24b : 고농도 접합 영역 15 : 사이드월 스페이서14b, 24b: high concentration junction region 15: sidewall spacer
25 : 텅스텐 실리사이드막 26 : 아크 산화질화막25 tungsten silicide film 26 arc oxynitride film
27 : 마스크 패턴27: mask pattern
상기 목적을 달성하기 위하여, 본 발명에 따른 LDD 구조의 반도체 소자를 제조함에 있어서, 반도체 기판에 트렌치 구조의 소자 분리막 및 활성 영역을 형성하는 단계, 전체 구조 상부에 게이트 산화막 및 제 1 폴리실리콘막을 차례로 증착하는 단계, 상기 제 1 폴리실리콘막 상에 사진 공정을 통하여 제 1 게이트 마스크 패턴을 형성하는 단계, 상기 제 1 폴리실리콘막을 식각하여 패턴을 형성하되, 식각되는 영역의 상기 제 1 폴리실리콘막이 소정량 남도록 식각하여 게이트 패턴을 형성한 후 상기 제 1 게이트 마스크 패턴을 제거하는 단계, 전체 구조 상에 저농도 이온 주입 공정을 실시하여 상기 게이트 패턴에 인접한 하부 활성 영역에 저농도 LDD 영역을 형성하는 단계, 전체 구조 상에 제 2 폴리실리콘막을 증착한 후 상기 제 1 폴리실리콘막 패턴 상부까지 평탄화하는 단계, 전체 구조 상에 금속막과 아크층을 차례로 증착하는 단계, 상기 아크층 상에 제 2 게이트 마스크 패턴을 형성하여 상기 게이트 산화막 상까지 식각하며, 상기 제 1 게이트 마스크 패턴보다 소정 부분 넓게 형성하여 게이트 전극을 형성하는 단계 및 전체 구조 상에 고농도 이온 주입 공정을 실시하여 상기 저농도 LDD 영역에 고농도 접합 영역을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, in the manufacturing of the LDD structure semiconductor device according to the present invention, forming a device isolation film and an active region of the trench structure on the semiconductor substrate, the gate oxide film and the first polysilicon film in order over the entire structure Depositing, forming a first gate mask pattern on the first polysilicon film through a photolithography process, etching the first polysilicon film to form a pattern, wherein the first polysilicon film in the etched region is small Removing the first gate mask pattern after etching to quantitatively remain to form a gate pattern, and performing a low concentration ion implantation process on the entire structure to form a low concentration LDD region in the lower active region adjacent to the gate pattern Depositing a second polysilicon film on the structure, and then up to the first polysilicon film pattern Carbonizing, depositing a metal layer and an arc layer on the entire structure in turn, forming a second gate mask pattern on the arc layer to etch the gate oxide layer, and widening a predetermined portion wider than the first gate mask pattern. Forming a gate electrode and performing a high concentration ion implantation process on the entire structure to form a high concentration junction region in the low concentration LDD region.
[실시예]EXAMPLE
이하, 첨부된 도면을 참조로하여 본 발명의 일실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a에서 2d는 본 발명의 일실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도로, N형 LDD 구조의 모스 트랜지스터에 대해서만 간략하게 설명하기로 한다. 먼저, P-웰(도시하지 않음)이 형성된 반도체 기판(20)에 트렌치 분리 공정을 이용하여 두꺼운 산화막을 형성한 후, 이를 화학적·기계적 연마(CMP)로 평탄화하여 소자 분리막(21)을 형성한다. 그 다음, 반도체 기판 상에 게이트 산화막(22)과 제1 폴리실리콘막(23a)을 증착한 후 제1 폴리실리콘막 상에 제1 마스크 패턴을 형성하되, 종래의 사이드월 스페이서 부분이 없는 게이트 크기로 형성하여 식각 공정을 진행한다. 그리고, 식각은 노출되는 제1 폴리실리콘막이 약 100Å 정도 남을 때까지 한 다음, 상기 제1 폴리실리콘 패턴 상의 마스크 패턴(도시하지 않음)을 제거하고 저농도 N형 이온 주입 공정을 실시하여 저농도 LDD 영역(24a)을 형성한 것이, 도 2a에 도시되어 있다. 계속해서, 전체 구조 상에 제2 폴리실리콘막을 증착하고, 도 2d에 나타난 바와 같이, 화학적·기계적 연마로 제2 폴리실리콘막(23b)을 평탄화한 다음, 그 상부에 게이트 전극의 저항을 낮추기 위한 텅스텐 실리사이드막(25) 및 후속되는 사진 공정의 원활한 진행을 위하여 아크 산화질화막(ARC TiN)(26)을 차례로 증착한다. 그 다음, 사진 공정을 통하여 전체구조 상에 도 2c와 같이, 종래의 게이트 전극과 사이드월 스페이서를 합한 크기의 제2 마스크(27)를 형성하여 제1 폴리실리콘막까지 식각한다. 계속해서, 도 2d에 도시된 바와 같이 고농도 N형 이온 주입 공정을 통하여 저농도 LDD 영역(24a) 상에 고농도 N형 접합 영역(24b)을 형성하여 열공정을 거쳐 LDD 구조를 갖는 반도체 소자의 접합 영역을 형성한다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and only a MOS transistor having an N-type LDD structure will be briefly described. First, a thick oxide film is formed on a semiconductor substrate 20 having a P-well (not shown) by using a trench isolation process, and then planarized by chemical and mechanical polishing (CMP) to form the device isolation film 21. . Next, after the gate oxide film 22 and the first polysilicon film 23a are deposited on the semiconductor substrate, a first mask pattern is formed on the first polysilicon film, but the gate size without the conventional sidewall spacer portion is formed. It is formed to proceed with the etching process. Then, etching is performed until the exposed first polysilicon layer is about 100 ms, and then a mask pattern (not shown) on the first polysilicon pattern is removed and a low concentration N-type ion implantation process is performed to remove the low concentration LDD region ( Forming 24a) is shown in FIG. 2A. Subsequently, a second polysilicon film is deposited on the entire structure, and as shown in FIG. 2D, the second polysilicon film 23b is planarized by chemical and mechanical polishing, and then a lowering resistance of the gate electrode is formed thereon. An arc oxynitride film (ARC TiN) 26 is sequentially deposited in order to smoothly proceed the tungsten silicide film 25 and the subsequent photographic process. Next, as shown in FIG. 2C, a second mask 27 having a size in which a conventional gate electrode and sidewall spacers are combined is etched to the first polysilicon film through a photographic process. Subsequently, as shown in FIG. 2D, a high concentration N-type junction region 24b is formed on the low concentration LDD region 24a through a high concentration N-type ion implantation process to thermally process the junction region of the semiconductor device having the LDD structure. To form.
따라서, 본 발명에서와 같이 사이드월 스페이서를 사용하지 않고 형성된 LDD 구조의 반도체 소자는 종래와 같이 핫 캐리어 효과를 방지할 뿐만 아니라, 접합 영역이 상부의 게이트 전극과 일부분 겹치게 됨으로써 전류 구동력을 향상시킬 수 있어 반도체 소자의 동작 속도를 높일 수 있다.Therefore, the LDD structure semiconductor device formed without using the sidewall spacer as in the present invention not only prevents the hot carrier effect as in the related art but also improves the current driving force by partially overlapping the junction region with the upper gate electrode. Therefore, the operation speed of the semiconductor device can be increased.
이상에서 설명한 바와 같이, 핫 캐리어 효과를 방지하기 위하여 채널 영역에 저농도 LDD 영역을 형성하되, 사이드월 스페이서를 사용하지 않고 LDD 구조의 접합 영역을 형성함으로써 게이트 전극 하부에 일부 접합 영역이 겹치게하여 소자의 전류 구동력을 향상시켜 동작 속도를 높일 수 있다.As described above, in order to prevent the hot carrier effect, a low concentration LDD region is formed in the channel region, but a junction region having an LDD structure is formed without using sidewall spacers so that some junction regions overlap the lower portion of the gate electrode. The operating speed can be increased by improving the current driving force.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970027406A KR100235625B1 (en) | 1997-06-25 | 1997-06-25 | Method of manufacturing semiconductor device |
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| KR1019970027406A KR100235625B1 (en) | 1997-06-25 | 1997-06-25 | Method of manufacturing semiconductor device |
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| KR19990003525A true KR19990003525A (en) | 1999-01-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030055689A (en) * | 2001-12-27 | 2003-07-04 | 동부전자 주식회사 | Method for manufacturing silicide layer of semiconductor device |
| KR100419744B1 (en) * | 2001-06-28 | 2004-02-25 | 주식회사 하이닉스반도체 | Method for manufacturing a transistor |
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1997
- 1997-06-25 KR KR1019970027406A patent/KR100235625B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100419744B1 (en) * | 2001-06-28 | 2004-02-25 | 주식회사 하이닉스반도체 | Method for manufacturing a transistor |
| KR20030055689A (en) * | 2001-12-27 | 2003-07-04 | 동부전자 주식회사 | Method for manufacturing silicide layer of semiconductor device |
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| KR100235625B1 (en) | 1999-12-15 |
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