KR19980086112A - Output data rearrangement device of frame memory - Google Patents

Abstract

Disclosed is an output data rearrangement apparatus of a frame memory in a motion compensator. The output data rearrangement apparatus of the frame memory sequentially reads and stores the pixel data of the macroblock predicted from the start address and the motion vector of the current macroblock to be motion compensated in frame units up to three blocks from the frame memory. By shifting the pixel data output in the box order over a maximum of three blocks from the data storage unit by a predetermined number of times according to the pixel address of the reference point of the predicted macroblock, the data storage unit is effective for the predicted macroblock. And a data sorting unit for extracting pixel data. Therefore, by reading a box unit over a maximum of three blocks according to the pixel address of the reference point of the predicted macroblock, and shifting left by up to seven times, the pixel data corresponding to the predicted macroblock may be rearranged.

Description

Output data rearrangement device of frame memory

The present invention relates to a motion compensation device, and more particularly, to an apparatus for rearranging output data of a frame memory.

The motion compensation technique used in the Moving Picture Experts Group (MPEG) -2 standard is to reduce temporal redundancy by estimating and compensating for motion between two adjacent temporal pictures in macroblock units. That is, in the motion estimation and compensation process, a neighboring image is compared with the current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector.

In an MPEG-2 video encoder using such a motion compensation technique, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture performs the current picture. The best one is selected from among motion compensation blocks obtained by performing forward motion compensation, reverse motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture.

The frame memory is used to store the I picture or P picture of the previous picture and the I picture or P picture of the next picture as the reference picture for motion compensation. In addition, the frame memory is used to temporarily store the decoded picture and read out the display order in a MPEG-2 video decoder because the decoding order and the display order are different from each other.

However, the frame memory as described above must have a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, and thus the price thereof is expensive, and therefore, the entire picture. In addition to raising the price of the decoder, there is a problem that the delay time from the completion of decoding to the display increases.

Accordingly, an object of the present invention is to solve the above-mentioned problems, in order to solve the above-mentioned problems, an area for storing reference image data when compensating for motion, an area for storing decoded image data for display, and a coded bitstream input to an image decoder. In a frame memory in which a region is implemented on one memory module, pixel data corresponding to a macroblock predicted by a start address and a motion vector of a current macroblock is read in units of boxes over a maximum of three blocks, and then predicted. An apparatus for rearranging pixel data corresponding to a macroblock is provided.

In order to achieve the above object, an output data rearrangement apparatus of a frame memory according to the present invention is a frame memory for storing pixel data for reference in motion block compensation in a macroblock unit.

A data storage unit sequentially reading and storing pixel data of a macroblock predicted from a start address and a motion vector of a current macroblock to be motion compensated, in box units, up to three blocks from the frame memory; And

By shifting the pixel data output from the data storage unit in a box order over a maximum of three blocks by a predetermined number of times according to the pixel address of the reference point of the predicted macroblock, effective pixel data corresponding to the predicted macroblock is obtained. It characterized in that it comprises a data sorting unit to extract.

1 is a diagram showing the structure of a frame memory adopted in the present invention;

FIG. 2 is a view illustrating an example of a method for setting a RAS box for one frame in the frame memory shown in FIG. 1;

3 is a view showing an example of a macroblock structure in the RAS box shown in FIG.

4 is a diagram illustrating an example of a position of a predicted macroblock;

5A and 5B are block diagrams showing the configuration of an output data rearrangement apparatus of a frame memory according to the present invention.

* Explanation of symbols for main parts of the drawings

200: memory controller 300: frame memory

310: data storage unit 350: data sorting unit

31a to 31c: first to third block data storage units 35a to 35g: first to seventh shifters

F11 ~ F64: Flip-flop L11 ~ L47: Latch

M1 ~ M23: Multiplexer C1 ~ C7: Counter

300-1 to 300-4: First to fourth frame storage areas 500: Common bus

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 1 illustrates a structure of a frame memory adopted in the present invention. The frame memory 300 includes a restored memory data write operation, a data read operation for motion compensation, and a data read operation for display. SYNC (Synchronous-DRAM) with a burst length of 8, which is controlled by a? The frame memory 300 has two memory banks, bank 1 and bank 2, bank 1 has first and second frame storage areas 300-1 and 300-2, and bank 2 stores third and fourth frames. There are regions 300-3 and 300-4. The first to fourth frame storage areas 300-1, 300-2, 300-3, and 300-4 have capacities for storing pixel data of one frame, respectively, and the first to fourth frame storage areas 300-1, 300-. 2,300-3,300-4 each have 1,024 row addresses, and have a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the number of RAS boxes. The column address of 256 words is derived by (8 macroblocks per one RAS box * 32 pixels per 256 macroblocks = 256 pixels).

The actual physical row address of the frame memory 300 is 000 _H to 3FF _H , 400 _H to 7FF _H for the first to fourth frame storage areas 300-1 to 300-4, respectively. , 800 _H to BFF _H and C00 _H to FFF _H. However, the first to fourth frame storage areas 300-1 to 300-4 exist independently, and the second and the second blocks corresponding to the macroblocks located at predetermined row addresses of the first frame storage area 300-1 are respectively provided. The macroblocks of the third frame storage areas 300-2 and 300-3 have the same row address. As such, the row addresses in the first to third frame storage areas 300-1 to 300-3 are referred to as virtual row addresses.

Here, the first and second frame storage areas 300-1 and 300-2 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and simultaneously for display. The three-frame storage area 300-3 is used to store motion compensated B picture image data, and the fourth frame storage area 300-4 stores a coded bitstream input to the image decoder in units of predetermined bits. Used to save.

FIG. 2 illustrates an example of a method for setting a RAS box for one frame in the frame memory 300 shown in FIG. 1. For example, when one frame includes 1,920 pixels * 1,088 pixels, 30 RAS boxes * It is divided into 34 RAS boxes, a total of 1,020 Row Address Strobe (RAS) boxes. That is, the number of the RAS box becomes the row address RA of the frame memory 300. Here, one RAS box is composed of four macroblocks * 2 macroblocks and a total of eight macroblocks MB0 to MB7. Meanwhile, one RAS box may have a structure of eight macroblocks * 1 macroblock. Each macroblock is divided into four blocks b0 to b3 when the luminance Y block is taken as an example.

FIG. 3 illustrates an example of a macroblock structure in the RAS box shown in FIG. 2 and includes four luminance (Y) blocks, one color difference (Cr) block, and one color difference (Cb) block. Luminance (Y) blocks are composed of eight boxes (b0-0 to b0-7, b1-0 to b1-7, b2-0 to b2-7, and b3-0 to b3-7), respectively. The color difference blocks Cr and Cb each consist of eight sub boxes sb0-0 to sb0-7, sb1-0 to sb1-7, sb2-0 to sb2-7, and sb3-0 to sb3-7. Then, 8 pixel data in 8 * 1 format is included in each box constituting the Y block, 2 pixel data in 2 * 1 format is formed in each subbox constituting the Cr block, and 2 * is in each subbox constituting the Cb block. There are two pixel data in one format.

FIG. 4 illustrates an example of a position of a predicted macroblock, wherein a macroblock MBp predicted by a start address and a motion vector of a current macroblock to be motion compensated has four macroblocks, that is, a macroblock MB7. ), The macroblock MB8, the macroblock MB127 and the macroblock MB128 are shown. In other words, the predicted macroblock (MBp) is located across four RAS boxes, RAS box 0, RAS box 1, RAS box 30 and RAS box 31.

5A and 5B are block diagrams illustrating a configuration of an output data rearrangement apparatus of a frame memory according to the present invention. The memory control unit 200, the frame memory 300, the data storage unit 310, and the data sorting unit ( 350 and the common bus 500. In addition, the data storage unit 310 includes first to third block data storage units 31a, 31b, and 31c including eight box groups 33a to 33h having a pipeline shape. Here, the first block data storage 31a has the same configuration for each box group. For example, the box group 33b includes a latch L11 and eight flip-flops F11 to F18. The second block data store 31b has the same configuration for each box group. For example, the box group 33b includes a latch L21 and eight flip-flops F21 to F28. The third block data storage 31c has the same configuration for each box group. For example, the box group 33b includes a latch L31 and eight flip-flops F31 to F38. The data sorting unit 350 may include first to seventh shifters 35a to 35g. Here, the first to seventh shifters 35a to 35g have the same configuration in a pipeline form as shown in FIG. 5B. For example, in the case of the first shifter 35a, one latch L41 and 23 It consists of multiplexers M1-M23, one counter C1, and 24 flip-flops F41-F64.

Then, the operation and effects of the present invention will be described in detail with reference to FIGS. 1 to 5a and 5b. Here, for convenience of description, when a picture to be referred to as a frame picture and a motion type is frame estimation and compensation, a luminance signal is taken as an example.

In order to consider the worst case that may occur, the starting address of the current macroblock to be motion compensated, that is, the slice position and the macroblock position (mb-position), and the vertical and horizontal motion vectors The case in which the macroblock MBp predicted from is located as shown in FIG. 4 will be described.

In FIG. 4, pixel data corresponding to the predicted macroblock MBp is read in box units, that is, in units of 8 pixels. Therefore, when the predicted macroblock MBp is read in units of two blocks, eight boxes are first selected from the box b3-1 of the block b3 of the macroblock MB7 where the reference point RP is located. 8 boxes are read from box b2-1 of block b2 of the next macroblock MB8, and finally from box b3-1 of block b3 of the macroblock MB8. From the eight boxes are read and sequentially placed on the common bus 500. When pixel data is read in a box as described above, eight boxes must be read over a total of three blocks except that the reference point RP is placed at the start of each macroblock. A total of 24 pixel data are read. The present invention is to extract the pixel data corresponding to the predicted macroblock (MBp) from the pixel data read out in a box unit over a maximum of three blocks in the storage area of the frame memory 300 as described above.

In FIG. 5A, the memory controller 200 inputs a start address, a motion vector, and various parameters of a current macroblock to be motion compensated, and writes / reads an address and various control signals (for example, wr1 to wr3). Is supplied to the frame memory 300 and to the data storage 310 at the same time. The first to third read control signals wr1 to wr3 include a RAS box number where each block Pb0 to Pb3 of the predicted macroblock MBp is located, a block position in the RAS box, and a box position in the block. And the reference point RP determined from the pixel position in the box. Taking the predicted macroblock MBp shown in FIG. 4 as an example, the first read control signal wr1 is the box b3-1 of the block b3 of the macroblock MB7 in which the reference point RP is located. The second read control signal wr2 is a signal for reading eight boxes from the box b2-1 of the block b2 of the macroblock MB8, and the third read signal wr2 is a signal for reading eight boxes from. The read control signal wr3 is a signal for reading eight boxes from the box b3-1 of the block b3 of the macroblock MB8. In the present invention, it is assumed that the predicted macroblock MBp is input to the motion compensator (not shown) in units of two blocks from the frame memory 300.

The data storage unit 310 is for storing pixel data in a box unit loaded on the common bus 500 sequentially over a maximum of three blocks from the corresponding storage area of the frame memory 300.

In each of the box groups 33a to 33h of the first block data storage 31a, 8 from the box b3-1 of the block b3 of the macroblock MB7 in accordance with the first read control signal wr1. Pixel data of four boxes are sequentially stored in eight flip-flops F11 to F18. Next, in each box group 33a to 33h of the second block data storage 31b, in the box b2-1 of the block b2 of the macroblock MB8 in accordance with the second read control signal wr2. To sequentially store the pixel data of eight boxes in eight flip-flops F21 to F28, respectively. Next, in each box group 33a to 33h of the third block data store 31c, in the box b3-1 of the block b3 of the macroblock MB8 in accordance with the third read control signal wr3. 8 pixel pixel data are sequentially stored in eight flip-flops F31 to F38.

In FIG. 5B, the data sorting unit 350 includes pixel data (that is, up to three blocks supplied from the data storage unit 310) for two blocks Pb0 and Pb1 of the predicted macroblock MBp. The pixel data (ie, 16 pixel data) for two blocks Pb0 and Pb1 of the macroblock MBp predicted from the 24 pixel data is extracted for each box group. To this end, the pixel address P.A for the reference point R.P of the predicted macroblock MBp is used.

In the first shifter 35a, the latch L41 latches 24 pixel data supplied from the data storage 310. The counter C1 supplies the selection control signal to the multiplexers M1 to M23 according to the pixel address P.A for the reference point R.P of the predicted macroblock MBp. The multiplexers M1 to M23 shift the pixel data left by one pixel in accordance with the selection control signal and output it. The flip-flops F41 to F63 temporarily store pixel data output from the multiplexers M1 to M23, and then supply them to the latch L42 of the second shifter 35b, and the flip-flop F64 is a latch ( The 24th pixel data is temporarily stored from L41 and then supplied to the latch L42 of the second shifter 35b. Here, the counter C1 operates as a down counter, and decreases the pixel address P.A by 1 to supply it to the counter C2.

In the second shifter 35b, the latch L42 latches 24 pixel data supplied from the first shifter 35a. The counter C2 supplies the selection control signal to the multiplexers M1 to M23 according to the pixel address by one. The multiplexers M1 to M23 shift the pixel data left by one pixel in accordance with the selection control signal and output it. The flip-flops F41 to F63 temporarily store pixel data output from the multiplexers M1 to M23, and then supply them to a latch (not shown) of a third shifter (not shown). The 24 th pixel data is temporarily stored from the latch L42 and then supplied to the latch of the third shifter (not shown). Here, the counter C2 operates as a down counter, and decreases the pixel address by one by one and supplies it to the counter (not shown) of the third shifter (not shown).

In the seventh shifter 35g, the latch L47 latches 24 pixel data supplied from the sixth shifter (not shown). The counter C7 supplies the selection control signal to the multiplexers M1 to M23 according to the pixel address reduced by one at the counter (not shown) of the sixth shifter (not shown). The multiplexers M1 to M23 shift the pixel data left by one pixel in accordance with the selection control signal and output it. The flip-flops F41 to F63 temporarily store pixel data output from the multiplexers M1 to M23, and then output them to a motion compensator (not shown), and the flip-flop F64 is a sixth shifter (not shown). The 24th pixel data is temporarily stored from the latch (not shown) of the output and then output to the motion compensator (not shown).

In the first to seventh shifters 35a to 35g, the multiplexers M1 to M23 each have a first input signal on the left or a second input on the right with respect to two adjacent pixel data according to a selection control signal. Output the signal selectively. That is, when there is an address value input to the counters C1 to C7, the multiplexers M1 to M23 respectively output the second input signals by the selection control signal, so that the shifters are shifted to the left. When there is no address value input to the counters C1 to C7, the multiplexers M1 to M23 output the first input signals by the selection control signal, thereby preventing shifting. A maximum of seven shifting operations are performed according to the pixel address PA. For example, when the pixel address of the reference point RP is 011 ₂ in FIG. 4, the first to third shifters 35a to 35c may be used. Three shifting operations are performed, and the fourth to seventh shifters 35d to 35g are output as they are without shifting.

That is, the data sorting unit 350 extracts 16 effective pixel data by shifting 24 pixel data left by one pixel a predetermined number of times according to the pixel address P.A.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications according to the structure of the RAS box, the structure of the macroblock block, the picture type, and the motion compensation form within the spirit of the present invention with reference to the above description and drawings.

As described above, when the macroblock predicted by the motion vector and the start address of the current macroblock to be motion compensated is read out from the corresponding storage area of the frame memory, according to the pixel address of the predicted macroblock. By reading in units of boxes over a maximum of three blocks and shifting left by up to seven times, the data can be rearranged into pixel data corresponding to the predicted macroblock.

Claims (6)

In the frame memory 300 for storing the pixel data for reference in the motion compensation unit in the motion compensation, A data storage unit 310 sequentially reading and storing pixel data of a macroblock predicted from a start address and a motion vector of a current macroblock to be motion compensated, in box units, up to three blocks from the frame memory; And By shifting the pixel data output from the data storage unit in a box order over a maximum of three blocks by a predetermined number of times according to the pixel address of the reference point of the predicted macroblock, effective pixel data corresponding to the predicted macroblock is obtained. Output data rearrangement apparatus of the frame memory, characterized in that it comprises a data sorting unit 350 for extracting. The method of claim 1, wherein one frame picture stored in the frame memory 300 comprises a plurality of RAS boxes, the RAS box is composed of eight macroblocks, and the macroblocks are four blocks for luminance blocks. Wherein the block has a 1 box * 8 box format, and the box has an 8 pixel * 1 pixel format. The data storage unit 310 is composed of eight box groups each having a pipeline form, and each box group is composed of eight flip flops operating according to first to third read control signals. Output data rearrangement apparatus of the frame memory, characterized in that the first to third block data storage (31a ~ 31c). The first and seventh shifters 35a of claim 1, wherein each of the data sorting units 350 is configured in a pipeline form and shifts pixel data output from the data storage unit 310 by one pixel. And 35g). The method of claim 4, wherein the first to seventh shifting machine (35a ~ 35g) are each A latch for latching 24 pixel data output from the data storage unit in pixel units; A counter outputting a selection control signal according to whether the pixel address is input and down counting the pixel address by one; And And a plurality of multiplexers for inputting two adjacent pixel data of the pixel data output from the latch, respectively, and outputting one of the two pixel data according to the selection control signal. Data rearrangement device. The apparatus of claim 1, wherein the data sorting unit performs shifting up to seven times according to the pixel address.