KR19980077799A - Plasma display device for computer monitor and its driving method - Google Patents

Abstract

According to the present invention, if the screen mode of the plasma display panel (hereinafter referred to as PDP) is VGA 3 mode (Video Graphic Array 3 mode), the image data input from the outside is displayed on all screens of the PDP, and the VGA 2 mode is used. (Text Mode) relates to a plasma display device for a computer monitor which displays externally input image data in a screen center of the PDP, and a driving method thereof, comprising a VGA 2 mode image data processing function and an image in VGA 2 mode. When data is input, the image is displayed in the center of the screen of the PDP, so that the display screen is stabilized than in the prior art, and an erase pulse is supplied to the margin part of the PDP screen generated during image data processing in VGA 2 mode so that discharge does not occur. The brightness and contrast of the entire screen are improved.

Description

Plasma display device for computer monitor and its driving method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device and a method of driving the same, and in particular, it is possible to process both image data of a VGA 2 mode (Video Graphic Adapter 2 mode) and a VGA 3 mode (Graphic mode) to be used as a computer monitor. The present invention relates to a plasma display device for a computer monitor and a driving method thereof.

As the modern society is called an information society, the importance of the image display device is increasing with the development and spread of the information processing system, and the types thereof are gradually diversifying.

CRT (Cathode Ray Tube), which has been used most often as an image display device, has various problems such as large size, high operating voltage, and distortion of display. Recently, research and development of various flat display devices having a matrix structure have been actively conducted.

A plasma display device is a device that includes a PDP, which is a light emitting device, and displays a moving image or a still image by using a gas discharge phenomenon inside the PDP.

One configuration of the plasma display device according to the related art will be described with reference to FIG. 1.

In FIG. 1, reference numeral 110 denotes 640 R (Red), G (Green), B (Blue) address electrode lines R1, G1, B1, ..., R640, G640, B640, hereinafter referred to as vertical electrode lines. A three-electrode surface discharge PDP having two first and second sustain electrode line pairs (S1, S2, ..., S479, S480, hereinafter referred to as horizontal electrode lines) is shown.

The three-electrode surface discharge PDP 110 is one of the most commonly used PDPs. Although not shown in the drawing, 480 horizontal electrode lines S1 to S480 are arranged on the front substrate, and the predetermined distance from the front substrate. 640 R, G, and B vertical electrode lines R1 to B640 are arranged orthogonal to each horizontal electrode line S1 to S480 on the back substrate disposed in parallel with each other so that the entire screen is 640 × 480 in a matrix form. It consists of several pixels (pixel, R, G, B cells).

In FIG. 1, reference numeral 120 digitizes R, G, and B image data input from the outside to output 8-bit R, G, and B digital image data (implementing 256 gray scales), and outputs the digital image data and the external signal. Accordingly, a microcomputer for outputting various control signals required for driving the three-electrode surface discharge PDP 110 is shown.

In FIG. 1, reference numeral 130 denotes a scan pulse to 480 horizontal electrode lines S1 to S480 according to the control signal of the microcomputer 120, and sequentially scans one line at a time, and then all horizontal electrode lines S1. A scanning and sustain driving unit for supplying a sustain pulse to S480 to maintain discharge and light emission of each cell.

The scanning and sustain driver 130 generates a clock signal CLK and a data signal D _O according to a control signal of the microcomputer 120, and outputs the clock and data generator 131 and the microcomputer 120. The clock signal CLK and the data in the state where the sustain pulse generator 132 generates and outputs a sustain pulse in accordance with a control signal of the signal, and 40 lines are connected to the 480 horizontal electrode lines S1 to S480 in order. First to 12th driving ICs 133a to 133l which sequentially supply scan pulses to the 480 horizontal electrode lines S1 to S480 according to the signal D _O and the sustain pulses, and then simultaneously supply the sustain pulses. Consists of.

In FIG. 1, reference numeral 140 denotes a memory unit for storing R, G, and B digital image data output from the microcomputer 120 for each frame, color, and bit, and 150 is scanned by the scanning and sustain driver 130. An address driver for reading bit values of 640 R, G, and B digital image data corresponding to horizontal electrode lines from the memory unit 140 and supplying the bit values of 640 R, G, B vertical electrode lines R1 to B640. Indicates.

A process of displaying an image of 256 gray scales on a PDP screen according to a subfield method by a plasma display device according to the related art configured as described above is as follows.

The subfield method is a method of dividing and displaying one frame screen into X subfield screens to implement 2 ^X grayscale, and digitizing externally input image data into X bit digital image data and supplying the PDP.

Each subfield screen is composed of a reset period, an address period, and a sustain period. Among them, the reset period and the address period are all identically assigned to each subfield, but the sustain period is the bit weight of the digital image data displayed in the address period. Are differently assigned according to each other, and gray scale implementation of the image is possible by combining each subfield (using the integration effect of the eyes).

Therefore, the microcomputer 120 digitizes R, G, and B image data externally inputted to implement 256 gray scales, and performs 8-bit R, G, and B digital image data (lowest bit value B1 to most significant bit value B8). And various control signals required for driving the PDP 110 according to the digital image data and the external signal.

At this time, the 8-bit R, G, B digital image data output from the microcomputer 120 is stored in the memory unit 140 for each frame, color, and bit.

Thereafter, in the reset period and the address period of the first to eighth subfield screens SF1 to SF8, the first to twelfth driving ICs 133a to 133l are moved to the previous horizontal electrode lines S1 to S480 in one step. Erase pulses to remove the wall charges generated in the first stage, write pulses for forming even wall charges on the three-electrode surface discharge PDP 110 in two stages, and erase pulses in three stages to supply 640 R , the G, B perpendicular to the electrode lines (R1~B640) above, and so the address pulse voltage to be supplied to the subsequent low to form the wall charges, a clock signal (CLK) and a data signal (D _O) in step 4 and a sustain pulse Accordingly, scan pulses are sequentially supplied to the 480 horizontal electrode lines S1 to S480 one by one.

Referring to the scan signal supplied to the course of the fourth step in more detail, first, the first driving IC (133a) is a data signal (D _O) is input data signal (D _O) and a scan pulse generated by the sustain pulse Synchronized with the clock signal CLK and sequentially supplied to the 40 horizontal electrode lines S1 to S40, and the second driving IC 133b is also a clock signal when the last output of the first driving IC 133a is input. Scan pulses are sequentially supplied to the 40 horizontal electrode lines S41 to S80 in synchronization with CLK, and the corresponding 40 horizontal electrode lines S441 to S480 of the twelfth driving IC 133l in such a manner. When the scan pulses are sequentially supplied up to, scanning of the 480 horizontal electrode lines S1 to S480 is completed.

In addition, when supplying the scan pulses in the four steps, the address driver 150 transmits address pulses (1 bit value of R, G, B digital image data) corresponding to the horizontal electrode lines to which scan pulses are supplied and scanned. Synchronization is supplied to 640 R, G, and B vertical electrode lines R1 to B640, respectively, so that discharge occurs within the discharge space of each cell supplied with logic high by the address pulse.

At this time, the address driver 150 converts the 8-bit R, G, and B digital image data B1 to B8 corresponding to each cell from B _{1 to} SF ₁ , B _{2 to} SF ₂ ,. It is supplied to B7 → SF7 and B8 → SF8 respectively.

On the other hand, when the address period of each of the subfield screens SF1 to SF8 is completed, the first to twelfth driving ICs 133a to 133l receive the sustain pulse from the sustain pulse generator 132 and then use the entire horizontal electrode lines S1 to S480. ) SF1: SF2:… SF7: SF8 = 2 ⁰ : 2 ¹ :... A number of sustain pulses proportional to 2 ⁶ : 2 ⁷ (luminance relative ratio) is supplied so that the discharge and light emission of some cells in which the discharge occurs in the address period are maintained for the period (sustain period) during which the sustain pulse is supplied.

When the configuration of the first to eighth subfield screens SF1 to SF8 is completed through the above process, an image of 256 gray scales is displayed on the entire screen of the three-electrode surface discharge PDP 110 as shown in FIG. Black portion) is displayed.

On the other hand, when using the conventional plasma display device constructed and operated as a monitor of a computer, when the image data of the VGA 3 mode having a pixel ratio of 640 × 480 is output from the computer, the image data of the VGA 3 mode is displayed. Can be normally displayed on the entire screen of the three-electrode surface discharge PDP 110 having a size of 640 × 480, but when the image data of VGA 2 mode having a pixel ratio of 640 × 400 is output from the computer, the image corresponds to 80 horizontal electrode lines. As shown in FIG. 3 due to lack of data, an image of a VGA 2 mode (black portion on the drawing) is displayed at the upper part of the screen of the three-electrode surface discharge PDP 110, and a margin corresponding to 80 horizontal electrode lines is provided at the lower part thereof. White part on the drawing).

In general, a computer initially boots in VGA 2 mode and is mainly operated in VGA 2 mode. When a plasma display device used as a monitor inputs image data in VGA 2 mode, a three-electrode surface discharge PDP is shown in FIG. 3. If the image is displayed in an upper portion of the screen of 110, the screen is visually unnatural, causing inconvenience to the user.

That is, the plasma display device according to the prior art cannot properly process the image data of the VGA 2 mode, which is not suitable as a monitor of a computer mainly performing work in the VGA 2 mode.

In addition, since all horizontal electrode lines included in the PDP are sequentially scanned regardless of the mode of image data input from the outside, discharge occurs in the margin part of the screen during image data processing in the VGA 2 mode, thereby increasing the brightness of the entire screen. And there was a problem that the contrast is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and adds the image data processing function of the VGA 3 mode to the image data processing function of the VGA 3 mode, and can be used as a computer monitor. The purpose is to provide a driving method.

In addition, the present invention provides a plasma display device for a computer monitor with improved brightness and contrast of a PDP screen and a driving method thereof by preventing discharge from occurring in a margin part generated on the screen of a PDP during image data processing in the VGA 2 mode. There is a purpose.

1 is a block diagram showing one configuration of a plasma display device according to the prior art;

2 is a view showing a scanning screen of 480 horizontal electrode lines according to the prior art,

3 is a view showing a scanning screen of 400 horizontal electrode lines according to the prior art,

4 is a block diagram showing the configuration of a plasma display device for a computer monitor according to an embodiment of the present invention;

5 is a view showing a scanning screen of 400 horizontal electrode lines according to an embodiment of the present invention,

6 is a view showing a scanning screen of 480 horizontal electrode lines according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10: 3-electrode surface discharge PDP 20: microcomputer

30: mode determination unit 40: block driving unit

41: clock and data generator 42: sustain pulse generator

43a to 43l: first to twelfth driving IC 44: driving IC control section

50: memory 60: address driver

In order to achieve the above object, a method of driving a plasma display device for a computer monitor according to the present invention is that the screen mode of the plasma display panel (hereinafter referred to as PDP) is VGA 3 mode (Video Graphic Array 3 mode). The image data input from the outside is displayed on all screens of the PDP, and in the VGA 2 mode (text mode), the image data input from the outside is displayed in the center of the screen of the PDP.

According to a preferred embodiment of the present invention, when the screen mode is the VGA 2 mode, a margin process is performed by supplying an erase pulse for erasing a display image to upper and lower portions of the screen where image data is not displayed, and margin processing of the PDP screen. The erase pulse is periodically supplied for a predetermined time so that the number of minute discharges caused by the erase pulse is reduced.

In addition, the method for driving a plasma display device for a computer monitor according to the present invention is a method for driving a plasma display device in which 480 horizontal electrode lines provided in a PDP are sequentially driven into a total of 12 blocks of 40 blocks each.

If the screen mode of the PDP is VGA 3 mode, the 12 blocks are selectively scanned in a predetermined order to display externally input image data on all screens of the PDP, and if the VGA 2 mode is selected, the highest and lowest blocks of the PDP are displayed. The remaining 10 blocks are selected and scanned in a predetermined order to display image data input from the outside in the center of the screen of the PDP.

According to a preferred embodiment of the present invention, when the screen mode is the VGA 2 mode, an erase pulse for erasing a display image is supplied to the uppermost block and the lowermost block of the PDP to perform margin processing.

In addition, a plasma display device for a computer monitor according to the present invention outputs digital image data by digitizing a PDP having a plurality of vertical electrode lines and 480 horizontal electrode lines, and externally input image data, and outputting the digital image data. And a microcomputer for outputting various control signals required for driving the PDP according to an external signal, a mode determination unit for receiving a control signal of the microcomputer to determine a screen mode and outputting a mode discrimination signal, and the 480 horizontal electrode lines. Is divided into 12 blocks by 40 in order, and the 12 blocks are selected and scanned according to a predetermined order when the current screen mode is VGA 3 mode by receiving the control signal of the microcomputer and the mode discrimination signal of the mode discriminator. In the VGA 2 mode, an erase pulse for erasing a display image in the uppermost block and the lowermost block of the PDP. A block driver for selectively scanning and scanning the remaining 10 blocks according to a predetermined order, a memory unit for storing digital image data output from the microcomputer, and digital image data corresponding to a horizontal electrode line scanned by the block driver. And an address driver which reads a bit value from the memory unit and supplies it to the plurality of vertical electrode lines.

According to an embodiment of the present invention, the block driver generates and outputs a clock signal and a data signal according to the control signal of the microcomputer, and a sustain pulse generating and outputting a sustain pulse according to the control signal of the microcomputer. A first to twelfth drive for receiving the clock signal, the data signal, and the sustain signal in parallel with the pulse generator and the 12 blocks in a one-to-one correspondence, and sequentially supplying scan pulses or sustain pulses to the corresponding blocks; It is preferably composed of an IC (Integrated Circuit), and a drive IC control unit for selecting a drive IC to output a scan pulse of the first to 12 drive ICs according to the control signal of the microcomputer and the mode determination signal of the mode determination unit. .

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in more detail.

In the method of driving a plasma display device for a computer monitor according to an exemplary embodiment of the present invention, the 480 horizontal electrode lines of the PDP are sequentially driven into 12 blocks of 40 blocks each in sequence, and the screen mode of the PDP is VGA 3 mode. In this case, the 12 blocks are selected and scanned in a predetermined order to display image data input from the outside on the entire screen of the PDP. In the VGA 2 mode, the remaining 10 blocks except for the top and bottom blocks of the PDP are arranged in a predetermined order. The image data input by scanning by external selection is displayed on the screen center of the PDP.

In addition, when the screen mode is VGA 2 mode, an erase pulse for erasing a display image is supplied to the uppermost block and the lowermost block of the PDP to perform margin processing, and the number of minute discharges caused by the erase pulse is reduced during the margin processing of the PDP screen. The erase pulses are periodically supplied for a predetermined time as much as possible.

In the plasma display device for a computer monitor according to the exemplary embodiment of the present invention which performs the driving method as described above, 640 R, G, and B address electrode lines R1, G1, B1, ..., R640 are shown in FIG. A three-electrode surface discharge PDP (G640, B640, hereinafter referred to as vertical electrode line) and 480 first and second sustain electrode line pairs (S1, S2, ..., S479, S480, hereinafter referred to as horizontal electrode line) 10) and digitize the R, G, and B image data input from the outside, and output 8-bit R, G, and B digital image data (lowest bit value B1 to most significant bit value B8), and the digital image data and external The microcomputer 20 outputs various control signals required for driving the three-electrode surface discharge PDP 10 and the control signals of the microcomputer 20 to determine a screen mode and output a mode discrimination signal according to the signal. The mode determining unit 30 and the 480 horizontal electrode lines S1 to S480 are sequentially ordered. The drive is divided into a total of 12 blocks, each of 0, and receives 12 control signals of the microcomputer 20 and a mode discrimination signal of the mode determining unit 30. If the current screen mode is VGA 3 mode, 12 blocks are arranged in a predetermined order. In the VGA 2 mode, the block driving unit 40 supplies an erase pulse for erasing the display image to the uppermost block and the lowermost block, and selectively scans the remaining 10 blocks in a predetermined order. Memory unit 50 for storing 8-bit R, G, and B digital image data output for each frame, color, and bit, and R and G corresponding to horizontal electrode lines scanned by the block driver 40. And the address driver 60 for reading the bit values of the B digital image data from the memory unit 50 and supplying the bit values of the B digital image data to the 640 R, G, and B vertical electrode lines R1 to B640.

Control of the clock signal (CLK) and a data signal (D _O) clock and data generation unit 41 and the microcomputer 20 for outputting a response to the control signal from the block driving unit 40 is a microcomputer (20) signal in accordance with the output to generate the sustain pulse of sustain pulse generating unit 42 and receives in the state associated with the 12 block a one-to-one correspondence with the input of the clock signal (CLK) and a data signal (D _O) and the sustain signal in parallel First to 12th driving ICs 43a to 43l for sequentially supplying scan pulses or sustain pulses to the 40 horizontal electrode lines of the block, the control signal of the microcomputer 20 and the mode discrimination unit 30. The driver IC control section 44 selects a driver IC to output a scan pulse among the first to twelfth driver ICs 43a to 43l in accordance with the mode discrimination signal.

A plasma display device for a computer monitor according to an embodiment of the present invention configured as described above will be described below for displaying a 256 grayscale image on a PDP screen.

First, the microcomputer 20 digitizes R, G, and B image data of an externally input VGA 2 mode or VGA 3 mode to implement 256 gray scales, and outputs 8-bit R, G, B digital image data (lowest bit). Values B1 to most significant bit value B8) are output, and various control signals required for driving the three-electrode surface discharge PDP 10 are output in accordance with the digital image data and the external signal.

At this time, the 8-bit R, G, and B digital image data output from the microcomputer 20 are stored in the memory unit 50 for each frame, color, and bit.

Thereafter, the mode determining unit 30 receives the control signal of the microcomputer 20 to determine the current screen mode (counting by counting the horizontal and vertical synchronizing signals and the synchronizing polarity pulses), and outputs a mode discriminating signal. The driving IC control unit 44 subfields of some blocks according to the control signal of the microcomputer 20, the mode determination signal of the mode determination unit 30, and the output signals CLK and D _O of the clock and data generator 41. Selection signals are supplied to two to four drive ICs for addressing the screens SF1 to SF8.

The driving IC supplied with the selection signal sequentially supplies scan pulses generated by the data signal D ₀ and the sustain pulse to the corresponding 40 horizontal electrode lines in synchronization with the clock signal CLK, and the selection signal is supplied. The unsuccessful driver IC supplies a sustain pulse to the corresponding horizontal electrode line to maintain the discharge just before.

When the current screen mode is determined as the VGA 2 mode by the mode determining unit 30, the driving IC control unit 44 selects the second to eleven driving ICs 43b to 43k in a predetermined order to drive the second to eleven. Scan pulses are supplied to 40 × 10 = 400 horizontal electrode lines S41 to S440 connected to the ICs 43b to 43k, respectively, and the address driver 60 supplies the address pulses corresponding to the horizontal electrode lines to which the scan pulses are supplied. The logic high is supplied to the address pulse by reading one bit value of R, G, and B digital image data from the memory unit 50 and supplying them to the 640 R, G, and B vertical electrode lines R1 to B640, respectively. Discharge occurs within the discharge space of each cell.

At this time, the address driver 60 similarly as in the prior art that the R, G, B digital image data (B1~B8) of the 8-bit B ₁ → SF1, SF2 → B2, corresponding to each cell ... It is supplied to B7 → SF7 and B8 → SF8 respectively.

In addition, when the address period of each subfield screen SF1 to SF8 for each block is completed, the second to eleventh driving ICs 43b to 43k receive a sustain pulse from the sustain pulse generator 42 and receive SF1 in the corresponding block. : SF2:… SF7: SF8 = 1: 2: 4: 8: 16: 32: 64: 128 The number of sustain pulses proportional to the relative luminance ratio is supplied to discharge and emit light in some cells in which the discharge occurred in the address period. It is maintained for the supply period (sustain period).

On the other hand, when the second to eleventh driving ICs 43b to 43k and the address driver 60 are addressing the ten blocks, the first driving IC 43a and the twelfth driving IC 43k correspond to each other. The erase pulses are supplied to the uppermost blocks S1 to S40 and the lowermost blocks S441 to S480 to blank the upper and lower portions of the three-electrode surface discharge PDP 10 screen.

At this time, if the device is left as it is without supplying the driving pulses to the uppermost blocks S1 to S40 and the lowermost blocks S441 to S480, which are to be spaced out, the margins of the three-electrode surface discharge PDP 10 are affected. Since discharge causes the luminance of the margin to increase, resulting in a decrease in contrast of the entire screen, an erase pulse must be supplied to the uppermost blocks S1 to S40 and the lowermost blocks S441 to S480.

In addition, since the erase signal supplied for the margin processing also causes a micro discharge, the first and twelfth driving ICs 43a and 43k apply an erase pulse to the uppermost blocks S1 to S40 and the lowermost blocks S441 to S480 for a predetermined time. By supplying periodically, the number of micro discharges caused by the erase pulse is reduced, thereby minimizing the discharge effect of the margin portion.

After the above process, as shown in FIG. 5, an image (black portion in the drawing) is displayed at the center of the three-electrode surface discharge PDP 10 screen, and the upper and lower portions are blank (white portion in the drawing). On-screen unnaturalness such as technology is solved.

On the other hand, when the current screen mode is determined to be the VGA 3 mode by the mode determination unit 30, the driving IC control unit 44 selects the first to twelfth driving ICs 43a to 43l in a predetermined order to determine the first to 12th. Scan pulses are supplied to 40 × 12 = 480 horizontal electrode lines S1 to S480 respectively connected to the driving ICs 43a to 43l, and the address driver 60 corresponds to an address pulse corresponding to the horizontal electrode line to which the scan pulses are supplied. Logical high is supplied by the address pulse by reading (1 bit value of R, G, B digital image data) from the memory unit 50 and supplying them to the 640 R, G, B vertical electrode lines R1-B640, respectively. Discharge occurs within the discharge space of each cell.

At this time, the address driver 60 includes a VGA mode 2, if as with the 8-bit R, G, B digital image data (B1~B8) B ₁ → SF1, SF2 → B2, ... of It is supplied to B7 → SF7 and B8 → SF8 respectively.

In addition, when the address period of each subfield screen SF1 to SF8 for each block is completed, the first to twelfth driving ICs 43a to 43l receive a sustain pulse from the sustain pulse generator 42 and receive SF1 in the corresponding block. : SF2:… SF7: SF8 = 1: 2: 4: 8: 16: 32: 64: 128 The number of sustain pulses proportional to the relative luminance ratio is supplied to discharge and emit light in some cells in which the discharge occurred in the address period. It is maintained for the supply period (sustain period).

After the above process, as shown in FIG. 6, an image (black portion on the drawing) is displayed on the entire screen of the three-electrode surface discharge PDP 10.

As described above, the exemplary embodiment of the present invention can appropriately display both the VGA 2 mode and the VGA 3 mode image data input from an external computer.

As described above, the plasma display device for a computer monitor and the driving method thereof according to the present invention have an image data processing function of VGA 2 mode, and when the image data of VGA 2 mode is input, an image is displayed at the center of the screen of the PDP. Since the display screen is stabilized and an erase pulse is supplied to the margin portion of the PDP screen generated during the image data processing in the VGA 2 mode, the discharge is not generated, thereby improving the brightness and contrast of the entire screen.

Claims (7)

If the screen mode of the plasma display panel (hereinafter referred to as PDP) is VGA 3 mode (Video Graphic Array 3 mode: graphic mode), externally input image data is displayed on all screens of the PDP, and the VGA 2 mode (text mode) Is displayed on the center of the screen of the PDP. The plasma display for a computer monitor according to claim 1, wherein when the screen mode is the VGA 2 mode, an erase pulse for erasing the display image is supplied to the upper and lower portions of the screen where the image data is not displayed. Method of driving the device. The method of claim 2, wherein the erase pulse is periodically supplied for a predetermined time so that the number of minute discharges caused by the erase pulse is reduced during the margin processing of the PDP screen. A method of driving a plasma display device in which 480 horizontal electrode lines of a PDP are divided into 12 blocks of 40 in order, wherein the 12 blocks are selected in a predetermined order when the screen mode of the PDP is VGA 3 mode. Image data input from outside by scanning is displayed on all screens of the PDP, and in VGA 2 mode, image data input from outside is selected by selectively scanning the remaining 10 blocks except the top and bottom blocks of the PDP in a predetermined order. And displaying the center portion of the screen of the PDP. 5. The method of driving a plasma display device for a computer monitor according to claim 4, wherein when the screen mode is VGA 2 mode, an erase pulse for erasing a display image is supplied to the uppermost block and the lowermost block of the PDP. . PDP having a plurality of vertical electrode lines and 480 horizontal electrode lines, and digitally outputting digital image data by digitizing externally input image data, and controlling various kinds of controls required for driving the PDP according to the digital image data and external signals. A microcomputer for outputting a signal, a mode determination unit for receiving a control signal of the microcomputer to determine a screen mode, and outputting a mode discrimination signal; and driving the 480 horizontal electrode lines into 12 blocks in total of 40 in order. Receiving the control signal of the microcomputer and the mode determination signal of the mode determination unit, and selecting and scanning the 12 blocks in a predetermined order if the current screen mode is the VGA 3 mode; and, if the VGA 2 mode is the most significant block and the lowest block of the PDP, The block is supplied with an erase pulse for erasing the display image, and the remaining 10 blocks are selected in a predetermined order. A plurality of vertical electrodes by reading a bit value of digital image data corresponding to a horizontal electrode line scanned by the block driver, a memory unit for storing digital image data output from the microcomputer, and a plurality of vertical electrodes A plasma display device for a computer monitor comprising an address driver for supplying a line. 7. The apparatus of claim 6, wherein the block driver generates and outputs a clock signal and a data signal according to the control signal of the microcomputer, and a sustain pulse that generates and outputs a sustain pulse according to the control signal of the microcomputer. First to 12th driving ICs which receive the clock signal, the data signal, and the sustain signal in parallel with the generator and the 12 blocks in a one-to-one correspondence, and sequentially supply scan pulses or sustain pulses to the corresponding blocks. (Integrated Circuit) and a drive IC control unit for selecting a drive IC that should output a scan pulse of the first to 12 drive ICs in accordance with the control signal of the microcomputer and the mode determination signal of the mode determination unit Plasma display for monitors.