KR19980066735A - Plug formation method of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a plug of a semiconductor device. One embodiment includes forming an interlayer insulating layer using an insulating material on the conductive layer; Etching a portion of the interlayer insulating layer over the conductive layer to form a damascene line; Etching the interlayer insulating layer between the damascene line and the conductive layer to form a contact hole; Forming a spacer on the damascene line and a sidewall of the contact hole; Selectively depositing tungsten (W) on the resultant formed of the steps to form a tungsten layer; And chemical mechanical polishing (CMP) the tungsten layer. Another embodiment includes forming an interlayer insulating layer using an insulating material on the conductive layer; Etching a portion of the interlayer insulating layer over the conductive layer to form a damascene line; Etching the interlayer insulating layer between the damascene line and the conductive layer to form a contact hole; Depositing a material capable of selectively depositing tungsten (W) on the resultant formed of the steps to form a material layer; Selectively depositing tungsten (W) on the material layer to form a tungsten layer; And chemical mechanical polishing (CMP) the tungsten layer until the interlayer insulating layer is exposed. As a result, tungsten deposition time can be reduced, and voids can be prevented from occurring due to poor step applicability.

Description

Plug formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a plug of a semiconductor device using a damascene method and a selective deposition method of tungsten (W).

As the degree of integration of semiconductor devices increases for high speed, high functionality, and miniaturization of electronic devices, the cell area is reduced, and consequently, the size of the contact hole decreases, so that the contact resistance increases. As the semiconductor device is highly integrated, an aspect ratio is increased, and accordingly, there is a demand for a technology for embedding and wiring high-level contact holes. Methods for embedding high-level contact holes include a selective tungsten (Selective-W) process, a blanket tungsten (Blanket-W) process, a laser reflow process, a high temperature deposition process, and an aluminum reflow process. Al-Reflow) process is generally used.

Among them, the blanket tungsten process is a method of filling a contact hole by forming a contact hole in an interlayer insulating film, depositing tungsten more than a predetermined thickness, and then performing a chemical mechanical polishing (CMP) process to form a tungsten plug in the contact hole to fill the contact hole. to be.

In the blanket tungsten process, the contact hole is completely filled in the state in which the contact hole is formed, and CMP is performed after depositing tungsten more than a predetermined thickness from the surface of the interlayer insulating film. As a result, a large amount of tungsten is removed. It is very uneconomical. In addition, when the size of the contact hole is not constant, the amount of tungsten is further increased because tungsten is to be deposited in consideration of the large size.

In order to alleviate these drawbacks, selective tungsten (Tungsten), which selectively deposits tungsten on the film, such as silicon (Si), aluminum (Al), titanium nitride (TiN), titanium (Ti), titanium silicide (TiSi), etc. Selective-W) process has been proposed and used. However, in the selective tungsten process, tungsten should not be deposited on the interlayer insulating film. If such selective deposition is not performed properly, tungsten may be deposited in unwanted portions. In order to solve this problem, changing the deposition conditions of tungsten causes a problem of generating a junction leakage current. In addition, there is a problem that voids are caused in the contact hole due to poor coating property of the deposited tungsten.

On the other hand, as the wiring structure of the semiconductor device is multilayered, the aspect ratio of the contact hole increases, resulting in problems such as unevenness, poor step coatability, metal short circuit, low yield, and deterioration of reliability. Accordingly, in recent years, as a new wiring technique for solving these problems, a damascene technique, which is easy in subsequent planarization processes, and which is advantageous in economics, has been used. According to the damascene process, a flat insulating film is etched to form a via pattern, and the resultant is buried in metal, and the excess metal layer on the insulating film is removed by the CMP method.

As a material for the damascene process, aluminum (Al) and tungsten (W) by chemical vapor deposition (CVD) are mainly used. Among them, in the case of CVD tungsten, a phenomenon in which a titanium nitride (TiN) film used as an adhesive layer is lifted by tungsten fluoride (WF ₆ ) gas occurs, and a crack, which is typical of CVD tungsten deposition, occurs. ), During the planarization process using Chemical Mechanical Polishing (CMP), a certain defect occurs in the middle of the metal line.

Accordingly, an object of the present invention is to provide a method for forming a plug of a semiconductor device for solving the above problems.

1A to 1E are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to an embodiment of the present invention.

2A to 2E are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to another exemplary embodiment of the present invention.

In order to achieve the above object, a method of forming a plug of a semiconductor device according to an embodiment of the present invention includes forming an interlayer insulating layer using an insulating material on a conductive layer; Etching a portion of the interlayer insulating layer over the conductive layer to form a damascene line; Etching the interlayer insulating layer between the damascene line and the conductive layer to form a contact hole; Forming a spacer on the damascene line and a sidewall of the contact hole; Selectively depositing tungsten (W) on the resultant formed of the steps to form a tungsten layer; And chemical mechanical polishing (CMP) of the tungsten layer provides a method for forming a plug (plug) of a semiconductor device characterized in that it comprises a.

Selective deposition of the tungsten is preferably carried out one or more times.

The tungsten layer is preferably formed by reacting silane (SiH ₄ ): WF ₆ in a ratio of 1: 2 at a temperature of 250 ° C. and a pressure atmosphere of several hundred Torr.

In addition, the spacer is preferably formed using a material capable of selectively depositing tungsten (W).

According to another aspect of the present invention, there is provided a plug forming method of a semiconductor device, the method including: forming an interlayer insulating layer using an insulating material on a conductive layer; Etching a portion of the interlayer insulating layer over the conductive layer to form a damascene line; Etching the interlayer insulating layer between the damascene line and the conductive layer to form a contact hole; Depositing a material capable of selectively depositing tungsten (W) on the resultant formed of the steps to form a material layer; Selectively depositing tungsten (W) on the material layer to form a tungsten layer; And chemical mechanical polishing (CMP) the tungsten layer until the interlayer insulating layer is exposed.

Selective deposition of the tungsten is preferably carried out one or more times.

In addition, the tungsten layer is preferably formed by reacting silane (SiH ₄ ): WF ₆ in a ratio of 1: 2 at a temperature of 250 ° C. and a pressure atmosphere of several hundred Torr.

The method for forming a plug of a semiconductor device according to the present invention has the advantage that the tungsten deposition time is reduced, and that voids can be prevented from occurring due to poor step coatability.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to an embodiment of the present invention.

In the drawings, reference numeral 1 is a conductive layer, 3 is an interlayer insulating layer, 4 is a damascene line, 5 is a contact hole, 7 is a spacer, 9 is a first tungsten layer, 11 is a second tungsten layer, 12 represents a loss and 13 represents a plug.

Referring to FIG. 1A, first, an interlayer insulating layer 3 is formed using an insulating material on a conductive layer 1, and a portion of the interlayer insulating layer 3 is etched on the conductive layer 1. To form a damascene line 4, and then to form a contact hole 5 by etching the interlayer insulating layer between the damascene line 4 and the conductive layer 1. .

The conductive layer 1 may be a semiconductor substrate or a material layer formed using a conductive material such as aluminum (Al) or titanium silicide (TiSi).

Referring to FIG. 1B, spacers 7 are formed on sidewalls of the damascene line 4 and the contact hole 5.

The spacer 7 is for selectively depositing tungsten (W) in the damascene line 4 and the contact hole 5 in a subsequent process, the titanium silicide (TiSi) or the entire surface of the conductive layer (1) or Polycrystalline silicon is deposited and then etched to form it.

Referring to FIG. 1C, the first tungsten layer 9 is formed by selectively depositing tungsten (W) on the conductive layer 1 on which the spacer 7 is formed.

The deposition process uses a silane (SiH ₄ ) reduction reaction, and reacts silane (SiH ₄ ): WF ₆ in a ratio of 1: 2 at a temperature of 250 ° C. and a pressure of several hundred torr. The deposition is performed so as to slightly over or under the center of the contact hole 5.

As a result, the first tungsten layer 9 is deposited only on the conductive layer 1 and the spacer 7 and not on the interlayer insulating layer 3.

Referring to FIG. 1D, the second tungsten layer 11 is formed on the first tungsten layer 9 by continuously performing the tungsten deposition process so that the damascene line 4 and the contact hole 5 are completely filled. Form.

In this case, tungsten is also deposited on the portions except the damascene line 4 and the contact hole 5, that is, the upper part of the interlayer insulating layer 3, thereby showing selective loss 12. Can be removed.

Referring to FIG. 1E, a plug 13 filling the damascene line 4 and the contact hole 5 by chemical mechanical polishing (CMP) of the second tungsten layer 11 and the first tungsten layer 9 is performed. ).

2A to 2E are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to another exemplary embodiment of the present invention.

Reference numeral 21 is a conductive layer, 23 is an interlayer insulating layer, 24 is a damascene line, 25 is a contact hole, 2727a is a material layer, 29 is a first tungsten layer, 31 is a second tungsten Layer represents 33, and plug represents respectively.

Referring to FIG. 2A, first, an interlayer insulating layer 23 is formed by using an insulating material on the conductive layer 21, and some thicknesses of the interlayer insulating layer 23 are etched on the conductive layer 21. To form a damascene line 24, and then to form a contact hole 25 by etching the interlayer insulating layer between the damascene line 24 and the conductive layer 21. .

The conductive layer 21 may be formed using a semiconductor substrate or a conductive material such as aluminum (Al) or titanium silicide (TiSi).

Referring to FIG. 2B, a material layer 27 is formed by depositing any one of titanium silicide (TiSi) and polycrystalline silicon according to the resultant structure formed by the above processes.

The material layer 27 may be formed of a material capable of selectively depositing tungsten (W) in a subsequent process other than the material.

Referring to FIG. 2C, a first tungsten layer 29 is formed by selectively depositing tungsten (W) on the material layer 27.

The deposition process uses a silane (SiH ₄ ) reduction reaction, and reacts silane (SiH ₄ ): WF ₆ in a ratio of 1: 2 at a temperature of 250 ° C. and a pressure of several hundred torr. The deposition is performed so as to slightly over or under the center of the contact hole 25.

Referring to FIG. 2D, a second tungsten layer 31 is formed on the first tungsten layer 29 by continuously performing a tungsten deposition process.

Referring to FIG. 2E, the second material layer 11 and the first material layer 9 are chemically mechanically polished (CMP) until the interlayer insulating layer 23 is exposed, thereby making contact with the damascene line 24. A plug 33 filling the hole 25 is formed.

The plug forming method of the semiconductor device according to the present invention described above has the advantage that the tungsten deposition time is reduced, and that voids can be prevented from occurring in the plug due to the step difference coating property.

Claims (7)

Forming an interlayer insulating layer using an insulating material on the conductive layer; Etching a portion of the interlayer insulating layer over the conductive layer to form a damascene line; Etching the interlayer insulating layer between the damascene line and the conductive layer to form a contact hole; Forming a spacer on the damascene line and a sidewall of the contact hole; Selectively depositing tungsten (W) on the resultant formed of the steps to form a tungsten layer; And And chemical mechanical polishing (CMP) the tungsten layer. The method of claim 1, wherein the step of selectively depositing tungsten The plug formation method of a semiconductor element characterized by advancing one or more times. The method of claim 1, wherein the tungsten layer A method of forming a plug of a semiconductor device, characterized by reacting silane (SiH ₄ ): WF ₆ in a ratio of 1: 2 at a temperature of 250 ° C. and a pressure of several hundred Torr. The method of claim 1, wherein the spacer A method for forming a plug of a semiconductor device, characterized in that the tungsten (W) is formed using a material that can be selectively deposited. Forming an interlayer insulating layer using an insulating material on the conductive layer; Etching a portion of the interlayer insulating layer over the conductive layer to form a damascene line; Etching the interlayer insulating layer between the damascene line and the conductive layer to form a contact hole; Depositing a material capable of selectively depositing tungsten (W) on the resultant formed of the steps to form a material layer; Selectively depositing tungsten (W) on the material layer to form a tungsten layer; And And chemical mechanical polishing (CMP) the tungsten layer until the interlayer insulating layer is exposed. The method of claim 5, wherein the step of selectively depositing tungsten The plug formation method of a semiconductor element characterized by advancing one or more times. The method of claim 5, wherein the tungsten layer A method of forming a plug of a semiconductor device, characterized by reacting silane (SiH ₄ ): WF ₆ in a ratio of 1: 2 at a temperature of 250 ° C. and a pressure of several hundred Torr.