KR19980048585A - DRAM device in S.O.I substrate and its manufacturing method - Google Patents

Abstract

The present invention discloses a DRAM device in an SOI substrate and a method of manufacturing the same. The disclosed invention comprises the steps of: forming a conductive layer on top of a silicon wafer for handling comprising a buried insulating film; Forming a first planarization layer formed on the conductive layer; Etching the first planarization layer to expose the conductive layer to form a storage node contact hole; Forming a capacitor in contact with the conductive layer in the storage node contact hole; Forming a contact layer on top of the capacitor; Forming a device layer over the entire structure; Forming a gate electrode on a predetermined portion of the device layer; And forming a source region and a drain region in contact with the contact layer on both device layers of the gate electrode.

Description

DRAM device in S.O.I substrate and its manufacturing method

The present invention relates to a DRAM device in an S.O.I (hereinafter referred to as SOI) substrate, and more particularly, to a DRAM device in an SOI substrate capable of reducing a step difference between a cell region and a peripheral region in a DRAM device. And to a method for producing the same.

In recent years, the widespread use of information devices such as computers has increased the demand for semiconductor memory devices. In particular, there is a great need for semiconductor memory devices having large storage capacities and operating at high speeds, which has followed the development of techniques for improving the integration density, response and reliability of semiconductor memory devices.

Among semiconductor memory devices, a DRAM is known as a memory capable of inputting arbitrary information or outputting already stored information, and a general DRAM inputs an external signal and a portion of a memory cell array in which a large amount of information as a storage area is stored. Or a peripheral circuit portion for outputting.

1, the source oxide film 2 is formed, and the source and drain regions 4A and 4B are formed on both sides of the gate electrode 3 and the gate electrode 3 on the semiconductor substrate 1, as shown in FIG. do. At this time, in order to optimize the devices, the semiconductor substrate 1 is formed with a P well 1A and an N well 1B by a known impurity doping or impurity ion implantation process, and the source and drain regions 4A and 4B are formed. It is formed in the type opposite to the impurity type of the wells 1A and 1B of the semiconductor substrate 1.

Subsequently, the first interlayer insulating film 5 is formed on the resultant, and the first interlayer insulating film 5 is partially etched to expose the drain region 4B, thereby forming a bit line contact hole (not shown). The bit line 6 is formed to contact the drain region 4B. The second interlayer insulating film 7 is formed to a predetermined thickness on the semiconductor substrate 1 on which the bit lines 6 are formed, and is etched so as to expose only the source region 4A of the cell region, thereby forming a storage node contact hole (not shown). ) Is formed. Subsequently, a storage node capacitor is formed to contact the source region 4A through the storage node contact hole.

At this time, the storage node capacitor 8 is not formed in the peripheral region, and the bit line 5 is selectively formed.

However, according to the conventional method as described above, due to the storage node capacitor, the step between the cell area and the peripheral area is severely generated. For this reason, in the metal patterning process for forming the subsequent metal wiring, due to the severe step between the cell region and the peripheral region, it is difficult to form a pattern in a desired shape.

In addition, in the etching process for forming the bit line contact hole and the storage node contact hole, over etching is involved to form a narrow diameter contact hole. This process causes a problem that the source and drain regions may be partially etched, thereby increasing the leakage current of the DRAM device.

Accordingly, in order to solve the above-mentioned problems, the present invention provides a method for a SOI substrate in which a storage node capacitor is formed inside a silicon on insulator (SOI) substrate so as to minimize a step between a cell region and a peripheral region in a DRAM device. An object of the present invention is to provide a LAN device and a method of manufacturing the same.

Another object of the present invention is to provide a DRAM device and a manufacturing method in an SOI substrate capable of reducing the junction leakage current of the source and drain regions of the DRAM device.

1 is a cross-sectional view showing a conventional semiconductor DRAM device.

Figure 2 is a cross-sectional view showing a DRAM device formed on the S. O. eye substrate according to the present invention.

3A to 3E are cross-sectional views illustrating a method for manufacturing a DRAM device on an S.O.I substrate of the present invention.

* Description of the symbols for the main parts of the drawings *

11 silicon wafer for handling 12 conductive layer

13 first planarization film 14 plate electrode

15 dielectric film 16: storage node electrode

17 contact layer 18 device layer

19 gate oxide film 20 gate electrode

21 spacer 22A source region

22B: drain region 23: second planarization film

24: metal wiring

In order to achieve the above object of the present invention, the present invention, a silicon wafer for handling, a buried insulating layer formed on the silicon wafer, a conductive layer formed on the buried insulating layer, and formed on the conductive layer A first planarization film, a device layer formed on the first planarization film, a gate electrode formed on a predetermined portion of the device layer, a source and a drain region formed on the device layers on both sides of the gate electrode, and the device layer; A second planarization film formed over the first planarization film, and a metal wiring formed in the second planarization film and the first planarization film and in contact with the conductive layer, and in the first planarization film, a source region And a storage node capacitor having a storage node electrode in contact with the substrate, and a plate electrode in contact with the dielectric layer and the conductive layer.

In addition, the method for manufacturing a DRAM device in an SOI substrate of the present invention comprises the steps of: forming a conductive layer on top of a silicon wafer for handling including a buried insulating film; Forming a first planarization layer formed on the conductive layer; Etching the first planarization layer to expose the conductive layer to form a storage node contact hole; Forming a capacitor in contact with the conductive layer in the storage node contact hole; Forming a contact layer on top of the capacitor; Forming a device layer over the entire structure; Forming a gate electrode on a predetermined portion of the device layer; Forming a source region and a drain region in contact with the contact layer on both device layers of the gate electrode.

According to the present invention, a semiconductor DRAM device is formed on an SOI substrate, a storage node capacitor of the DRAM is formed in an insulating film at the bottom of the device layer, and a portion protruding above the surface is removed, thereby eliminating the area between the cell region and the peripheral region caused by the storage node capacitor. The step difference can be reduced. In addition, since the contact hole forming process for exposing the source and drain regions is excluded, the junction leakage current due to the etching of the source and drain regions is not generated.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view showing a DRAM device formed in the SOI substrate of the present invention, and FIGS. 3A to 3E illustrate a method of manufacturing a DRAM device in the SOI substrate of the present invention.

In the present invention, in order to reduce the step difference between the cell area and the peripheral area due to the storage node capacitor of the DRAM device, and to reduce the leakage current, the device is formed on the SOI substrate with perfect device isolation and improved punch-through characteristics. To form.

In addition, the storage node capacitor of the DRAM device is formed in the insulating film at the bottom of the device layer of the SOI substrate to reduce the surface step of the substrate.

2, in the DRAM device of the present invention, a buried insulating layer 11 is formed on the silicon wafer 10 for handling, and a conductive layer 12 is formed on the buried insulating layer 11. It is. At this time, the conductive layer 12 is a polysilicon film doped with P atoms.

The first planarization film 13 is formed on the conductive layer 12, and the device layer 18 formed on the first planarization film 13 is formed. At this time, the first planarization film 13 is preferably formed of a BPSG film, and the device layer is a polysilicon film doped with a P-type impurity.

The gate electrode 20 is formed in a predetermined portion above the device layer 18, and the N type source and drain regions 22A and 22B are formed in the device layer 18 on both sides of the gate electrode.

The first planarization layer 12 includes a storage node electrode 16 in contact with the source region 22A and a plate electrode 14 in contact with the dielectric layer 15 and the conductive layer 12. Node capacitors are formed.

A second planarization film 23 is formed on the device layer 18 and the first planarization film 13, and the metal wires 24 pass through the second planarization film 23 and the first planarization film 13. It is formed to be in contact with the conductive layer 12. At this time, the metal wiring 24 is a laminated film of a barrier metal film and an aluminum metal film, or an aluminum metal film.

Hereinafter, the manufacturing method of the present invention will be described in detail.

Referring to FIG. 3A, a buried insulating layer 11 is formed on the handling silicon wafer 10 for forming an SOI substrate by a known method, and on top of the buried insulating layer 11, a conductive layer ( 12) is deposited to a predetermined thickness. At this time, the conductive layer 12 is polysilicon doped with a predetermined impurity, for example, P atoms.

3B, a first planarization film 13 such as a BPSG film is deposited on the conductive layer 12, and the first planarization film 13 is flowed at a temperature of about 700 to 800 ° C. do. Subsequently, the first planarization layer 13 is partially etched to form a storage node contact hole H.

Thereafter, a first polysilicon film doped with P atoms is deposited to a predetermined thickness on the resultant, and then, as shown in FIG. 3C, the blanket is etched so as to be embedded in the storage node contact hole H, thereby forming a plate electrode 14.

Subsequently, in order to form the dielectric film of the capacitor, an ONO insulating film (oxide-nitride-oxide) is formed, and a second polysilicon film doped with P atoms and N-type impurities such as P or As atoms doped thereon The third polysilicon film is formed in an orderly manner.

Then, after the resultant is annealed, the third polysilicon film, the second polysilicon film, and the ONO insulating film are etched to exist in the storage node contact hole, so that the contact layer 17, the storage node electrode 16, and the dielectric film are etched. (15) is formed. Here, the contact layer 17 is a third polysilicon film doped with N-type impurities such as P or As atoms, and serves to effectively contact the source region of the transistor to be formed later and the storage node electrode of the capacitor. do.

Thereafter, with reference to Fig. 3D, a device layer 18 for forming an element is formed on the planarization film 130 and the contact layer 17. The device layer 18 is polysilicon doped with P-type impurities. The film is heat-treated at a predetermined temperature after deposition, and then partially etched. Then, a gate oxide film 19 and a polysilicon film for the gate electrode are formed on the device layer 18, and then a predetermined portion is etched to form a gate electrode ( 20) is formed.

Then, after forming N-type low concentration impurities, such as P atoms, into the exposed device layer 18 to form a source and drain region, deposition of a known oxide film is formed on both sidewalls of the gate electrode 20. And the spacer 21 is formed by a blanket etching process. Thereafter, the exposed device layer 18 on both sides of the gate electrode 20 and the spacer 21 is ion implanted with an N type high concentration impurity, for example, As atoms. At this time, the source and drain region forming impurities are N-type impurities because the operation speed of the N-MOS transistor is significantly faster than that of the P-MOS transistor, so that the DRAM switching element is formed of the N-MOS transistor.

Referring to Fig. 3E, a second planarization film 23, such as a BPSG film, is formed on the substrate and flows at a predetermined temperature. In this flowing process, the ion implanted impurity atoms are diffused to form source and drain regions 22A and 22B. In this case, since the source region 22A is the same material in which the same impurities are injected into the contact layer 17, the source region 22A is effectively contacted with the storage node electrode 16 using the contact layer 17 as a buffer layer.

Then, the second planarization film 23 and the first planarization film 13 are etched to expose a predetermined portion of the lower conductive layer 12 to form holes (not shown), and then through the holes, The metal wiring 24 in contact with the conductive layer 12 is formed.

In this case, the metal wire 24 may be formed of a laminated film of the barrier metal film 25 and the aluminum metal film 26, and may be formed of only the aluminum metal film 26.

As described in detail above, according to the present invention, a semiconductor DRAM device is formed on an SOI substrate, a storage node capacitor of the DRAM is formed in an insulating film at the bottom of the device layer, and a portion protruding above the surface is removed, thereby saving the storage node capacitor. The step difference between the cell area and the surrounding area can be reduced.

In addition, since the contact hole forming process for exposing the source and drain regions is excluded, the junction leakage current due to the etching of the source and drain regions is not generated.

Thus, the quality of the DRAM device is improved.

Claims (15)

A silicon wafer for handling, A buried insulating layer formed on the silicon wafer; A conductive layer formed on the buried insulating layer; A first planarization film formed over the conductive layer, A device layer formed on the first planarization film; A gate electrode formed on a predetermined portion of the device layer; Source and drain regions formed on the device layers on both sides of the gate electrode; A second planarization film formed on the device layer and the first planarization film; A metal wiring formed in the second planarization film and the first planarization film, the metal wiring being in contact with the conductive layer, and in the first planarization film, the storage node electrode in contact with the source region, the dielectric film and the conductive layer; And a storage node capacitor having a plate electrode in contact therewith. The DRAM device of claim 1, wherein the conductive layer is a polysilicon film doped with P atoms. The DRAM device of claim 1, wherein the device layer is a polysilicon film doped with P-type impurities. The DRAM device of claim 1, wherein the source and drain regions are N-type impurity regions. The DRAM device of claim 1, wherein the storage node electrode and the plate electrode are polysilicon films doped with P atoms. The DRAM device of claim 1, wherein the first and second planarization films are flowed BPSG films. Forming a conductive layer on the handling silicon wafer including the buried insulating film; Forming a first planarization layer formed on the conductive layer; Etching the first planarization layer to expose the conductive layer to form a storage node contact hole; Forming a capacitor in contact with the conductive layer in the storage node contact hole; Forming a contact layer on top of the capacitor; Forming a device layer over the entire structure; Forming a gate electrode on a predetermined portion of the device layer; And forming a source region and a drain region in contact with the contact layer on both device layers of the gate electrode. 8. The method of claim 7, further comprising, after forming the source and drain regions, forming a second planarization layer on the entire structure; Etching the second planarization layer and the first planarization layer so that the conductive layer is partially exposed to form a hole; Forming a metal wiring to contact the conductive layer in the hole. 8. The DRAM device of claim 7, wherein the conductive layer is formed of a polysilicon film doped with P atoms. 8. The method of claim 7, wherein the forming of the capacitor comprises: depositing a first polysilicon film doped with N type impurities; Blank-etching the first polysilicon layer on the storage node contact hole to form a plate electrode of a capacitor; Depositing an insulating film and second and third polysilicon films doped with N-type impurities on the resultant material; And etching the third and second polysilicon layers and the insulating layer to exist in the storage node contact holes, thereby forming a contact layer of the capacitor, the storage node electrode, and a dielectric layer. Manufacturing method. The method of claim 10, wherein the contact layer serves to contact the source region and the storage node electrode. 11. The method of claim 10, wherein the first and second polysilicon films are polysilicon films doped with P atoms. 8. The method of claim 7, wherein the device layer is a polysilicon film doped with P-type impurities. The method of manufacturing a DRAM device in an SOI substrate according to claim 7, wherein the source and drain regions are N-type impurity regions. 9. The method of claim 7 or 8, wherein forming the first and second planarization films comprises: depositing a BPSG film; And flowing said BPSG film at a predetermined temperature.