KR19980048146A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19980048146A KR19980048146A KR1019960066696A KR19960066696A KR19980048146A KR 19980048146 A KR19980048146 A KR 19980048146A KR 1019960066696 A KR1019960066696 A KR 1019960066696A KR 19960066696 A KR19960066696 A KR 19960066696A KR 19980048146 A KR19980048146 A KR 19980048146A
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- insulating film
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- semiconductor device
- interlayer insulating
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- 239000004065 semiconductor Substances 0.000 title abstract description 24
- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 41
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000004380 ashing Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract description 8
- 210000002381 plasma Anatomy 0.000 description 15
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- IUHFWCGCSVTMPG-UHFFFAOYSA-N [C].[C] Chemical compound [C].[C] IUHFWCGCSVTMPG-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000010257 thawing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
- G03F7/427—Stripping or agents therefor using plasma means only
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자에 관한 것으로 특히, 방향성 에싱(ashing)을 통한 메탈 층간절연막의 신뢰성을 향상하기에 적당한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method for manufacturing a semiconductor device suitable for improving the reliability of a metal interlayer insulating film through directional ashing.
본 발명에 따른 반도체소자의 제조방법은 기판의 소정영역상에 배선층을 형성하는 단계, 상기 배선층을 포함한 기판전면에 제 1 절연막과 상기 제 1 절연막상에 층간절연막을 형성하는 단계, 상기 층간절연막상에 제 2 절연막과 감광막을 차례로 형성하는 단계, 상기 배선층 상층영역의 감광막을 선택적으로 패터닝하는 단계, 상기 패터닝된 감광막을 마스크로 이용한 식각공정으로 제 2 절연막, 층간절연막 그리고 제 1 절연막을 선택적으로 제거하여 비아 홀을 형성하는 단계, 상기 패터닝된 감광막 및 비아 홀 내의 레지듀를 방향성 에싱법으로 제거하는 단계를 포함하여 충간절연막으로 사용하는 SOG층의 밀도저하 등의 문제를 해결하여 금속배선공정에서의 신뢰성을 향상시킨 반도체소자의 제조방법을 제공할 수 있는 효과가 있다.A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a wiring layer on a predetermined region of a substrate; forming a first insulating film and an interlayer insulating film on the first insulating film on the entire surface of the substrate including the wiring layer; Forming a second insulating film and a photosensitive film in order, selectively patterning the photosensitive film in the upper layer of the wiring layer, and selectively removing the second insulating film, the interlayer insulating film, and the first insulating film by an etching process using the patterned photosensitive film as a mask. Forming a via hole, and removing the patterned photoresist and the residue in the via hole by a directional ashing method to solve a problem such as a decrease in density of the SOG layer used as the interlayer insulating film in the metal wiring process. There is an effect that can provide a method for manufacturing a semiconductor device with improved reliability.
Description
본 발명은 반도체소자소자에 관한 것으로 특히, 방향성 에싱(ashing)을 통한 메탈 층간 절연막의 신뢰성을 향상하기에 적당한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device devices, and more particularly, to a method for manufacturing a semiconductor device suitable for improving the reliability of a metal interlayer insulating film through directional ashing.
반도체소자가 점차로 고집적화, 다층화함에 따라 중요한 기술의 하나로 다층배선기술이 등장하게 되었는데 이와 같은 다층배선은 배선 패턴층과 절연막층(층간절연막)을 반도체 웨이퍼 위에 번갈아 겹쳐쌓는 구조로, 상하의 배선층은 층간절연막에 설치된 접속홀을 통해서 상호 접속된다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring has emerged as one of the important technologies. Such multilayer wiring has a structure in which a wiring pattern layer and an insulating layer (interlayer insulating film) are alternately stacked on a semiconductor wafer, and upper and lower wiring layers are interlayer insulating films. They are interconnected through connecting holes installed in the
반도체소자에서 다층배선이 필요한 이유는 교차배선을 가능하게 하여 회로설계의 자유도, 집적도 그리고 배선 길이를 단축하여 배선이 수반되는 속도의 지연 시간을 짧게 하여 소자 동작 속도를 향상시키는 것 등이다.The reason why multi-layer wiring is required in semiconductor devices is to improve the operation speed of the device by shortening the delay time of the wiring by shortening the degree of freedom of circuit design, integration degree and wiring length by enabling cross wiring.
이와 같은 다층배선 구조는 앞에서도 설명한 바와 같이 배선층과 절연층(층간절연막)을 번갈아 쌓아 올리는 것으로 층간절연막 등의 절연막은 절연 내압이 높고 유전율, 유전손실이 작을 것, 습기나 알카리 이온 오염 등의 침입을 방지할 것, 크랙이 발생하지 않은 것 등의 여러 조건을 만족하여야 한다.As described above, the multilayer wiring structure alternately stacks the wiring layer and the insulating layer (interlayer insulating film) .The insulating film such as the interlayer insulating film has a high dielectric breakdown voltage, low dielectric constant, low dielectric loss, and invasion of moisture or alkali ion contamination. It should satisfy various conditions such as the prevention of cracks and the absence of cracks.
이하에서, 종래 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래 반도체소자의 제조공정 단면도이다.1A to 1E are cross-sectional views of a manufacturing process of a conventional semiconductor device.
먼저, 도 1a에 나타낸 바와 같이, 기판(1)의 소정영역상에 배선층(2)을 형성한다.First, as shown in FIG. 1A, the wiring layer 2 is formed on a predetermined region of the substrate 1.
도 1b에 나타낸 바와 같이, 상기 배선층(2)을 포함한 기판(1)전면에 제 1 산화막(3)을 형성한후 상기 제 1 산화막(3)전면에 SOG(Spin On Glass)층(4)과 제 2 산화막(5)을 형성한다. 이때, SOG층(4)은 층간절연막의 특성 뿐 아니라 유동성이 좋아 평탄화공정에 유리한 물질이다.As shown in FIG. 1B, a first oxide film 3 is formed on the entire surface of the substrate 1 including the wiring layer 2, and then a SOG (Spin On Glass) layer 4 is formed on the entire surface of the first oxide film 3. The second oxide film 5 is formed. At this time, the SOG layer 4 is not only the characteristics of the interlayer insulating film, but also has good fluidity, which is advantageous for the planarization process.
도 1c에 나타낸 바와 같이, 상기 제 2 산화막(5)상에 감광막(PR)을 형성한후 노광 및 현상공정으로 배선층(2)상층의 제 2 산화막(5)이 부분적으로 노출되도록 감광막(PR)을 패터닝한다.As shown in FIG. 1C, after the photoresist film PR is formed on the second oxide film 5, the photoresist film PR is partially exposed so that the second oxide film 5 of the upper layer of the wiring layer 2 is partially exposed by the exposure and development processes. Pattern.
도 1d에 나타낸 바와 같이, 상기 패터닝된 감광막(PR)을 마스크로 이용한 식각공정으로 제 2 산화막(5), SOG층(4) 그리고 제 1 산화막(3)을 선택적으로 제거하여 배선층(2)의 상층면이 부분적으로 노출되도록 비아 홀(6)을 형성한다.As shown in FIG. 1D, the second oxide film 5, the SOG layer 4, and the first oxide film 3 are selectively removed by an etching process using the patterned photoresist film PR as a mask. Via holes 6 are formed to partially expose the top surface.
도 1e에 나타낸 바와 같이 상기와 같은 비아 홀(6)형성공정후 후속공정을 진행하기에 앞서 O2플라즈마(plasma)를 이용하여 랜덤(random)하게 감광막(PR) 애싱(ashing)공정을 진행한다. 이때, 감광막(PR)에 대한 애싱(ashing) 공정은 감광막(PR) 패턴 뿐만 아니라 감광막(PR)을 마스크로 이용한 식각공정후의 잔류물인 레지듀(residue) 등에 대한 애싱(ashing)공정도 포함하고 있다.As shown in FIG. 1E, the photoresist (ASH) ashing process is randomly performed using an O 2 plasma prior to the subsequent process after the via hole 6 formation process as described above. . In this case, the ashing process for the photoresist film PR includes not only the photoresist pattern PR but also an ashing process for a residue, which is a residue after the etching process using the photoresist film PR as a mask. .
종래 반도체소자의 제조방법에 있어서는 O2플라즈마를 이용하여 애싱공정을 진행할 때 층간절연막으로 사용하는 SOG층에 함유된 카본(Carbon)이나 하이드로젠(Hydrogen)이온이 랜덤(random)하게 반응하는 O2플라즈마의 산소와 반응하여 CO 가스와 수증기(H2O) 등을 발생시켜 SOG층 내의 카본(탄소)이나 하이드로젠(수소)의 밀도를 저하시키게 된다. 결국, 쉬링크(shrink)한 상태의 SOG층이 수분을 쉽게 흡수하게 되고 그와 같은 상태에서 비아 홀을 통한 금속배선을 하게되면 금속배선공정시에 필수적인 고온 공정을 수반하면서 SOG층의 수분과 금속배선이 반응하여 금속배선을 산화시키는등 부식이나, 수분에 의한 반도체소자의 특성을 감소시켜 반도체소자의 신뢰성을 저하시키는 문제점이 있었다. 참고로 SOG층이 O2플라즈마와 쉽게 반응하는 이유는 O2플라즈마와 감광막 패턴 또는 레지듀등과의 반응성을 향상시키기 위하여 높은 압력(1 torr 이상)과 높은 온도(100 ℃ 이상)에서 공정을 진행하기 때문에 플라즈마 충돌로 O2플라즈마들이 랜덤하게 반응하면서 SOG층과 직접적으로 접촉하기 때문이다.O 2 for the prior time in the manufacturing method of the semiconductor device by using the O 2 plasma proceed with the ashing process with carbon (Carbon) or hydrogen (Hydrogen) ions contained in the SOG layer used as interlayer insulating the reaction at random (random) Reaction with oxygen in the plasma generates CO gas, water vapor (H 2 O), and the like, thereby lowering the density of carbon (carbon) or hydrogen (hydrogen) in the SOG layer. As a result, the shrinked SOG layer easily absorbs moisture, and if the metal wiring is performed through the via hole in such a state, the moisture and metal of the SOG layer are accompanied by the high temperature process essential for the metal wiring process. There is a problem that the reliability of the semiconductor device is reduced by reducing the characteristics of the semiconductor device due to corrosion or moisture, such as oxidizing the metal wire by reacting the wiring. Note that the reason why SOG layer is easy to react with O 2 plasma in order to improve the reactivity of such as O 2 plasma and the photoresist pattern or residue to proceed with the process at high pressure (more than 1 torr) and a temperature (more than 100 ℃) This is because the O 2 plasmas react in direct contact with the SOG layer in a plasma collision.
본 발명은 상기한 바와 같은 종래 반도체소자의 문제점을 해결하기 위하여 안출한 것으로 감광막을 이용한 비아 홀 형성공정후 애싱공정을 진행시킬 때 O2플라즈마를 수직방향으로 진행시켜 비아 홀에 측면이 노출된 SOG층과의 반응을 최대한 억제시키므로써 층간절연막의 특성저하 억제에 적당한 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the problems of the conventional semiconductor device as described above, SOG in which the side surface is exposed to the via hole by advancing O 2 plasma in the vertical direction when the ashing process is performed after the via hole forming process using the photosensitive film. It is an object of the present invention to provide a method for manufacturing a semiconductor device suitable for suppressing the deterioration of characteristics of an interlayer insulating film by suppressing the reaction with the layer as much as possible.
도 1a 내지 도 1e는 종래 반도체소자의 제조공정 단면도1A to 1E are cross-sectional views of a manufacturing process of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명 반도체소자의 제조공정 단면도2A to 2E are cross-sectional views of a manufacturing process of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 기판11 : 배선층10 substrate 11 wiring layer
12 : 제 1 절연막13 : 층간절연막12: first insulating film 13: interlayer insulating film
14 : 제 2 절연막15 : 비아 홀14 second insulating film 15 via hole
본 발명에 따른 반도체소자의 제조방법은 기판의 소정영역상에 배선층을 형성하는 단계, 상기 배선층을 포함한 기판전면에 제 1 절연막과 상기 제 1 절연막상에 층간절연막을 형성하는 단계, 상기 층간절연막상에 제 2 절연막과 감광막을 차례로 형성하는 단계, 상기 배선층 상층영역의 감광막을 선택적으로 패터닝하는 단계, 상기 패터닝된 감광막을 마스크로 이용한 식각공정으로 제 2 절연막, 층간절연막 그리고 제 1 절연막을 선택적으로 제거하여 비아 홀을 형성하는 단계, 상기 패터닝된 감광막 및 비아 홀 내의 레지듀를 방향성 에싱법으로 제거하는 단계를 포함한다.A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a wiring layer on a predetermined region of a substrate; forming a first insulating film and an interlayer insulating film on the first insulating film on the entire surface of the substrate including the wiring layer; Forming a second insulating film and a photosensitive film in order, selectively patterning the photosensitive film in the upper layer of the wiring layer, and selectively removing the second insulating film, the interlayer insulating film, and the first insulating film by an etching process using the patterned photosensitive film as a mask. Forming a via hole, and removing the residue in the patterned photoresist and the via hole by a directional ashing method.
이와 같은 본 발명 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2e는 종래 반도체소자의 제조공정 단면도이다.2A through 2E are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device.
먼저, 도 2a에 나타낸 바와 같이 기판(10)의 소정영역상에 배선층(11)을 형성한다.First, as shown in FIG. 2A, the wiring layer 11 is formed on a predetermined region of the substrate 10.
도 2b에 나타낸 바와 같이 상기 배선층(11)을 포함한 기판(10)전면에 제 1 절연막(12)을 형성한 후 상기 제 1 절연막(12)전면에 층간절연막(13)과 제 2 절연막(14)을 형성한다. 이때, 상기 층간절연막(13)은 SOG(Spin On Glass)로 형성한다. 이때, SOG는 유동성이 좋은 물질로써 평탄화공정에 유리한 물질이다. 그리고, 상기 제 1 절연막(12)과 제 2 절연막(14)은 산화막과 질화막중 어느 하나로 형성한다.As shown in FIG. 2B, the first insulating film 12 is formed on the entire surface of the substrate 10 including the wiring layer 11, and then the interlayer insulating film 13 and the second insulating film 14 are formed on the entire surface of the first insulating film 12. To form. In this case, the interlayer insulating layer 13 is formed of SOG (Spin On Glass). At this time, SOG is a material having good fluidity and is advantageous for the planarization process. The first insulating film 12 and the second insulating film 14 are formed of any one of an oxide film and a nitride film.
도 2c에 나타낸 바와 같이 상기 제 2 절연막(14)상에 감광막(PR)을 형성한후 노광 및 현상공정으로 상기 배선층(11) 상층의 제 2 절연막(14)이 부분적으로 노출되도록 감광막(PR)을 패터닝한다.As shown in FIG. 2C, after the photoresist film PR is formed on the second insulating film 14, the photoresist film PR is partially exposed so that the second insulating film 14 over the wiring layer 11 is partially exposed by an exposure and development process. Pattern.
도 2d에 나타낸 바와 같이 상기 패터닝된 감광막(PR)을 마스크로 이용한 식각공정으로 제 2 절연막(14), 층간절연막(13) 그리고 제 1 절연막(12)을 선택적으로 제거하여 상기 배선층(11)의 상층면이 부분적으로 노출되도록 비아 홀(15)을 형성한다.As shown in FIG. 2D, the second insulating film 14, the interlayer insulating film 13, and the first insulating film 12 are selectively removed by an etching process using the patterned photoresist film PR as a mask. Via holes 15 are formed to partially expose the top surface.
도 2e에 나타낸 바와 같이 상기와 같은 비아 홀(15)형성공정후 후속공정을 진행하기에 앞서 감광막(PR) 애싱(ashing)공정을 진행한다. 이때, 애싱 공정을 진행하는 조건은 O2플라즈마를 이용하는 것은 종래와 동일하나 상기 O2플라즈마를 이용한 애싱공정시의 압력을 1 torr 이하의 저압과 35℃ 이하 정도의 상온에서 실시하면 O2플라즈마들의 충돌을 억제시켜 방향성을 갖게 되어 감광막과 레지듀 등에 대해 직진성을 갖는 O2플라즈마를 사용한 애싱공정이 가능하다.As shown in FIG. 2E, the photoresist film ashing process is performed before the subsequent process after the via hole 15 forming process. In this case, it is conditions to proceed the ashing process using O 2 plasma be carried on the same one temperature of the low pressure and below 35 ℃ degree of the O less than 2 the pressure during the ashing process using plasma 1 torr in the prior art of the O 2 plasma The ashing process using the O 2 plasma which has a directivity by suppressing a collision and has linearity with respect to a photosensitive film, a residue, etc. is possible.
본 발명에 따른 반도체소자의 제조방법에 있어서는 애상공정시의 O2플라즈마들이 저압 및 저온 상태로 플라즈마를 반응시키므로 플라즈마들간의 충돌을 최대한 억제시킬 수 있어 감광막 패턴과 비아 홀내의 레지듀를 제거하는 공정시 비아홀 내에서 측면이 노출되는 SOG층과의 반응을 억제시키므로 SOG층의 밀도저하 등의 문제가 해결되어 금속배선공정에서의 신뢰성을 향상시킨 반도체소자의 제조방법을 제공할 수 있는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention, since the O 2 plasmas during the defrosting process react the plasma at low pressure and low temperature, the collision between the plasmas can be suppressed to the maximum, thereby removing the photoresist pattern and the residue in the via hole. Since the reaction with the SOG layer exposed to the side surface in the via via hole is suppressed, problems such as a decrease in the density of the SOG layer are solved, thereby providing a method of manufacturing a semiconductor device having improved reliability in a metal wiring process.
Claims (4)
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| KR1019960066696A KR100239411B1 (en) | 1996-12-17 | 1996-12-17 | Method of manufacturing semiconductor device |
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| KR20020050080A (en) * | 2000-12-20 | 2002-06-26 | 다니구찌 이찌로오, 기타오카 다카시 | A semiconductor device, and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20020050080A (en) * | 2000-12-20 | 2002-06-26 | 다니구찌 이찌로오, 기타오카 다카시 | A semiconductor device, and method of manufacturing the same |
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