KR19980028087A - 3D semiconductor package and manufacturing method thereof - Google Patents
3D semiconductor package and manufacturing method thereof Download PDFInfo
- Publication number
- KR19980028087A KR19980028087A KR1019960047073A KR19960047073A KR19980028087A KR 19980028087 A KR19980028087 A KR 19980028087A KR 1019960047073 A KR1019960047073 A KR 1019960047073A KR 19960047073 A KR19960047073 A KR 19960047073A KR 19980028087 A KR19980028087 A KR 19980028087A
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- semiconductor package
- bond
- manufacturing
- pads
- conductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 3차원 반도체 패키지 및 그 제조방법에 관한 것으로, 종래 기술에 의한 3차원 반도체 패키지 및 그 제조방법은 그 반도체 패키지의 집적도에 비하여 경박단소화가 난이할뿐만 아니라 리드와 솔더로 인하여 전기적 성능이 저하되고, 또 제조공정수가 많아 생산비를 증가시키게 되는 문제점이 있었다. 이러한 문제점을 해결하기 위하여 본 발명은 아래 도면에 도시된 바와 같이 패드(12)가 형성된 상기 반도체 패키지(13)에 본드컨덕터(14)를 형성하고, 그 반도체 패키지(13)를 다수개 적층하여 상기 본드컨덕트(14)와 본드컨덕트(14)를 전기적으로 통할 수 있도록 사이드버티컬컨덕션(15)을 형성하므로써, 상기 반도체 패키지의 집적도에 비하여 경박단소화되고, 또 패드와 패드를 상기 본드컨덕트와 사이드버티컬컨덕트로 연결하므로 전기적 성능이 향상됨과 아울러 제조공정수가 절감되어 생산비가 절감되게 되는 효과가 있다.The present invention relates to a three-dimensional semiconductor package and a method of manufacturing the same. The three-dimensional semiconductor package and the manufacturing method according to the prior art are not only light and short and difficult compared to the integration degree of the semiconductor package, but also has electrical performance due to the lead and solder. There was a problem in that the production cost was lowered and the number of manufacturing steps was increased. In order to solve this problem, the present invention forms a bond conductor 14 on the semiconductor package 13 on which the pad 12 is formed, as shown in the drawings, and stacks a plurality of the semiconductor packages 13 to the By forming the side vertical conduction 15 so as to electrically connect the bond conductor 14 and the bond conductor 14, the thickness and the thickness of the semiconductor package are reduced, and the pads and the pads are connected to the bondcone. Since the duct and the side vertical conduction are connected, the electrical performance is improved and the number of manufacturing processes is reduced, thereby reducing the production cost.
Description
본 발명은 3차원 반도체 패키지 및 그 제조방법에 관한 것으로, 특히 패드에 본드컨덕터를 연결형성한 반도체 패키지를 적층하고, 그 적층된 상기 반도체 패키지의 측부에 사이드버티걸커넥션을 형성하여 그 반도체 패키지를 경박단소화 함과 아울러 반도체 칩의 물리적인 손상을 방지하고, 또 전기적 특성을 향상할 수 있도록 한 3차원 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional semiconductor package and a method of manufacturing the same. In particular, a semiconductor package in which bond conductors are connected to a pad is laminated, and sidevert-girl connections are formed on the side of the stacked semiconductor package to form the semiconductor package. The present invention relates to a three-dimensional semiconductor package and a method of manufacturing the same, which are capable of reducing the size and thickness of the semiconductor chip and preventing physical damage to the semiconductor chip and improving electrical characteristics.
종래 기술에 의한 3차원 반도체 패키지(1)는 상기 도 1에 도시된 바와 같이, 에폭시 수지와 같은 몰드물로 몰드되고, 외부의 전기적인 회로와 전기적으로 통할 수있게 연결되는 리드(2)가 다수개 설치된 반도체 패키지(3)를 다단으로 적층하여, 적층된 상기 반도체 패키지(3)의 리드(2)와 리드(2)를 전기적으로 통할 수 있도록 솔더(4)로 연결하여 구성한 것이다.As shown in FIG. 1, the three-dimensional semiconductor package 1 according to the related art is molded of a mold such as an epoxy resin, and has a plurality of leads 2 electrically connected to an external electrical circuit. The semiconductor packages 3 installed in multiple stages are stacked, and the leads 2 and the leads 2 of the stacked semiconductor packages 3 are connected to each other by solder 4 so as to be electrically connected.
상기와 같이 구성된 3차원 반도체 패키지(1)는 기존의 반도체 패키지 공정을 거쳐 만들어진 단품 반도체 패키지(3)를 적층하는 공정만 추가하여 만들어 지게 되는 것이다.The 3D semiconductor package 1 configured as described above is made by adding only a process of stacking a single-component semiconductor package 3 made through a conventional semiconductor package process.
그러나, 상기와 같이 구성된 3차원 반도체 패키지 및 그 제조방법은 그 반도체 패키지의 집적도에 비하여 경박단소화가 난이할뿐만 아니라 리드와 솔더로 인하여 전기적 성능이 저하되고, 또 제조공정수가 많아 생산비를 증가시키게 되는 문제점이 있었다.However, the three-dimensional semiconductor package and the manufacturing method configured as described above are not only light and small, but also difficult to reduce the thickness of the semiconductor package compared with the integration of the semiconductor package, the electrical performance is lowered due to the lead and solder, and the number of manufacturing processes increases the production cost There was a problem.
따라서, 본 발명의 목적은 상기의 문제점을 해결하여 반도체 패키지를 경방박단소화 함과 아울러 전기적 성능을 향상하그, 또 제조공정수를 줄여 생산비를 절감할수 있도록 한 3차원 반도체 패키지 및 그 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a three-dimensional semiconductor package and a method of manufacturing the same to solve the above problems and to reduce the manufacturing cost of the semiconductor package, to improve the electrical performance, and to reduce the production cost by reducing the number of manufacturing processes. Is in.
도 1은 종래 기술에 3차원 반도체 패키지의 종단구조를 단면도.1 is a cross-sectional view of a termination structure of a three-dimensional semiconductor package in the prior art.
도 2는 본 발명에 의한 3차원 반도체 패키지의 종단구조를 단면도.Figure 2 is a cross-sectional view of the termination structure of the three-dimensional semiconductor package according to the present invention.
도 3a는 본 발명에 의한 3차원 반도체 패키지의 제조공정을 보인 것으로, 다수개의 패드가 형성된 반도체 패키지의 구조를 보인 단면도.Figure 3a is a cross-sectional view showing a structure of a semiconductor package having a plurality of pads, showing a manufacturing process of a three-dimensional semiconductor package according to the present invention.
도 3b는 본 발명에 의한 3차원 반도체 패키지의 제조공정을 보인 것으로, 반도체 패키지에 본드컨덕트를 형성한 구조를 보인 단면도.Figure 3b is a cross-sectional view showing a manufacturing process of the three-dimensional semiconductor package according to the present invention, a bond conductor formed on the semiconductor package.
도 3c는 본 발명에 의한 3차원 반도체 패키지의 제조공정을 보인 것으로, 본드 컨덕트가 형성된 다수개의 반도체 패키지를 적층한 상태를 보인 단면도.3C is a cross-sectional view illustrating a manufacturing process of a three-dimensional semiconductor package according to the present invention, in which a plurality of semiconductor packages on which bond conductors are formed are stacked.
도 3d는 본 발명에 의한 3차원 반도체 패키지의 제조공정을 보인 것으로, 다수개 적층한 반도체 패키지에 사이드버티컬컨넥션을 형성하기 위한 버티컬홀을 형성한 반도체 패키지의 구조를 보인 단면도.FIG. 3D is a cross-sectional view illustrating a structure of a semiconductor package in which a vertical hole for forming side vertical connections is formed in a plurality of stacked semiconductor packages according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 3차원 반도체 패키지 12 : 패드11: three-dimensional semiconductor package 12: pad
13 : 반도체 패키지 14 : 본드컨덕터13: semiconductor package 14: bond conductor
15 : 사이드버티컬컨덕션15: Side Vertical Conduction
본 발명의 목적은 외부의 전기적인 회로와 전기적으로 통할 수 있도록 연결되는 다수개의 패드가 설치된 반도체 칩과, 그 반도체 칩의 패드에 형성한 본드컨덕터와,그 본드컨덕터가 형성된 상기 반도체 패키지를 다수개 적층하여 그 반도체 패키지의 패드에 형성한 본드컨덕트와 본드컨덕트가 전기적으로 통할 수 있도록 연결 형성한 사이드버티컬커넥션을 구비하여 구성된 것을 특징으로 하는 3차원 반도체 패키지에 의하여 달성된다.SUMMARY OF THE INVENTION An object of the present invention is to provide a plurality of semiconductor chips provided with a plurality of pads connected to communicate with an external electrical circuit, a bond conductor formed on a pad of the semiconductor chip, and a plurality of the semiconductor packages on which the bond conductors are formed. It is achieved by a three-dimensional semiconductor package, characterized in that it is provided with a side vertical connection formed by laminating and bonding the bond conductor and the bond conductor formed on the pad of the semiconductor package.
또, 본 발명의 목적은 외부의 전기적인 회로와 전기적으로 통할 수 있도록 형성한 다수개의 패드가 설치되고 몰드물로 몰드된 반도체 패키지의 패드에 본드컨덕터를 형성하는 단계와, 상기 본드컨덕터가 형성된 반도체 패키지를 다수개 적층하는 단계와, 상기 적층된 반도체 패키지의 본드컨덕트와 본드컨덕트를 전기적으로 통할 수 있도록 사이드버티컬커넥션을 형성하는 단계로 제조되는 3차원 반도체 패키지의 제조방법에 의하여 달성된다.In addition, an object of the present invention is the step of forming a bond conductor on the pad of the semiconductor package molded and molded with a plurality of pads are formed so as to be in electrical communication with the external electrical circuit, the semiconductor with the bond conductor is formed A method of manufacturing a three-dimensional semiconductor package is manufactured by stacking a plurality of packages and forming sidevertical connections to electrically connect the bonded and bonded conductors of the stacked semiconductor packages.
다음은, 상기 본 발명에 의한 3차원 반도체 패키지 및 그 제조방법의 일실시예를 침부된 도면에 의거하여 상세하게 설명한다.Next, an embodiment of the three-dimensional semiconductor package and a method of manufacturing the same according to the present invention will be described in detail with reference to the attached drawings.
도 2는 본 발명에 의한 3차원 반도체 패키지의 종단구조를 단면도이고, 도 3a는 본 발명에 의한 3차원 반도체 패키지의 제조공정을 보인 것으로, 다수개의 패드가 형성된 반도체 패키지의 구조를 보인 단면도이며, 또 도 3b는 본 ,발명에 의한 3차원반도체 패키지의 제조공정을 보인 것으로, 반도체 패키지에 본드컨덕트를 형성한 구조를 보인 단면도이고, 도 3c는 본 발명에 의한 3차원 반도체 패키지의 제조공정을 보인 것으로, 본드컨덕트가 형성된 다수개의 반도체 패키지를 적층한 상태를 보인 단면도이며, 도 3d는 본 발명에 의한 3차원 반도체 패키지의 제조공정을 보인것으로, 다수개 적층한 반도체 패키지에 사이드버티컬컨넥션을 형성하기 위한 버티컬홀을 형성한 반도체 패키지의 구조를 보인 단면도이다.Figure 2 is a cross-sectional view of the termination structure of the three-dimensional semiconductor package according to the present invention, Figure 3a is a cross-sectional view showing the structure of a semiconductor package having a plurality of pads, showing the manufacturing process of the three-dimensional semiconductor package according to the present invention, FIG. 3B is a cross-sectional view illustrating a manufacturing process of a three-dimensional semiconductor package according to the present invention, wherein a bond conductor is formed on a semiconductor package, and FIG. 3C is a manufacturing process of a three-dimensional semiconductor package according to the present invention. 3D is a cross-sectional view illustrating a manufacturing process of a three-dimensional semiconductor package according to the present invention, in which a plurality of semiconductor packages are formed with side vertical connections. It is sectional drawing which shows the structure of the semiconductor package which formed the vertical hole for forming.
상기 도 2에 도시된 바와 같이 본 발명에 의한 3차원 반도체 패키지(11)는 외부의 전기적인 회로와 전기적으로 통할 수 있도록 연결되는 다수개의 패드(12)가 설치되고 몰드물(13a)로 몰드된 반도체 패키지(13)가 있고, 그 반도체 패키지(13)의 패드(12)에 본드컨덕터(14)가 형성되어 있으며, 상기 본드컨덕트(14)가 형성된 반도체패키지(13)를 다수개 적층하여 그 본드컨덕트(14)와 본드컨덕트(14)가 전기적으로 통할 수 있도록 사이드버티컬커넥션(15)이 연결 형성되어 있다.As shown in FIG. 2, the three-dimensional semiconductor package 11 according to the present invention is provided with a plurality of pads 12 connected to be in electrical communication with an external electrical circuit and molded into a mold 13a. There is a semiconductor package 13, a bond conductor 14 is formed on a pad 12 of the semiconductor package 13, and a plurality of semiconductor packages 13 having the bond conductor 14 are stacked and Side vertical connections 15 are connected to each other so that the bond conductor 14 and the bond conductor 14 can be electrically connected to each other.
상기와 같이 구성된 3차원 반도체 패키지(13)는 상기 도 3a 내지 도 3d에 도시된 바와 같이, 먼저 외부의 전기적인 회로와 전기적으로 통할 수 있도록 형성한 다수개의 패드(12)가 설치되고 몰드물(13a)로 몰드된 반도체 패키지(13)의 패드(12)에 본드컨덕터(14)를 형성하고, 그 본드컨덕터(14)가 헝성된 반도체 패키지(13)를 다수개 적층하며, 상기 적층된 반도체 패키지(13)의 본드컨덕트(14)와 본드컨덕트(14)를 전기적으로 통할 수 있도록 사이드버티컬커넥션(15)을 형성하기 위하여 버티컬홀(15a)을 형성하고, 그 버티컬흘(15a)에 컨덕션메터리얼을 충진하여 상기 도2에 도시된 바와 같은 3차원 반도체 패키지(11)가 완성되는 것이다.As shown in FIG. 3A to FIG. 3D, the three-dimensional semiconductor package 13 configured as described above is provided with a plurality of pads 12 formed to be in electrical communication with an external electrical circuit. A bond conductor 14 is formed on the pad 12 of the semiconductor package 13 molded by 13a, and a plurality of the semiconductor packages 13 on which the bond conductors 14 are formed are stacked. A vertical hole 15a is formed in order to form the side vertical connection 15 so that the bond conductor 14 and the bond conductor 14 of (13) can be electrically connected to each other. The 3D semiconductor package 11 as shown in FIG. 2 is completed by filling the instruction material.
상기와 같이 패드가 형성된 반도체 패키지에 본드컨덕터를 형성하고, 그 반도체 패키지를 다수개 적층하여 상기 본드컨덕트와 본드컨덕트를 전기적으로 통할 수 있도록 사이드버티컬컨덕션을 형성하므로써, 상기 반도체 패키지의 집적도에 비하여 경박단소화되고, 또 패드와 패드를 상기 본드컨덕트와 사이드버티컬컨덕트로 연결하므로 전기적 성능이 향상됨과 아울러 제조공정수가 절감되어 생산비가 절감되게 되는 효과가 있다.As described above, a bond conductor is formed on a semiconductor package in which a pad is formed, and a plurality of semiconductor packages are stacked to form sidevertical conduction so as to electrically connect the bond conductor and the bond conductor, thereby integrating the semiconductor package. Compared to the light and shorter, the pad and the pad are connected to the bond conductor and the side vertical conductor, so that the electrical performance is improved and the number of manufacturing processes is reduced, thereby reducing the production cost.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960047073A KR100239703B1 (en) | 1996-10-21 | 1996-10-21 | Three dimension semiconductor package and fabrication method thereof |
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| KR1019960047073A KR100239703B1 (en) | 1996-10-21 | 1996-10-21 | Three dimension semiconductor package and fabrication method thereof |
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| KR19980028087A true KR19980028087A (en) | 1998-07-15 |
| KR100239703B1 KR100239703B1 (en) | 2000-01-15 |
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| KR (1) | KR100239703B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040086133A (en) * | 2003-04-01 | 2004-10-08 | 가부시끼가이샤 르네사스 테크놀로지 | Semiconductor device |
| KR100652440B1 (en) * | 2005-10-27 | 2006-12-01 | 삼성전자주식회사 | Semiconductor package, stack package using the same package and method of fabricating the same stack package |
| KR100729079B1 (en) * | 2000-12-29 | 2007-06-14 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5247423A (en) * | 1992-05-26 | 1993-09-21 | Motorola, Inc. | Stacking three dimensional leadless multi-chip module and method for making the same |
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1996
- 1996-10-21 KR KR1019960047073A patent/KR100239703B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100729079B1 (en) * | 2000-12-29 | 2007-06-14 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
| KR20040086133A (en) * | 2003-04-01 | 2004-10-08 | 가부시끼가이샤 르네사스 테크놀로지 | Semiconductor device |
| KR100652440B1 (en) * | 2005-10-27 | 2006-12-01 | 삼성전자주식회사 | Semiconductor package, stack package using the same package and method of fabricating the same stack package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100239703B1 (en) | 2000-01-15 |
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