KR100279249B1 - Stacked Package and Manufacturing Method - Google Patents

Abstract

The present invention relates to a laminated package in which two or more semiconductor packages are laminated and a method of manufacturing the same. In the stacked package according to the present invention, a plurality of leads parallel to each other are attached to one upper surface of the semiconductor chip so as to extend in an outward direction thereof, and are electrically connected to the bonding pads of the semiconductor chip by a plurality of metal wires, respectively. At least two unit semiconductor packages having a shape in which the spatial region including the semiconductor chip and the leads are sealed by the molding compound are stacked under an adhesive, and the leads of each unit semiconductor package are adjacent to the unit semiconductor package. The same roles as the leads of the interconnections are connected to each other by interconnection wiring, and a surface on which the interconnection wiring is formed is covered by a protective film, and solder balls for mounting on a substrate are mounted on the interconnection wiring. It penetrates through.

Description

Laminated package and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a stacked package in which two or more packages are stacked and a method of manufacturing the same.

Typically, wafer-like semiconductor chips obtained through known manufacturing processes are used for chip cutting, die attach, wire bonding, molding, and trim / forming. It is packaged through the containing assembly process. A cross-sectional structure of a general semiconductor package manufactured through the above assembly process is illustrated in FIG. 1, which will be described below.

As shown, the semiconductor chip 1 is attached on the die pad 2a of the lead frame including the die pad 2a and the inner leads 2b and the outleads 2c, and a metal wire (3) is electrically connected to the inner leads 2b. In addition, the spatial region including the semiconductor chip 1 and the inner leads 2b is sealed by a molding compound 4 such as an epoxy resin so that the semiconductor chip 1 is prevented from being damaged by external influences.

On the other hand, although not shown, when manufacturing the module, the semiconductor package is mounted by connecting out leads exposed to the outside of the molding compound with the electrode terminals of the substrate, respectively. However, there is a problem in that the mounting area is increased because a plurality of the semiconductor packages are mounted on the substrate. In addition, defects such as solder joint cracks in which the outlead portion connected to the substrate are damaged by external influences, for example, moisture, are generated. As a result, the semiconductor chip and the substrate through the outlead and innerlead are generated. There is a problem that the reliability of the module is deteriorated because the input and output of the electrical signal between them is not desired.

Therefore, efforts have recently been made to solve the above problems. As an example, the mounting area is reduced by manufacturing and using a stacked package in which two or more semiconductor chips are embedded in one package. Defects such as solder joint cracks are solved by using solder balls instead of outleads used as mounting means for semiconductor packages.

In the above, the stacked package for reducing the mounting area is a form in which two or more bare chips are stacked or two or more semiconductor packages are stacked. FIG. 2 is a view illustrating a stacked package manufactured by stacking two or more semiconductor packages on a substrate. As shown, the stacked package includes semiconductor packages 10a, 10b, and 10c fabricated through an assembly process, and the outleads 11a, 11b, and 11c of each package are formed with outleads of neighboring packages. The stacked package is mounted on the substrate 20 through the outleads 11c of the package 10c positioned at the bottom thereof.

However, since such a laminated package is made by soldering outleads of the package located at the bottom of the mounting on the substrate, there are still defects such as solder joint cracks, thereby degrading the electrical characteristics of the module. . In addition, the stacked package has a problem in that the overall manufacturing process is very difficult because the interconnects between the outleads of each semiconductor package and the outleads of the semiconductor package located below are interconnected, and thus, there is a problem in that it cannot be applied to mass production.

Accordingly, an object of the present invention is to provide a laminated package in which defects such as solder joint cracks are removed.

Another object of the present invention is to provide a method of manufacturing a laminated package easier.

1 illustrates a conventional semiconductor package.

2 illustrates a stacked package made according to the prior art.

3 to 9 are a series of cross-sectional views illustrating a method of manufacturing a stacked package according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

30: lead frame 30a: unit lead frame

32: lead 40: semiconductor chip

42: bonding pad 50: metal wire

60: molding compound 70: adhesive film

80a: primary protective film 80b: secondary protective film

90 interconnection wiring 100 unit semiconductor package

110: solder ball 200,200a, 200b, 200c, 200d: strip type package

300; Stacked Package

In the stacked package for achieving the object of the present invention, a plurality of leads arranged in parallel to each other is attached to the upper surface of one side of the semiconductor chip, the leads and the bonding pads of the semiconductor chip are wire bonded, In the spatial region including the semiconductor chip and the leads, two or more semiconductor packages encapsulated with a molding compound are stacked under an adhesive. In this case, the leads are exposed to the outside of the molding compound, and the leads of each semiconductor package are interconnected with the leads of the neighboring semiconductor package which play the same role. In addition, a protective film having a predetermined thickness is formed on the package surface on which the interconnect wiring is formed to prevent damage to the interconnect wiring from external influences, and some of the interconnect wirings are exposed to the outside through an etching process. Solder balls are attached to the interconnect wires for mounting on the substrate.

In addition, a method of manufacturing a stacked package for achieving another object of the present invention, first, attaching a semiconductor chip to a lead frame in a strip state in which leads are arranged only at one end, and corresponding bonding pads of the semiconductor chip and the same. After wire bonding between the leads, a molding process is performed to fabricate a semiconductor package in a strip state. Thereafter, two or more stripped semiconductor packages are laminated using an adhesive, and then trimmed. Subsequently, a passivation layer is formed on the disposed package surface of the leads, the leads are exposed through an etching process, and interconnections are formed by interconnecting the leads, which will perform the same role among the exposed leads, with a metal material. . Subsequently, after the protective film is formed on the surface of the package so that the interconnect wiring is covered, a portion of the interconnect wiring is exposed through an etching process as before. Then, solder balls for mounting to the substrate are respectively attached on the exposed interconnect wiring.

According to the present invention, since solder balls are used as a means for mounting on a substrate, defects such as solder joint cracks can be prevented, and since the leads are interconnected by using a metal material, the leads between neighboring semiconductor packages are prevented. The process can be simplified compared to the method of connecting the two.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 and 9 are a series of cross-sectional views for explaining a method of manufacturing a stacked package according to an embodiment of the present invention, which will be described below.

First, as shown in FIG. 3, a center pad type semiconductor chip (not shown) is formed on each of the unit lead frames 30a of the lead frame 30 in a strip state in which the leads 32 are arranged only at one end thereof. 40). At this time, the semiconductor chip 40 is attached such that its upper surface is in contact with the lower surface of the leads 32. Thereafter, the wire bonding process connects the bonding pads 42 and the corresponding leads 32 of the semiconductor chip to the metal wires 50, respectively.

Subsequently, as shown in FIG. 4, a strip type including several unit semiconductor packages 100 by individually encapsulating spatial regions including a semiconductor chip and wire-bonded leads through a transfer molding process. The package 200 is manufactured. Here, reference numeral 60 denotes a molding compound used in the transfer molding process.

Then, as shown in Fig. 5, two or more, preferably four strip-shaped packages 200a, 200b, 200c, 200d fabricated through the above process are stacked. At this time, between the stacked unit semiconductor packages 100 is a thermosetting or thermoplastic adhesive film 70 is interposed for adhesion between them as shown in FIG. 6, in the embodiment of the present invention, Instead of a conventionally used adhesive film having a three-layer structure having an adhesive material attached to the bottom thereof, only an adhesive material is used in consideration of cost.

Thereafter, as shown in FIG. 6, the trimming process is performed to separately separate the unit semiconductor packages stacked in a strip form, and to maintain flatness between the stacked unit semiconductor packages 100. Polish the cross section.

Then, as shown in FIG. 7, the polyimide-based nonconductive resin or film is laminated on one side of the stacked unit semiconductor packages 100, that is, the surface on which the leads 32 are disposed, to form a primary layer. The protective film 80a is formed. Then, the leads 32 of the unit semiconductor packages 100 are exposed through a known etching process.

Subsequently, as shown in FIG. 8, interconnections between the leads of the unit semiconductor packages 100 having the same role, for example, the same signal lines and power lines, are interconnected using copper or aluminum metal materials. To form the interconnection wiring 90.

Then, as shown in FIG. 9, the second protective layer 80b is formed by laminating a polyimide-based resin or film of a predetermined thickness on the package surface on which the interconnection interconnection 90 is formed, and then as in the previous case. Exposed portions of the interconnection interconnects are exposed through known etching processes. Then, each of the solder balls 110 for mounting to the substrate is attached to each of the exposed interconnects to complete the stacked package 300.

In the above, when manufacturing a general semiconductor package, a lead frame made of aluminum is used, while an embodiment of the present invention uses a lead frame made of copper. In detail, the lead frame made of copper has a higher electrical conductivity than the lead frame made of aluminum, but is easily corroded by external influences, for example, moisture, so that the lead frame made of copper may be It may lower the electrical characteristics. In addition, in order to prevent defects such as corrosion, an additional process such as a protective coating has to be added, thereby increasing the manufacturing time and cost. However, as described above, in the embodiment of the present invention, the leads are not exposed to the outside of the package, and furthermore, there is no need to consider the corrosion problem because the mounting process is made by solder balls. Therefore, in the embodiment of the present invention it is possible to use a lead frame made of copper, thereby improving the electrical properties of the laminated package.

In addition, in the embodiment of the present invention, since the mounting of the laminated package is made by solder balls, defects such as solder joint cracks generated in the conventional laminated package can be prevented, and as a result, the electrical reliability can be improved. do.

On the other hand, although not shown, in another embodiment of the present invention, a tab tape having a circuit pattern may be used instead of leads providing an electrical signal transmission path. This method is more expensive in terms of cost than the above-described embodiment of the present invention, but the thickness of the unit semiconductor package can be reduced as much as possible because the wire bonding process connecting the leads and the bonding pads of the semiconductor chip is eliminated. Thus, the thickness of the stacked package can be reduced.

In addition, in the exemplary embodiment of the present invention, a method of manufacturing an individual stacked package by stacking unit semiconductor packages in a strip form and then proceeding to a subsequent process is illustrated and illustrated, but a stacked package may be manufactured by stacking respective unit semiconductor packages. have.

As described above, since the laminated package of the present invention and the manufacturing method thereof use solder balls as a means for mounting on a substrate, defects such as solder joint cracks generated when using leads can be prevented. The electrical reliability of the stacked package can be improved.

In addition, by improving the method for connecting the leads of the stacked unit semiconductor packages, the number of packages to be stacked is not limited, and thus the mounting area can be significantly reduced.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (16)

A plurality of leads parallel to each other are attached to one upper surface of the semiconductor chip so as to extend in an outward direction thereof, and are electrically connected to the bonding pads of the semiconductor chip by a plurality of metal wires, respectively. At least two unit semiconductor packages having a shape in which a spatial region including the leads are sealed by a molding compound are stacked under an adhesive, and the leads of each unit semiconductor package play the same role as the leads of the neighboring unit semiconductor package. Doing is connected to each other by interconnection wiring, the surface on which the interconnection wiring is formed is covered with a protective film, the laminated package, characterized in that the solder ball is attached through the protective film on the interconnection wiring. The stack package of claim 1, wherein the leads are exposed at one end thereof on an outer side of the molding compound. The laminate package of claim 1 or 2, wherein the lead is made of copper. The package of claim 1, wherein the adhesive is a thermosetting or thermoplastic adhesive film. The package of claim 4, wherein the adhesive film is a single layer of adhesive material. The package of claim 1, wherein the protective layer comprises a first protective layer formed on the package surface and a second protective layer covering the interconnection wiring formed thereon. The laminate package according to claim 1 or 6, wherein the protective film is a polyimide-based nonconductive resin or film. The package of claim 1, wherein the interconnect wiring is copper or aluminum metal. Attaching a semiconductor chip to a lower surface of each of the unit lead frames of the lead frame in a strip state in which leads are arranged only at one end; Wire bonding between bonding pads and leads of the semiconductor chip; Molding each of the spatial regions including the semiconductor chip and wire-bonded leads to form a strip type package including several unit semiconductor packages; Stacking two or more strip-shaped packages; Separating the stacked unit semiconductor packages from the stacked strip packages; Forming a first passivation layer having a predetermined thickness on an arrangement surface of leads of the stacked unit semiconductor packages; Etching portions of the first passivation layer to expose leads of the unit semiconductor packages; Forming interconnection lines connecting leads selected from among the exposed leads of each unit semiconductor package and leads that will play the same role among leads of neighboring unit semiconductor packages; Forming a secondary passivation layer on the surface of the stacked unit semiconductor packages in which the interconnection wiring is formed; Etching portions of the second passivation layer to expose the interconnections; And Attaching solder balls on the exposed interconnect interconnects. 10. The method of claim 9, wherein the lead frame is made of copper. 10. The method of claim 9, wherein the strip packages are laminated by an adhesive. 12. The method of claim 11, wherein the adhesive is a thermosetting or thermoplastic adhesive film. The method of claim 12, wherein the adhesive film is a single layer of an adhesive material. 10. The method of claim 9, further comprising: polishing a cross section of leads to maintain flatness between the stacked unit semiconductor packages after separating the stacked unit semiconductor packages from the stacked strip-shaped packages. The manufacturing method of the laminated package. The method of claim 9, wherein the primary and secondary protective films are polyimide-based nonconductive resins or films. 10. The method of claim 9, wherein the interconnection wiring is formed of copper or aluminum metal.