KR19980025635A - Semiconductor Memory Device Manufacturing Method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method for manufacturing a semiconductor memory device suitable for increasing capacitance and simplifying a process.

Such a method for manufacturing a semiconductor memory device according to the present invention comprises the steps of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate; Selectively etching the second insulating layer and the first insulating layer to form a node contact hole; Forming a first conductive layer on the entire surface of the second insulating layer including the node contact hole and patterning the remaining conductive layer only in the capacitor region; After the insulating layer is formed on the entire surface of the second insulating layer including the patterned first conductive layer, only the upper surface of the first conductive layer on both sides of the node contact hole except the upper surface of the first conductive layer on the upper side of the node contact hole is exposed. Patterning to form an insulating layer hole; Forming a storage node including first and second conductive layers by forming a second conductive layer having a sidewall spacer shape on a side surface of the insulating layer hole; And removing the insulating layer and forming dielectric and plate nodes on the surface of the storage node.

Description

Semiconductor Memory Device Manufacturing Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method for manufacturing a semiconductor memory device suitable for increasing capacitance and simplifying process.

BACKGROUND With the development of semiconductor devices, the work of integrating many devices on one semiconductor chip has been actively performed.

In particular, in memory cells of DRAM (Dynamic Random Access Memory), various various cell structures have been proposed to minimize the device size.

Generally, a DRAM memory cell is composed of one transistor and one capacitor.

As described above, in a memory cell including one transistor and one capacitor, signal charges are stored in a storage node of a capacitor connected to a transistor (switching transistor).

Therefore, when the size of the memory cell is reduced due to the high integration of the semiconductor memory device, the size of the capacitor is also reduced, thereby reducing the number of charges that can be stored in the storage node.

Therefore, in order to deliver the desired signal without malfunctioning, the capacitor storage node of the memory cell must have a surface area above a certain value in order to secure the capacitor capacity required for signal transmission.

Therefore, in order to reduce the size of the memory cell, the storage node of the capacitor must have a relatively large surface area within a limited area of the semiconductor substrate.

Therefore, the form of the capacitor is to use the fin (PIN) or pillar (Pillar) structure in the parallel plate structure.

Hereinafter, a conventional method of manufacturing a semiconductor memory device will be described.

1A to 1D are cross-sectional views illustrating a manufacturing process of a conventional semiconductor memory device.

First, the nitride film 3 is sequentially formed as the first oxide film 2 and the etch stop layer on the semiconductor substrate 1 as shown in FIG. 1A. The nitride film 3 and the first oxide film 2 are selectively formed. It removes and forms the node contact hole 4. In this case, the node contact hole 4 is formed at the position where the impurity diffusion region 5 of the semiconductor substrate 1 is formed.

As shown in FIG. 1B, the first polysilicon 6 and the second oxide layer 7 for the storage node are sequentially formed on the front surface including the node contact hole 4. Next, the photoresist layer RR is deposited on the second oxide layer 7, and the photoresist layer PR is patterned by defining a storage node formation region by an exposure and development process, and then using the patterned photoresist layer PR as a mask. The oxide film 7 is selectively removed.

As shown in FIG. 1C, after the photoresist film PR is removed, a second polysilicon 8 is formed on the first polysilicon 6 including the second oxide film 7 and then etched back to form a second oxide film ( It forms in the side wall spacer shape at the side of 7). At this time, the first polysilicon 6 is also etched until the nitride film 3 is exposed to form the storage node 9 made of the first and second polysilicon 6 (8).

As shown in FIG. 1D, after removing the second oxide layer 7, a dielectric layer 10 is formed on the surface of the storage node 9, and then a third polysilicon is formed on the entire surface including the dielectric layer 10 and then etched to form a plate. Node 11 is formed.

In the conventional semiconductor memory device, the capacitance can be increased as compared with the case of using a planar storage node. However, since the planar structure is simply a cylindrical shape, there is a problem in that the integration of the semiconductor memory device is limited.

The present invention has been made to solve the problems of the conventional semiconductor memory device as described above to provide a method of manufacturing a semiconductor memory device by improving the capacitance by forming a storage node in a double-cylinder structure and a simple ring process There is this.

1A to 1D are cross-sectional views illustrating a manufacturing process of a conventional semiconductor memory device.

2A to 2G are cross-sectional views illustrating a manufacturing process of a semiconductor memory device according to a first embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a manufacturing process of a semiconductor memory device according to a second embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

20: semiconductor substrate 21: impurity diffusion region

22: first insulating film 23: second insulating film

24: node contact hole 25a: first conductive layer pattern

26: insulating layer 27: insulating layer hole

28a: second conductive layer pattern 29: storage node

30 dielectric film 31 plate electrode

A method of manufacturing a semiconductor memory device according to the present invention includes the steps of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate; Selectively etching the second insulating layer and the first insulating layer to form a node contact hole; Forming a first conductive layer on the entire surface of the second insulating layer including the node contact hole and patterning the remaining conductive layer only in the capacitor region; After the insulating layer is formed on the entire surface of the second insulating layer including the patterned first conductive layer, only the upper surface of the first conductive layer on both sides of the node contact hole except the upper surface of the first conductive layer on the upper side of the node contact hole is exposed. Patterning to form an insulating layer hole; Forming a storage node including first and second conductive layers by forming a second conductive layer having a sidewall spacer shape on a side surface of the insulating layer hole; And removing the insulating layer and forming dielectric and plate nodes on the storage node surface.

Such embodiments of the semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a process of manufacturing a semiconductor memory device according to the first embodiment of the present invention.

First, as shown in FIG. 2A, first and second insulating layers 22 and 23 are sequentially formed on a semiconductor substrate 20 on which an impurity diffusion region 21 to be used as a source (or drain) region is formed. The node contact holes 24 are formed by selectively patterning the first and second insulating layers 22 and 23 over the diffusion region 21 (photolithography process + etching process).

As shown in FIG. 2B, the first conductive layer 25 is formed on the entire surface of the second insulating layer 23 including the node contact hole 24. In this case, the first conductive layer 25 is formed using polysilicon, and the thickness of 500 to 4000 kW using low pressure chemical vapor deposition at a temperature of 520 to 620 ° C. using a gas such as SiH ₄ or SiH ₂ Cl ₂ . To form. Subsequently, after the photoresist film PR ₂₀ is formed on the entire surface of the first conductive layer 25, the photoresist film PR ₂₀ is patterned by defining a storage node formation region through an exposure and development process.

As illustrated in FIG. 2C, the first conductive layer 25 is selectively removed by an etching process using the patterned photosensitive film PR ₂₀ as a mask to form a first conductive layer pattern 25a. Then, the photosensitive film PR ₂₀ is removed. Next, the insulating layer 26 and the photosensitive film PR ₂₁ are sequentially formed on the entire surface of the second insulating film 23 including the first conductive layer pattern 25a. In this case, the insulating layer 26 is formed using any one of flat materials such as PSG, BPSG, and SOG, and has a thickness of 3000 to 5000 kPa.

As shown in FIG. 2D, only the photoresist film PR ₂₁ on the upper surface of the first conductive layer pattern 25a formation region is removed by the exposure and development process, except for the first photoresist film PR _{21 at the} node contact hole 24 formation position. The photosensitive film PR ₂₁ on the upper surface of the conductive layer pattern 25a is removed. In this case, the photoconductive film PR ₂₁ is formed on the insulating layer 26 so as to overlap the photosensitive film PR ₂₁ on the edges on both sides of the first conductive layer pattern 25a on both sides of the first conductive layer pattern 25a. Next, an etching process using the photoresist film PR ₂₁ as a mask is performed to etch the insulating layer 26 under the photoresist film PR ₂₁ to exclude the first conductive layer pattern 25a of the node contact hole 24 forming region. The insulating layer hole 27 which exposes the upper surface of one conductive layer pattern 25a is formed. In this case, since the photosensitive film PR ₂₁ is formed on both sides of the first conductive layer pattern 25a on the insulating layer 26 on the upper layer of the first conductive layer pattern 25a, the insulating layer is formed. (26) is formed to overlap the edge portion of the first conductive layer pattern (25a) at regular intervals.

As shown in FIG. 2E, the photosensitive film PR ₂₁ is removed. Next, a second conductive layer 28 having a predetermined thickness is formed on the entire surface of the insulating layer 26 including the insulating layer hole 27. At this time, the second conductive layer 28 is formed to a thickness of 500 ~ 3000Å using polysilicon.

As shown in FIG. 2F, the second conductive layer 28 is polished by chemical mechanical polishing to form a cylindrical second conductive layer pattern toward the insulating layer 26 on the upper layer surface of the first conductive layer pattern 25a ( 28a) to complete the storage node 29 including the first and second conductive layer patterns 25a and 28a. At this time, the chemical mechanical polishing process uses a polishing liquid containing water by adding some or all of the polishing solution of Al ₂ O ₃ or SiO ₂ and a chemical solution such as KOH, NH ₄ F or HF, and the pH is 9 It grinds on condition of -13. In this case, instead of the chemical mechanical polishing method, it may be formed using an etch back using a reactive ion etching (RIE) method.

As shown in FIG. 2G, the dielectric layer 30 is formed on the surface of the storage node 29 after the insulating layer 26 is removed, and polysilicon is formed on the entire surface of the dielectric layer 30 to be etched to form a plate node 31. Form.

Hereinafter, a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention will be described with reference to the accompanying drawings.

3A to 3F are sectional views of the manufacturing process according to the second embodiment of the present invention.

First, as shown in FIG. 3A, first and second insulating layers 22 and 23 are sequentially formed on a semiconductor substrate 20 on which an impurity diffusion region 21 to be used as a source (or drain) region is formed. The node contact hole 24 is formed to selectively expose the impurity diffusion region 21 region by selectively patterning the first and second insulating layers 22 and 23 over the diffusion region 21 (photolithography process + etching process). do.

As shown in FIG. 3B, the first conductive layer 25 and the insulating layer 26 are sequentially formed on the entire surface of the second insulating layer 23 including the node contact hole 24. In this case, the first conductive layer 25 is formed using polysilicon, and is 1000-5000 kPa using low pressure chemical vapor deposition at a temperature of 520-620 ° C. using a gas such as SiH ₄ or SiH ₂ Cl ₂ . Form to thickness. The insulating layer 26 is formed using any one of a silicon oxide film such as PSG, BPSG, or USG, and has a thickness of 3000 to 5000 kPa.

As shown in FIG. 3C, the photoresist film PR ₂₂ is formed on the entire surface of the insulating layer 26, and then the photoresist film PR ₂₂ is patterned by defining a capacitor formation region through an exposure and development process.

At this time, the photoresist film PR _{22 on the} upper layer of the node contact hole 24 is also removed, but the width is narrower than that of the node contact hole 24. Next, in the etching process using the photoresist film PR ₂₂ as a mask, the insulating layer 26 and the first conductive layer 25 are sequentially etched until the second insulating layer 23 is exposed, thereby forming the first conductive layer pattern 25a. ). At this time, an insulating layer hole 27 having a narrower width than the node contact hole 24 is formed above the node contact hole 24.

As shown in FIG. 3D, the photosensitive film PR ₂₂ is removed. Next, a second conductive layer 28 is formed on the entire surface of the second insulating layer 23 including the insulating layer hole 27. At this time, the second conductive layer 28 is formed to a thickness of 500 ~ 3000Å using polysilicon. The second conductive layer 28 is formed so as not to stick to each other in the insulating layer hole 27.

As shown in FIG. 3E, the second conductive layer 28 is polished by chemical mechanical polishing, so that the side surface of the insulating layer 27 and the first conductive layer pattern 25a and the first conductive layer pattern in the insulating layer hole 27 are removed. A storage node 29 made of the first and second conductive layer patterns 25a and 28a is formed by forming the cylindrical second conductive layer pattern 28a on the upper layer surface. At this time, the chemical mechanical polishing process uses a polishing liquid containing water by adding some or all of the abrasives made of Al ₂ O ₃ or SiO ₂ and a chemical solution such as KOH, NH ₄ F or HF, and the pH is 9∼ Polished under the conditions of 13. In this case, it may be formed using an etch back method using RIE (Reactive Ion Etch) instead of the chemical mechanical polishing method.

As shown in FIG. 3F, the dielectric layer 30 is formed on the surface of the storage node 29 after the insulating layer 26 is removed, and polysilicon is formed on the entire surface of the dielectric layer 30 to be etched to form a plate node 31. Form.

In the method of manufacturing a semiconductor memory device according to the present invention, since a plurality of cylindrical (cylindrical) storage nodes can be formed by one etching process using chemical mechanical polishing, a highly integrated semiconductor memory device can be provided in a simple process. It works.

Claims (8)

Sequentially forming a first insulating film and a second insulating film on the semiconductor substrate; Selectively etching the second insulating layer and the first insulating layer to form a node contact hole; Forming a first conductive layer on the entire surface of the second insulating layer including the note contact hole and patterning the remaining conductive layer only in the capacitor region; After the insulating layer is formed on the entire surface of the second insulating layer including the patterned first conductive layer, the insulating layer is exposed to expose the upper surface of the first conductive layer on both sides of the node contact hole except the upper surface of the first conductive layer on the upper side of the node contact hole. Patterning to form insulating layer holes; Forming a storage node including first and second conductive layers by forming a second conductive layer having a sidewall spacer shape on a side surface of the insulating layer hole; And Removing the insulating layer and forming a dielectric film and a plate node on a surface of a storage node. The method of claim 1, wherein the first conductive layer is formed using polysilicon, and the gas is 500-4000 Pa by using a low pressure chemical vapor deposition method at a temperature of 520 ~ 620 ℃ using a gas such as SiH ₄ or SiH ₂ Cl ₂ A method of manufacturing a semiconductor memory device, characterized in that formed in a thickness. The method of claim 1, wherein the insulating layer is formed using any one of planar materials such as PSG, BPSG, and SOG, and has a thickness of about 3000 to about 5000 microns. The method of manufacturing a semiconductor memory device according to claim 1, wherein the second conductive layer (28) is formed to have a thickness of 500 to 3000 GPa using polysilicon. The method of claim 1, wherein the second conductive layer having a sidewall spacer shape is formed on a side surface of the insulating layer hole, wherein a second conductive layer having a predetermined thickness is formed on an entire surface of the second insulating layer including the insulating layer and the first storage node. And then polishing the second conductive layer by chemical mechanical polishing to form a cylindrical shape on the side of the insulating layer of the upper surface of the first storage node. 6. The chemical mechanical polishing process according to claim 5, wherein the chemical mechanical polishing process is performed by using a polishing liquid containing water in which part or all of an abrasive made of Al ₂ O ₃ or SiO ₂ and a chemical solution such as KOH, NH ₄ F or HF are added. Wherein the PH is polished under the conditions of 9 to 13; The semiconductor memory according to claim 1, wherein the second conductive layer having the sidewall spacer shape on the side of the insulating layer hole is formed by an etch back process using a reactive ion etching (RIE) method. Method of manufacturing the device. Sequentially forming a first insulating film and a second insulating film on the semiconductor substrate; Selectively etching the second insulating layer and the first insulating layer to form a node contact hole; After the first conductive layer and the insulating layer are sequentially formed on the entire surface of the second insulating layer including the node contact hole, the insulating layer and the first conductive layer are selectively removed to be patterned so as to remain only in the capacitor region, and also to be insulated in the node contact hole forming region. Selectively removing the layer and the first conductive layer to form an insulating layer hole having a width narrower than that of the node contact hole; Forming a storage node including first and second conductive layers by forming a second conductive layer having sidewall spacer shapes on side surfaces of the insulating layer and the first conductive layer; And, Removing the insulating layer and forming a dielectric film and a plate node on a surface of a storage node.