KR19980015779U - Heat dissipation structure of semiconductor package - Google Patents
Heat dissipation structure of semiconductor package Download PDFInfo
- Publication number
- KR19980015779U KR19980015779U KR2019960029048U KR19960029048U KR19980015779U KR 19980015779 U KR19980015779 U KR 19980015779U KR 2019960029048 U KR2019960029048 U KR 2019960029048U KR 19960029048 U KR19960029048 U KR 19960029048U KR 19980015779 U KR19980015779 U KR 19980015779U
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- semiconductor package
- heat dissipation
- lead frame
- wire bonding
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 14
- 238000000465 moulding Methods 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 abstract description 9
- 229920005989 resin Polymers 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 고안은 반도체 패키지 공정시, 와이어 본딩되는 부위를 제외한 칩의 전영역이 노출되도록 하여 반도체 패키지의 열방출 성능을 향상시킴과 동시에 몰딩수지의 소요량을 줄일 수 있도록 한 것이다.The present invention is to improve the heat dissipation performance of the semiconductor package while reducing the requirement of the molding resin by exposing the entire area of the chip except for the wire bonding portion during the semiconductor package process.
이를 위해, 본 고안은 리드프레임(1)의 패들(2)에 안착된 칩(3) 상면의 본딩패드(4)와 리드프레임(1)의 인너 리드(5)를 연결하는 와이어 본딩 후, 칩(3)과 리드프레임(1)의 와이어 본딩된 부분을 제외한 전영역이 노출되어 열방출면으로 작용하도록 칩(3)과 인너 리드(5)의 와이어 본딩 부위만 몰딩하여서 된 반도체 패키지의 열방출 구조이다.To this end, the present invention, after the wire bonding connecting the bonding pad 4 of the upper surface of the chip 3 seated on the paddle 2 of the lead frame 1 and the inner lead 5 of the lead frame 1, the chip The heat dissipation structure of the semiconductor package formed by molding only the wire bonding portions of the chip 3 and the inner lead 5 so that the entire area except for the wire bonded portion 3 and the lead frame 1 is exposed to act as a heat dissipation surface. to be.
Description
본 고안은 반도체 패키지의 열방출 구조에 관한 것으로서, 더욱 상세하게는 반도체 패키지의 와이어 본딩 부위를 제외한 칩의 전영역이 노출되도록 하여 반도체 패키지의 열방출 성능을 향상시킴과 동시에 몰딩수지의 소요량을 줄일 수 있도록 한 것이다.The present invention relates to a heat dissipation structure of a semiconductor package, and more particularly, to expose the entire area of the chip except for the wire bonding portion of the semiconductor package, thereby improving the heat dissipation performance of the semiconductor package and at the same time reducing the amount of molding resin required. I would have to.
일반적으로, 반도체소자 제조를 위해 웨이퍼에 집적회로를 형성하는 FAB공정(Fabrication Process)을 완료한 후에는 웨이퍼 상에 만들어진 각 칩(3)을 분리하는 다이싱(Dicing), 분리된 각 칩(3)을 리드프레임(1)의 패들(2)(paddle)에 안착시키는 칩(3) 본딩(Chip Bonding), 칩(3) 위의 본딩패드(4)(Bonding pad)와 리드프레임(1)의 인너 리드(5)(Inner Lead)를 전기적으로 접속시키는 와이어 본딩(Wire Bonding)을 순차적으로 수행한 후 회로를 보호하기 위해 몰딩(Molding)을 수행하게 된다.In general, after completing a FAB process (fabrication process) for forming an integrated circuit on a wafer for manufacturing a semiconductor device, dicing and separating each chip (3) made on the wafer (3) ) Is bonded to the chip (3) bonding (Bonding pad) on the chip 3 and the lead frame (1) seated on the paddle (2) (paddle) of the lead frame (1) The wire bonding is sequentially performed to electrically connect the inner lead 5, and then molding is performed to protect the circuit.
또한, 몰딩을 수행한 후에는 리드프레임(1)의 써포트 바(Supper Bar) 및 댐 바(Dam Bar)를 자르는 트리밍(Trimming) 및 아웃 리드(7)(Out Lead)를 소정의 형상으로 굽혀 주는 포밍(Forming)을 동시에 수행하고 난 후, 최종적으로 솔더링(Sodering)을 실시하므로써 패키지 공정을 완료하게 된다.In addition, after molding, the trimming and the out lead 7 for cutting the support bar and the dam bar of the lead frame 1 are bent in a predetermined shape. After forming and simultaneously forming, the soldering process is finally performed to complete the package process.
그러나, 이와 같이 제조되는 종래의 반도체 패키지(6a)는 칩(3)의 동작시, 칩(3)에서 발생하는 열을 효과적으로 방출할 수가 없었다.However, the conventional semiconductor package 6a manufactured as described above was unable to effectively release heat generated in the chip 3 during the operation of the chip 3.
즉, 칩(3)의 구동시 발생되는 열은 도 1 및 도 2에 나타낸 바와 같이 리드 프레임(1)의 패들(2)을 통해 몰딩수지(9)로 전달되어 방출되거나, 칩(3) 상면의 본딩패드(4)와 리드프레임(1)의 인너 리드(5)를 연결하는 와이어(8)를 통해 아웃 리드(7)로 전달되어 방출되나, 열방출 성능이 미약하여 반도체 패키지(6a)의 소자 특성을 저하시키거나 수명을 단축시키게 되는 문제점이 있었다.That is, the heat generated when the chip 3 is driven is transferred to the molding resin 9 through the paddle 2 of the lead frame 1 and discharged as shown in FIGS. 1 and 2, or the upper surface of the chip 3. Is transferred to the out lead 7 through a wire 8 connecting the bonding pad 4 of the lead frame 1 and the inner lead 5 of the lead frame 1, but the heat dissipation performance of the semiconductor package 6a is poor. There is a problem in that device characteristics are reduced or the life is shortened.
한편, 종래의 반도체 패키지(6a)는 몰딩수지(9)가 칩(3) 둘레를 전체적으로 감싸므로 인해 몰딩수지(9)의 소요량이 많아 반도체 패키지(6a)의 단가를 상승시키게 되는 등 많은 문제점이 있었다.On the other hand, the conventional semiconductor package (6a) has a number of problems, such as the molding resin (9) wraps around the chip 3 as a whole due to the large amount of molding resin (9) required to increase the unit cost of the semiconductor package (6a) there was.
본 고안은 상기한 제반 문제점을 해결하기 위한 것으로서, 반도체 패키지 공정시 와이어 본딩 부위를 제외한 칩의 전영역이 노출되도록 하여 반도체 패키지의 열방출 성능을 향상시킴과 동시에 몰딩수지의 소요량을 줄일 수 있도록 한 반도체 패키지의 열방출 구조를 제공하는데 그 목적이 있다.The present invention is to solve the above problems, and to improve the heat dissipation performance of the semiconductor package while reducing the requirements of the molding resin by exposing the entire area of the chip except the wire bonding portion during the semiconductor package process. The purpose is to provide a heat dissipation structure of a semiconductor package.
상기한 목적을 달성하기 위해, 본 고안은 리드프레임의 패들에 안착된 칩 상면의 본딩패드와 리드프레임의 인너 리드를 연결하는 와이어 본딩 후, 칩과 리드프레임의 와이어 본딩된 부분을 제외한 전영역이 노출되어 열방출면으로 작용하도록 칩과 인너 리드의 와이어 본딩 부위만 몰딩하여서 된 반도체 패키지의 열방출 구조이다.In order to achieve the above object, the present invention after the wire bonding connecting the bonding pad of the upper surface of the chip seated on the paddle of the lead frame and the inner lead of the lead frame, the entire area except the wire bonded portion of the chip and lead frame It is a heat dissipation structure of a semiconductor package formed by molding only a wire bonding portion of a chip and an inner lead to be exposed and act as a heat dissipation surface.
도 1은 종래의 반도체 패키지를 나타낸 종단면도1 is a vertical cross-sectional view showing a conventional semiconductor package
도 2는 도 1의 평면도2 is a plan view of FIG. 1
도 3은 본 고안에 다른 반도체 패키지를 나타낸 종단면도Figure 3 is a longitudinal cross-sectional view showing another semiconductor package in the present invention
도 4는 도 3의 평면도4 is a top view of FIG. 3
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1; 리드프레임2; 패들One; Leadframe 2; Paddle
3; 칩4; 본딩패드3; Chip 4; Bonding pad
5; 인너 리드6; 반도체 패키지5; Inner lead 6; Semiconductor package
7; 아웃 리드8; 와이어7; Out lead8; wire
9; 몰딩수지9; Molding resin
이하, 본 고안의 일실시예를 첨부도면 도 3 및 도 4를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.
도 3은 본 고안에 따른 반도체 패키지를 나타낸 종단면도이고, 도 4는 도 3의 평면도로서, 본 고안은 리드프레임(1)의 패들(2)에 안착된 칩(3) 상면의 본딩패드(4)와 인너 리드(5)를 연결하는 와이어 본딩 후, 칩(3)과 리드프레임(1)의 와이어 본딩 부위만 몰딩하여 칩(3)과 인너 리드(5)의 와이어 본딩된 부분을 제외한 전영역이 노출되어 열방출면으로 작용하도록 구성된다.3 is a longitudinal cross-sectional view illustrating a semiconductor package according to the present invention, and FIG. 4 is a plan view of FIG. 3, and the present invention is a bonding pad 4 on an upper surface of a chip 3 seated on a paddle 2 of a lead frame 1. ) And the entire area except the wire bonded portions of the chip 3 and the inner lead 5 by molding only the wire bonding portion of the chip 3 and the lead frame 1 after wire bonding connecting the inner lead 5 to the inner lead 5. It is configured to be exposed and act as a heat dissipating surface.
이와 같이 구성된 본 고안의 작용은 다음과 같다.The operation of the present invention configured as described above is as follows.
반도체 패키지(6)가 실장된 상태에서 외부로부터 전기신호가 입력되면, 전기신호는 아웃 리드(7) 및 인너 리드(5)를 거쳐 와이어(8)를 통해 칩(3)으로 전달되어 칩(3)을 구동시키게 된다.When an electrical signal is input from the outside while the semiconductor package 6 is mounted, the electrical signal is transmitted to the chip 3 through the wire 8 via the out lead 7 and the inner lead 5, and the chip 3. ) Will be driven.
이에 따라, 칩(3)에서는 열이 발생하게 되며, 이 때 발생하는 열은 칩(3)의 본딩패드(4)와 인너 리드(5)를 연결하는 와이어(8)를 통해 아웃 리드(7)로 전달되어 방출되는 한편, 인너리칩(3) 및 칩(3)이 안착되는 패들(2)의 개방된 면을 통해 외부로 직접 방출된다.Accordingly, heat is generated in the chip 3, and the heat generated at this time is the out lead 7 through the wire 8 connecting the bonding pad 4 and the inner lead 5 of the chip 3. The inner chip 3 and the chip 3 are directly discharged to the outside through the open face of the paddle 2 on which the chip 3 is transferred.
즉, 본 고안의 반도체 패키지(6)는 칩(3)과 패들(2)의 와이어 본딩부를 제외한 전영역이 노출되어 있으므로 외부의 공기에 의해 효과적으로 냉각된다.That is, the semiconductor package 6 of the present invention is exposed to the entire area except the wire bonding portion of the chip 3 and the paddle 2 is effectively cooled by the outside air.
한편, 칩(3) 표면에는 외부로 노출되는 칩(3)을 보호하기 위한 산화막이나 질화막으로된 보호막(Passivation Layer)이 형성되어 있어서 칩(3) 표면이 공기중에 노출되더라도 칩(3)에 형성된 회로에는 영향을 미치지 않게 된다.On the other hand, a passivation layer made of an oxide film or a nitride film is formed on the surface of the chip 3 to protect the chip 3 exposed to the outside, so that the chip 3 is formed on the chip 3 even when the surface of the chip 3 is exposed to air. It will not affect the circuit.
또한, 본 고안은 칩(3) 몰딩 공정에서 칩(3) 전체를 감싸도록 몰딩하지 않고, 와이어 본딩된 부위만을 감싸도록 몰딩하므로 인해 몰딩수지(9)의 소요량을 절감하여 반도체 패키지(6)의 제조 원가를 절감할 수 있게 된다.In addition, the present invention is not molded to wrap the entire chip 3 in the molding process of the chip 3, and molding only to wrap the wire bonded portion, thereby reducing the amount of the molding resin 9 to reduce the amount of the semiconductor package 6. The manufacturing cost can be reduced.
이상에서와 같이, 본 고안은 반도체 패키지 공정시, 와이어 본딩 부위를 제외한 칩(3)의 전영역이 노출되도록 하여 반도체 패키지(6)의 열방출 성능을 향상시킴과 동시에 몰딩수지의 소요량을 줄일 수 있도록 한 매우 유용한 고안이다.As described above, the present invention improves heat dissipation performance of the semiconductor package 6 by reducing the required amount of molding resin by exposing the entire area of the chip 3 except for the wire bonding portion during the semiconductor package process. That's one very useful design.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960029048U KR19980015779U (en) | 1996-09-12 | 1996-09-12 | Heat dissipation structure of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960029048U KR19980015779U (en) | 1996-09-12 | 1996-09-12 | Heat dissipation structure of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980015779U true KR19980015779U (en) | 1998-06-25 |
Family
ID=53975825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019960029048U KR19980015779U (en) | 1996-09-12 | 1996-09-12 | Heat dissipation structure of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980015779U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100712894B1 (en) * | 2003-11-13 | 2007-05-02 | 페어차일드코리아반도체 주식회사 | Molded leadless package having improved reliability and high thermal transferability |
-
1996
- 1996-09-12 KR KR2019960029048U patent/KR19980015779U/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100712894B1 (en) * | 2003-11-13 | 2007-05-02 | 페어차일드코리아반도체 주식회사 | Molded leadless package having improved reliability and high thermal transferability |
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