KR20010063892A - Wafer level multi-chip package and the manufacturing method - Google Patents

Abstract

PURPOSE: A wafer-level multichip package is provided to easily cope with variation of coordinates of chip pads and variation of size of semiconductor chips, by using a wafer-level chip size package(CSP) process. CONSTITUTION: A plurality of the first chip pads(53) are formed on the first semiconductor chip(51). A plurality of the second chip pads(59) are formed on the second semiconductor chip(57) installed on the first semiconductor chip. A buffer layer(61) is formed on the first and second semiconductor chips. A plurality of bumps(67) are formed in the buffer layer, located in a position corresponding to the first and second chip pads. The first and second interconnections(63,65) electrically connects the first and second chip pads with the respective bumps, formed in the buffer layer to make the first and second chip pads correspond to the respective bumps. A solder ball(69) functions as an external terminal, adhered to the respective bumps.

Description

Wafer-level multichip package and its manufacturing method {WAFER LEVEL MULTI-CHIP PACKAGE AND THE MANUFACTURING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package in which an SRAM and a flash memory, which are commonly applied to a cellular phone, are stacked.

1 is a front cross-sectional view showing a structure of a multi-chip package according to the prior art. Referring to this, the conventional multi-chip package is installed on a substrate 1 and above the substrate 1, A first semiconductor chip 3 having a first chip pad 5 formed thereon, a second semiconductor chip 9 provided above the first semiconductor chip 3 and having a plurality of second chip pads 11 formed thereon; First and second gold wires 15 and 16 electrically connecting the inner substrate pad, the first chip pad 5, and the second chip pad 11 formed on the substrate 1, respectively, It is configured to include a plurality of solder balls 17 attached to the outer substrate pad of the substrate 1 formed to be connected to the substrate pad to serve as an external terminal.

Here, the first semiconductor chip 3 and the second semiconductor chip 9 are bonded to the upper side of the substrate 1 and the first semiconductor chip 3 by adhesives 7 and 13, respectively.

In addition, the upper portions of the first semiconductor chip 3 and the second semiconductor chip 9 and the bonding portions of the first and second gold wires 15 and 16 are sealed by a sealant 17. The sealant 17 serves to protect the first and second semiconductor chips 3 and 9 and the first and second gold wires 15 and 16 from external impact.

In order to manufacture the conventional multichip package configured as described above, first, the first semiconductor chip 3 is installed above the substrate 1, and then the first chip pad 5 of the first semiconductor chip 3 is installed. Wire bonding is performed on the inner substrate pad and the inner substrate pad, respectively, so that the first chip pad 5 and the inner substrate pad are electrically connected by the first gold wire 15.

When the first semiconductor chip 3 is installed on the substrate 1 as described above, the second semiconductor chip 9 is installed in the same manner as the second semiconductor chip 9 above the first semiconductor chip 3. The second chip pad 11 and the inner substrate pad are wire bonded to each other so that the second chip pad 11 and the inner substrate pad are electrically connected by the second gold wire 16.

In this case, the first semiconductor chip 3 and the second semiconductor chip 9 are bonded to the substrate 1 and the first semiconductor chip 3 by adhesives 7 and 13, respectively.

As described above, when the first semiconductor chip 3 and the second semiconductor chip 9 are electrically connected to the substrate 1 by the first and second gold wires 15 and 16, the first semiconductor chip 3 may be used. ) And the bonding portion of the first and second gold wires 15 and 16 and the upper side of the second semiconductor chip 9 are sealed with a sealant 17.

In this case, the sealant 17 serves to protect the first and second semiconductor chips 3 and 9 and the first and second gold wires 15 and 16 from external impact.

Thereafter, when the solder balls 19 are attached to the outer substrate pads of the substrate 1, the conventional multichip package is completed.

However, in the conventional multichip package as described above, in addition to the two semiconductor chips 3 and 9, a separate substrate 1 having a circuit pattern formed thereon for interconnection with each of the semiconductor chips 3 and 9 described above. There is a problem in that the substrate 1 is not compatible due to the change in the size of the semiconductor chips 3 and 9.

Therefore, in the conventional multichip package, when the size of the semiconductor chips 3 and 9 and the coordinates of the chip pads 5 and 11 are changed, an additional substrate 1 considering wire bonding is additionally required. Equipment investment in accordance with a separate package manufacturing process to cope with the size change of the chip (3) (9) is required, there was a problem that it is not easy to change the arrangement of the solder ball (19).

In addition, the conventional multi-chip package has a problem that the thermal characteristics of the package is not good because it is difficult to mount the heat sink for heat dissipation of the package.

The object of the present invention devised in view of the above-described problems is to apply a wafer-level chip size package (CSP) manufacturing process to easily respond to changes in the size of semiconductor chips and coordinates of chip pads In addition to simplifying the manufacturing process for manufacturing, the manufacturing cost is reduced, and the outer size and thickness of the package are reduced to reduce the thickness and thickness, and the electrical path is shortened. To provide a wafer-level multi-chip package and a method of manufacturing the same.

1 is a front sectional view showing the structure of a multichip package according to the prior art;

FIG. 2 is a perspective view of a portion of the wafer-level multichip package according to the present invention, in which a portion of the chip is exposed to be exposed;

3A to 3G are front cross-sectional views and their plan views sequentially showing a process of manufacturing a wafer-level multichip package according to the present invention;

Figure 4 is a front sectional view showing a state in which the wafer-level multi-chip package is mounted on a printed circuit board according to the present invention.

<Explanation of symbols for the main parts of the drawings>

51: first semiconductor chip 53: first chip pad

55: adhesive 57: second semiconductor chip

59: second chip pad 61: buffer layer

63: first wiring 65: second wiring

67: bump 69: solder ball

In order to achieve the object of the present invention as described above, the first semiconductor chip formed with a plurality of first chip pads, the second semiconductor chip provided on the upper side of the first semiconductor chip and formed with a plurality of second chip pads; A buffer layer formed on the first semiconductor chip and the second semiconductor chip, a plurality of bumps formed on the buffer layer so as to correspond to the first chip pad and the second chip pad, and the first chip pad and the second chip. First and second wirings formed in the buffer layer to electrically connect the chip pads and the respective bumps to electrically connect the bumps to the first chip pads and the second chip pads; A wafer level multichip package is provided, including a solder ball attached to and serving as an external terminal.

In addition, according to the present invention, there is provided a first process of installing a second semiconductor chip having a plurality of second chip pads formed on an upper side of a first semiconductor chip having a plurality of first chip pads, and the first semiconductor chip and the second semiconductor chip. Forming a buffer layer on an upper side of the semiconductor chip and forming wirings for rearrangement of the first chip pad and the second chip pad on the buffer layer; and through the wiring on the upper surface of the buffer layer, the first chip pad And a third process of forming a plurality of bumps electrically connected to the second chip pads, and then attaching solder balls to the respective bumps to serve as external terminals. A manufacturing method is provided.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a perspective view of a portion of the wafer-level multichip package according to the present invention, in which portions of the wafer are cut out to reveal the cross-section. FIGS. 4 is a front sectional view showing a state in which a wafer-level multichip package according to the present invention is mounted on a printed circuit board.

2 to 4, the wafer-level multichip package according to the present invention includes a first semiconductor chip 51 having a plurality of first chip pads 53 and the first semiconductor chip 51. ) And a second semiconductor chip 57 having a plurality of second chip pads 59 formed thereon, and a buffer layer 61 formed above the first semiconductor chip 51 and the second semiconductor chip 57. And a plurality of bumps (UBM: Under Bump Metallurgy) 67 having a metal material formed on the buffer layer 61 so as to correspond to the first chip pad 53 and the second chip pad 59. The first chip pads 53 and the second chip pads are formed in the buffer layer 61 to connect the first chip pads 53, the second chip pads 59, and the bumps 67 to correspond to each other. 59 and the first wiring 63 and the second wiring 65 of metal material electrically connecting the bumps 67 to each of the bumps 67 to serve as external terminals. Solder It consists of a ball 69.

Here, the second semiconductor chip 57 is bonded to the upper side of the first semiconductor chip 51 by an adhesive 55, and the adhesive 55 has a dry type film or a liquid paste such as a LOC tape. Used.

In addition, the buffer layer 61 is formed of an insulating material to prevent electrical interference between the first wiring 63 and the second wiring 65, and the first wiring 63 and the second wiring ( 65 and serves to protect the first semiconductor chip 51 and the second semiconductor chip 57 from external impact.

In addition, the buffer layer 61 has a function of alleviating thermal stress caused by a difference in thermal expansion coefficient between the first semiconductor chip 51 and the second semiconductor chip 57 when the package is mounted on the printed circuit board 70. Do also with.

A method of manufacturing a wafer-level multichip package according to the present invention for manufacturing a multichip package configured as described above will be described with reference to FIGS. 3A to 3G.

First, the adhesive 55 is applied to an upper surface of the first semiconductor chip 51 on which the plurality of first chip pads 53 are formed, and then the plurality of second chip pads 59 are formed on the adhesive 55. A second semiconductor chip 57 is attached to the second semiconductor chip 57 to be attached to the upper side of the first semiconductor chip 51.

In this case, a dry film or a liquid paste, such as a LOC tape, is typically used as the adhesive 55. In the case of using the liquid paste, a curing process for curing the paste is added.

Thereafter, a buffer layer 61 is formed on the first semiconductor chip 51 and the second semiconductor chip 57, and the first chip pad 53 and the second chip pad 59 are formed on the buffer layer 61. The first wiring 63 and the second wiring 65 for rearranging () are formed.

The process of forming the buffer layer 61 and the first and second wirings 63 and 65 will be described in more detail. First, the same height as that of the second semiconductor chip 57 is formed on the upper surface of the first semiconductor chip 51. After forming the primary buffer layer 61a by using a photoresist to remove the portion located on the upper side of the first chip pad 53 of the primary buffer layer (61a) by the first chip pad ( 53) Make sure the top of the cover is exposed.

Subsequently, a first wiring layer of a metal material is formed on the top surface of the first chip pad 53 and the first buffer layer 61a to a uniform thickness, and then partially removed according to a predetermined pattern through a lithography process. Thus, one end is connected to the first chip pad 53 and the other end is formed such that a plurality of primary wires 63a positioned on the upper surface of the primary buffer layer 61a are formed.

Subsequently, after forming the second buffer layer 61b on the upper surface of the second semiconductor chip 57 and the primary buffer layer 61a, the other end and the second end of the primary wiring 63a of the secondary buffer layer 61b are formed. The upper portion of the chip pad 59 is removed to expose the other end of the primary wiring 63a and the top surface of the second chip pad 59.

Thereafter, a second wiring layer of a metal material is formed on the other end of the first wiring 63a, the second chip pad 59, and the second buffer layer 61b to have a uniform thickness, and then, the lithography process is performed. The second wiring layer is partially removed according to a predetermined pattern so that one end thereof is connected to the other end of the primary wiring 63a or the second chip pad 59, and the other end thereof is located on the upper surface of the secondary buffer layer 61b. The difference wirings 63b and 65a are formed respectively.

Finally, after forming the tertiary buffer layer 61c on the upper surface of the secondary buffer layer 61b, the portion located above the other end of the secondary wirings 63b and 65a of the tertiary buffer layer 61c is removed. Thus, the other end surface of the secondary wirings 63b and 65a is exposed.

As a result, the buffer layer 61 including the first, second, and third buffer layers 61a, 61b, and 61c, the first chip pad 53 of the first semiconductor chip 51, and the corresponding buffer layer 61 are formed. A first wiring 63 composed of a primary wiring 63a and a part of a secondary wiring 63b for connecting the bumps 67, respectively, and a second chip pad 59 of the second semiconductor chip 57; And a second wiring 65 formed of the remaining secondary wiring 65a for connecting the bumps 67 corresponding thereto.

In this case, dividing the formation of the buffer layer 61 and the first and second wirings 63 and 65 in a plurality of times solves the step between the first semiconductor chip 51 and the second semiconductor chip 57. In order to maintain the thickness of the buffer layer 61 uniformly in this process, the thickness of the second semiconductor chip 57 is better.

In addition, the buffer layer 61 is formed of an insulating material to prevent electrical interference between the first wiring 63 and the second wiring 65, and the first wiring 63 and the second wiring ( 65) serves to serve as a base material for the formation of the substrate, and protects the first semiconductor chip 51 and the second semiconductor chip 57 from external impact and a package is mounted on the printed circuit board 70. The first semiconductor chip 51 and the second semiconductor chip 57 also play a role of mitigating thermal stress caused by the difference in thermal expansion coefficient.

When the buffer layer 61, the first wiring 63, and the second wiring 65 are formed as described above, the first and second wirings 63 and 65 are formed on the upper surface of the buffer layer 61. And a plurality of bumps 67 connected to the two chip pads 53 and 59, respectively.

That is, bumps 67 are formed on upper ends of the first and second wirings 63 and 65, respectively, so that the bumps 67 are formed through the first and second wirings 63 and 65. The first chip pad 53 and the second chip pad 59 are electrically connected to each other.

In this case, the bump 67 is formed to have the same pitch and diameter as the foot print of the printed circuit board 70 on which the package is mounted.

Thereafter, when the solder balls 69 serving as the external terminals are attached to the respective bumps 67, the package is completed.

When the package is completed as described above, as shown in FIG. 4, the package is mounted on the printed circuit board 70 by bonding the solder ball 69 to the land 71 of the printed circuit board 70 corresponding thereto. do.

On the other hand, in order to mass-produce the above-described multichip package of the present invention, another type of semiconductor chip for lamination is adhered to the surface of the wafer without dicing, and the buffer layer 61 and the first wiring 63 are attached. ), The second wiring 65, the bumps 67, and the solder balls 69 are formed in this order, and the above-described wafer may be diced to an appropriate size. At this time, the diced wafer becomes the first semiconductor chip 51, and the heterogeneous semiconductor chips adhered on the wafer become the second semiconductor chip 57.

As described above, in the wafer-level multichip package according to the present invention, the size of the semiconductor chips 51 and 57 and the chip pad 53 are applied by applying a wafer-level chip size package (CSP) manufacturing process. Easily correspond to the change of the coordinates of (59), as well as easy to adjust the pitch and diameter of the solder ball 69 according to the footprint of the printed circuit board, the mounting on the printed circuit board is easy, and the application range is expanded, In particular, there is an advantage that can easily correspond to a package for stacking a semiconductor chip of fine pitch.

In addition, since the present invention eliminates the need for a separate substrate for supporting the semiconductor chips 51 and 57 and a manufacturing process such as wire bonding and molding processes, the manufacturing process of the package is simplified, and the outer size and thickness of the package are reduced, thereby reducing the weight The material cost is greatly reduced due to the shortening and elimination of the substrate, which previously took up most of the raw material cost.

In addition, the present invention simplifies the electrical path by forming the wirings 63 and 65 for rearrangement of the chip pads 53 and 59, and at the same time, the back surface of the semiconductor chip 51 is exposed to the air so that the semiconductor chip 51 is exposed. Since heat dissipation is easy during operation of 57, the electrical and thermal characteristics of the package may be improved, thereby improving reliability of the package.

In addition, the present invention applies a FAB process to a manufacturing unit, which shortens the process period compared to conventional package fabrication, and in particular, enables stacking of semiconductor chips in a wafer state, and thus, at a wafer level, which has not been possible until now. This has the advantage of enabling multichip package implementations.

Claims (5)

A first semiconductor chip having a plurality of first chip pads formed thereon, a second semiconductor chip provided on an upper side of the first semiconductor chip formed thereon and having a plurality of second chip pads formed thereon, and an upper side of the first semiconductor chip and the second semiconductor chip formed thereon; A buffer layer formed on the buffer layer, a plurality of bumps formed on the buffer layer so as to correspond to the first chip pad and the second chip pad, and the first chip pad and the second chip pad and the respective bumps to correspond to each other. A first wire and a second wire formed on the buffer layer and electrically connecting the first chip pad and the second chip pad to the respective bumps, and solder balls attached to the respective bumps to serve as external terminals. Wafer-level multichip package, characterized in that. The wafer-level multichip package according to claim 1, wherein the second semiconductor chip is adhered to the upper side of the first semiconductor chip by an adhesive. A first process of installing a second semiconductor chip having a plurality of second chip pads formed on the first semiconductor chip having the plurality of first chip pads formed thereon; and a buffer layer on the first semiconductor chip and the second semiconductor chip And forming a wiring for repositioning the first chip pad and the second chip pad on the buffer layer and simultaneously forming the wiring on the first chip pad and the second chip pad through the wiring on the upper surface of the buffer layer. And forming a plurality of bumps electrically connected to each other and attaching a solder ball to each of the bumps to serve as an external terminal. 4. The method of claim 3, wherein in the first process, the second semiconductor chip is adhered to the upper side of the first semiconductor chip by an adhesive. 4. The method of claim 3, wherein the second process comprises forming a first buffer layer on the top surface of the first semiconductor chip at the same height as the second semiconductor chip and then exposing the top surface of the first chip pad to expose the first buffer layer. The first step of removing the upper portion of the first chip pad, and the plurality of primary wires are respectively connected so that one end is connected to the first chip pad exposed the upper surface in the first step and the other end is located on the upper surface of the primary buffer layer. Forming a second buffer layer on an upper surface of the second semiconductor chip and the primary buffer layer, and then forming a second buffer layer so that the other end of the primary wiring and the upper surface of the second chip pad are exposed. A third step of removing the other end of the wiring and the upper portion of the second chip pad, and one end of the second wire and the other end of the first wiring with the upper surface exposed in the third step, and the other end of the second buffer layer Each of the plurality of secondary wires is positioned so A fourth step of forming and a fifth step of forming a third buffer layer on the upper surface of the secondary buffer layer, and then removing the other end upper portion of the secondary wiring of the tertiary buffer layer so that the other end surface of the secondary wiring is exposed. Wafer level multi-chip package manufacturing method characterized in that consisting of.