KR102676772B1 - Light-emitting device - Google Patents

Abstract

The light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A first bonding pad located on the semiconductor stack; a second bonding pad located on the semiconductor stack, spaced apart from the first bonding pad, and defining an area located between the first bonding pad and the second bonding pad on the semiconductor stack; and a plurality of hole portions penetrating the active layer to expose the first semiconductor layer, wherein, in a plan view of the light emitting device, the first bonding pad and the second bonding pad are formed in areas other than the plurality of hole portions.

Description

Light-emitting device {LIGHT-EMITTING DEVICE}

The present invention relates to a light emitting device, and particularly to a light emitting device including a semiconductor stack and a bonding pad located on the semiconductor stack.

Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting device, and its advantages include low power consumption, low heat energy generated, long operating life, vibration resistance, small volume, and fast response speed. It has good photoelectric properties (eg, stable emission wavelength). Therefore, light emitting diodes are widely used in home appliances, facility indicator lights, and photoelectric products.

The light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A first bonding pad located on the semiconductor stack; a second bonding pad located on the semiconductor stack; It includes a plurality of holes penetrating the active layer to expose the first semiconductor layer, wherein the first bonding pad and the second bonding pad are spaced apart from each other and are located between the first bonding pad and the second bonding pad on the semiconductor stack. defines an area located in , and on the plan view of the light emitting device, the first bonding pad and the second bonding pad are formed in areas other than the positions of the plurality of holes.

The light emitting device includes a semiconductor stack, a first contact layer, a second contact layer, a first bonding pad, and a second bonding pad, and the semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and a first semiconductor layer and a second bonding pad. It includes an active layer located between semiconductor layers, wherein the first contact layer is located on a second semiconductor layer and surrounds a side wall of the second semiconductor layer and is connected to the first semiconductor layer, wherein the second contact layer is connected to the first semiconductor layer. 2 is located on the semiconductor layer and connected to the second semiconductor layer, the first bonding pad is located on the semiconductor layer and connected to the first contact layer, and the second bonding pad is located on the semiconductor layer and connected to the second contact layer. , the first bonding pad and the second bonding pad are spaced apart from each other and define an area located between the first bonding pad and the second bonding pad on the semiconductor stack, and on the top view of the light emitting device, on the second semiconductor layer. The first contact layer located at surrounds the second contact layer.

The light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A first bonding pad electrically connected to the first semiconductor layer; a second bonding pad electrically connected to the second semiconductor layer; and a metal layer located on the semiconductor stack, surrounding a plurality of side walls of the second bonding pad, and being spaced apart from the second bonding pad.

The light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A first contact layer located on the semiconductor stack; a first bonding pad located on the first contact layer and including a side edge; a second bonding pad located on the semiconductor stack; An insulating layer including a first portion covered by the first bonding pad and a connecting portion adjacent to a side of the first bonding pad, wherein the insulating layer is formed between the first portion and the connecting portion to expose the first contact layer. It includes an opening located between the first side of the first part and the side of the connection part, and the side of the first bonding pad is more than 100 μm from the first side of the first part or the side of the connection part. They are separated by a small distance.

1A to 7C are diagrams showing a method of manufacturing the light emitting device 1 or light emitting device 2 disclosed in one embodiment of the present invention.
Figure 8 is a plan view of the light emitting device 1 disclosed in one embodiment of the present invention.
Figure 9a is a cross-sectional view of the light emitting device 1 disclosed in one embodiment of the present invention.
Figure 9b is a cross-sectional view of the light emitting device 1 disclosed in one embodiment of the present invention.
Figure 10 is a plan view of the light emitting device 2 disclosed in one embodiment of the present invention.
Figure 11a is a cross-sectional view of the light emitting device 2 disclosed in one embodiment of the present invention.
Figure 11b is a cross-sectional view of the light emitting device 2 disclosed in one embodiment of the present invention.
12A to 18B are diagrams showing a method of manufacturing the light emitting device 3 or 4 disclosed in one embodiment of the present invention.
Figure 19 is a plan view of the light emitting device 3 disclosed in one embodiment of the present invention.
Figure 20 is a cross-sectional view of the light emitting device 3 disclosed in one embodiment of the present invention.
Figure 21 is a plan view of the light emitting device 4 disclosed in one embodiment of the present invention.
Figure 22 is a cross-sectional view of the light emitting device 4 disclosed in one embodiment of the present invention.
Figure 23 is a cross-sectional view of the light emitting device 5 disclosed in one embodiment of the present invention.
Figure 24 is a cross-sectional view of the light emitting device 6 disclosed in one embodiment of the present invention.
Figures 25 to 33b are diagrams showing the manufacturing method and structure of the light emitting device 7 disclosed in one embodiment of the present invention.
Figure 34a is a plan view of the light emitting device 8 disclosed in one embodiment of the present invention.
Figure 34b is a cross-sectional view of the light emitting device 8 disclosed in one embodiment of the present invention.
Figure 35 is a structural schematic diagram of a light emitting device according to an embodiment of the present invention.
Figure 36 is a structural schematic diagram of a light emitting device according to an embodiment of the present invention.

To make the description of the present invention more detailed and complete, please combine the relevant drawings with reference to the description of the embodiments below. However, the examples below are only for illustrating the light emitting device of the present invention and are not intended to limit the present invention. In addition, the size, material, shape, relative arrangement, etc. of the component parts described in the examples of this specification do not limit the scope of the present invention, unless specifically limited, but are merely explanations. Additionally, the sizes and positional relationships of members shown in each drawing may be exaggerated to make the explanation clearer. In addition, in the description below, parts that are the same or have the same properties are indicated using the same names and symbols in order to appropriately omit detailed description.

1A to 11B are diagrams showing a method of manufacturing the light emitting device 1 or light emitting device 2 disclosed in one embodiment of the present invention.

As shown in FIG. 1B, which is a plan view of FIG. 1A and a cross-sectional view taken along line A-A' of FIG. 1A, the method of manufacturing the light emitting device 1 or the light emitting device 2 includes a platform forming step, and the platform forming step The steps include providing a substrate 11a; and forming a semiconductor stack (10a) on the substrate (11a), wherein the semiconductor stack (10a) includes a first semiconductor layer (101a), a second semiconductor layer (102a), and a first semiconductor layer (101a). and an active layer 103a located between the second semiconductor layer 102a. The semiconductor stack 10a is patterned using lithography or etching to partially remove the second semiconductor layer 102a and the active layer 103a to form one or more semiconductor structures 1000a; And a surrounding portion 111a surrounding one or more semiconductor structures 1000a may be formed. The surrounding portion 111a exposes the first surface 1011a of the first semiconductor layer 101a. The one or more semiconductor structures 1000a each include one first outer wall 1003a, a second outer wall 1001a, and one inner wall 1002a, and the first outer wall 1003a includes a first semiconductor layer 101a. The second outer wall 1001a is the sidewall of the active layer 103a and/or the second semiconductor layer 102a, and one end of the second outer wall 1001a is the surface 102s of the second semiconductor layer 102a. is connected to, the other end of the second outer wall 1001a is connected to the first surface 1011a of the first semiconductor layer 101a, and one end of the inner wall 1002a is connected to the surface 102s of the second semiconductor layer 102a. ), the other end of the inner wall 1002a is connected to the second surface 1012a of the first semiconductor layer 101a, and the plurality of semiconductor structures 1000a are connected to each other by the first semiconductor layer 101a. do. As shown in FIG. 1B, the inner wall 1002a of the semiconductor structure 1000a and the second surface 1012a of the first semiconductor layer 101a form an obtuse angle, and the first outer wall 1003a of the semiconductor structure 1000a The surface 11s of the substrate 11a forms an obtuse angle or a right angle, and the second outer wall 1001a of the semiconductor structure 1000a and the first surface 1011a of the first semiconductor layer 101a form an obtuse angle. The surrounding portion 111a surrounds the semiconductor structure 1000a, and the surrounding portion 111a is rectangular or polygonal in a plan view of the light emitting device 1 or 2.

In one embodiment of the present invention, light emitting device 1 or light emitting device 2 has a side length of less than 30 mil. When an external current is injected into the light-emitting device 1 or the light-emitting device 2, the surrounding portion 111a surrounds the semiconductor structure 1000a, so that the light-emitting device 1 or the light-emitting device 2 The light field distribution can be made uniform and the forward voltage of the light emitting device can be reduced.

In one embodiment of the present invention, light emitting device 1 or light emitting device 2 has a side length greater than 30 mil. The semiconductor stack 10a is patterned using lithography or etching to partially remove the second semiconductor layer 102a and the active layer 103a, thereby forming one or more holes penetrating the second semiconductor layer 102a and the active layer 103a. 100a is formed, and one or more hole portions 100a expose one or more second surfaces 1012a of the first semiconductor layer 101a. When an external current is injected into the light emitting device 1 or the light emitting device 2, the light of the light emitting device 1 or the light emitting device 2 is activated by the distributed arrangement of the surrounding portion 111a and the plurality of hole portions 100a. The field distribution can be made uniform and the forward voltage of the light emitting device can be reduced.

In one embodiment of the present invention, the light emitting device 1 or 2 has a side length of less than 30 mil, and the light emitting device 1 or 2 is used to increase the light emitting area of the active layer. It may not include the hole portion 100a.

In one embodiment of the present invention, the opening shape of the one or more hole portions 100a includes a circular shape, an oval shape, a rectangular shape, a polygonal shape, or an arbitrary shape. The plurality of hole parts 100a may be arranged in a plurality of rows, and the hole parts 100a in two adjacent rows may be arranged side by side or offset from each other.

In one embodiment of the present invention, the substrate 11a is a gallium arsenide (GaAs) wafer on which aluminum gallium indium phosphorus (AlGaInP) is grown, a sapphire (Al2O3) wafer on which insulium gallium nitrogen (InGaN) is grown, or a gallium nitride (GaN) wafer. ) It may be a growth substrate containing a wafer or a silicon carbide (SiC) wafer. Here, light-emitting lamination, etc. is performed on the substrate 11a using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxial method (MBE), hydride vapor deposition (HVPE), evaporation method, or ion plating method. A semiconductor stack 10a having photoelectric properties can be formed.

In one embodiment of the present invention, the first semiconductor layer 101a and the second semiconductor layer 102a are, for example, a cladding layer or a confinement layer, and both have different conductivity types and electrical properties. Electrons or holes can be provided depending on the quality, polarity, or doped elements. For example, the first semiconductor layer 101a is a semiconductor with n-type electrical characteristics, and the second semiconductor layer 102a is a semiconductor with p-type electrical characteristics. It is a semiconductor. The active layer 103a is formed between the first semiconductor layer 101a and the second semiconductor layer 102a, and electrons and holes are recombined in the active layer 103a under the driving of current, converting electrical energy into light energy and producing light. emits. The wavelength of light emitted by the light emitting device 1 or 2 is adjusted by changing the physical and chemical composition of a single or multilayer of the semiconductor stack 10a. The material of the semiconductor stack 10a includes a group III-V semiconductor material, for example, AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0x,y1; It is (x+y)1. Depending on the material of the active layer 103a, if the material of the semiconductor layer 10a is an AlInGaP-based material, red light with a wavelength of 610 nm to 650 nm and green light with a wavelength of 530 nm to 570 nm can be emitted, and the semiconductor layer If the material of (10a) is an InGaN-based material, it can emit blue light with a wavelength of 450 nm to 490 nm, and if the material of the semiconductor layer (10a) is an AlGaN-based material, it can emit blue light with a wavelength of 400 nm to 250 nm. Can emit external light. The active layer 103a has a single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), and multi-quantum well (MQW). ) can be. The material of the active layer 103a may be a semiconductor with neutral, p-type, or n-type electrical characteristics.

Following the platform forming step, the method of manufacturing the light-emitting device 1 or the light-emitting device 2 includes forming a first insulating layer, as shown in the plan view of FIG. 2A and the cross-sectional view taken along the line A-A' in FIG. Including the formation stage. The first insulating layer 20a may be formed on the semiconductor structure 1000a by evaporation or deposition, and may be formed on the first surface 1011a and the hole portion (1011a) of the surrounding portion 111a. lithography to cover the second surface 1012a of the semiconductor structure 1000a, the second outer wall 1001a and the inner wall 1002a of the active layer 103a, It is patterned by etching, and the first insulating layer 20a covers the first surface 1011a of the first semiconductor layer 101a located in the surrounding portion 111a. A first insulating layer surrounding area (200a) covering; a first group of first insulating layer cover areas 201a covering the hole portion 100a to cover the second surface 1012a of the first semiconductor layer 101a located in the hole portion 100a; and a second group of first insulating layer openings 202 exposing the surface 102s of the second semiconductor layer 102a. The first insulating layer cover areas 201a of the first group are separated from each other and each corresponds to a plurality of hole portions 100a. The first insulating layer 20a may have a single-layer or multi-layer structure. When the first insulating layer 20a is a single-layer film, the first insulating layer 20a can protect the sidewall of the semiconductor structure 1000a and prevent the active layer 103a from being damaged in a subsequent manufacturing process. When the first insulating layer 20a is a multilayer film, the first insulating layer 20a is made by alternately stacking two or more materials with different refractive indices to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The first insulating layer 20a is formed of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin, cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, the method of manufacturing the light-emitting device 1 or the light-emitting device 2 following the first insulating layer forming step is as shown in FIG. 3A and a cross-sectional view taken along line A-A' in FIG. 3A. As shown in 3b, it includes a transparent conductive layer forming step. The transparent conductive layer 30a may be formed in the first insulating layer opening 202a of the second group by evaporation or deposition, and the outer edge 301a of the transparent conductive layer 30a and the first insulating layer 20a are spaced apart from each other to expose the surface 102s of the second semiconductor layer 102a. Since the transparent conductive layer 30a is formed on almost the entire surface of the second semiconductor layer 102a and is in contact with the second semiconductor layer 102a, the transparent conductive layer 30a allows the current to flow through the entire surface of the second semiconductor layer 102a. It can be spread evenly. The material of the transparent conductive layer 30a includes a material that is transparent to the light emitted by the active layer 103a, and the transparent material is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the platform forming step, the transparent conductive layer forming step may be performed first, and then the first insulating layer forming step may be performed.

In another embodiment of the present invention, after the platform forming step, the forming step of the first insulating layer may be omitted and the transparent conductive layer forming step may be performed directly.

In one embodiment of the present invention, the method of manufacturing the light-emitting device 1 or the light-emitting device 2 following the transparent conductive layer forming step includes the plan view of FIG. 4A and the cross-sectional view taken along line A-A' of FIG. 4A in FIG. 4B. As shown, it includes a reflective structure forming step. The reflective structure includes a reflective layer 40a and/or a barrier layer 41a, and may be formed directly on the transparent conductive layer 30a by evaporation or deposition, and the reflective layer 40a is the transparent conductive layer 30a. and the barrier layer 41a. On the top view of the light-emitting device 1 or the light-emitting device 2, the outer edge 401a of the reflective layer 40a is provided inside or outside the outer edge 301a of the transparent conductive layer 30a, or the outer edge 401a of the transparent conductive layer 30a ) may be installed overlapping and aligned with the outer edge 301a of the barrier layer 41a, and the outer edge 411a of the barrier layer 41a may be installed inside or outside the outer edge 401a of the reflective layer 40a, or on the outer edge of the reflective layer 40a. It can be installed aligned and overlapping with (401a).

In another embodiment of the present invention, the forming step of the transparent conductive layer may be omitted, and the reflective structure forming step may be performed directly after the platform forming step or the first insulating layer forming step. For example, the reflective layer 40a and/or the barrier layer 41a are formed directly on the second semiconductor layer 102a, and the reflective layer 40a is located between the second semiconductor layer 102a and the barrier layer 41a.

The reflective layer 40a may have a single-layer or multi-layer structure, and the multi-layer structure is, for example, a Bragg reflective structure. The material of the reflective layer 40a includes a metal material with a relatively high reflectivity, and the metal material is, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy thereof. Here, having a relatively high reflectance means having a reflectance of 80% or more for the wavelength of the light emitted by the light-emitting device 1 or 2. In one embodiment of the present invention, the barrier layer 41a covers the reflective layer 40a to prevent the surface of the reflective layer 40a from being oxidized and the reflectivity of the reflective layer 40a to deteriorate. The material of the barrier layer 41a includes metal, and the metal material includes, for example, titanium (Ti), wolfram (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), and platinum ( It is a metal such as Pt) or an alloy thereof. The barrier layer 41a may have a single-layer or multi-layer structure, and the multi-layer structure is, for example, titanium (Ti)/aluminum (Al) and/or titanium (Ti)/wolfram (W). In one embodiment of the present invention, the barrier layer 41a includes a laminate structure of titanium (Ti)/aluminum (Al) on one side away from the reflective layer 40a and titanium (Ti) on one side close to the reflective layer 40a. /Includes a layered structure of wolfram (W). In one embodiment of the present invention, the material of the reflective layer 40a and the barrier layer 41a preferably includes a metal material other than gold or copper (Cu).

In one embodiment of the present invention, the method of manufacturing the light-emitting device 1 or the light-emitting device 2 following the step of forming the reflective structure includes the plan view of FIG. 5A, the cross-sectional view along line AA' of FIG. 5A, and FIGS. 5B and 5A. As shown in FIG. 5C, which is a cross-sectional view taken along line B-B', a second insulating layer forming step is included. The second insulating layer 50a is formed on the semiconductor structure 1000a by evaporation or deposition, and a first group of second insulating layer openings 501a are formed to expose the first semiconductor layer 101a. and patterned by lithography and etching to form a second group of second insulating layer openings 502a to expose the reflective layer 40a or barrier layer 41a, and the second insulating layer 50a In the patterning process, the first insulating layer surrounding area 200a covered in the surrounding portion 111a in the above-described first insulating layer forming step and the first group of first insulating layer covering areas 201a in the hole portion 100a ) is partially etched and removed to expose the first semiconductor layer 101a, and a first group of first insulating layer openings 203a are formed in the hole portion 100a to expose the first semiconductor layer 101a. In this embodiment, on the cross-sectional view of the light-emitting element 1 or the light-emitting element 2, as shown in FIG. 5B, a first group of second insulating layer openings 501a and a second group of second insulating layer openings (502a) has different widths and numbers. The opening shapes of the first group of second insulating layer openings 501a and the second group of second insulating layer openings 502a include circular, oval, rectangular, polygonal, or arbitrary shapes. In this embodiment, as shown in FIG. 5A, the first group of second insulating layer openings 501a are separated from each other and arranged in a plurality of rows, respectively, forming a plurality of hole portions 100a and the first group of first insulating layer openings 501a. Corresponding to the layer opening 203a, the second insulating layer openings 502a of the second group are all close to one side of the substrate 11a, for example, to the left or right of the center line of the substrate 11a, and the second insulating layer openings 502a of the second group are all close to the left or right side of the center line of the substrate 11a. The insulating layer opening 502a is located between the second insulating layer openings 501a of the first group of two adjacent rows, separated from each other. The second insulating layer 50a may have a single-layer or multi-layer structure. When the second insulating layer 50a is a single-layer film, the second insulating layer 50a can protect the sidewall of the semiconductor structure 1000a and prevent the active layer 103a from being damaged in a subsequent manufacturing process. When the second insulating layer 50a is a multilayer film, the second insulating layer 50a is made by alternately stacking two or more materials with different refractive indices to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The second insulating layer 50a is formed of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin, cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, the method of manufacturing the light-emitting device 1 or the light-emitting device 2 following the second insulating layer forming step includes the plan view of FIG. 6A and the cross-sectional view of FIG. 6B along line A-A' of FIG. 6A. and a contact layer forming step, as shown in FIG. 6C, which is a cross-sectional view taken along line B-B' in FIG. 6A. The contact layer 60a may be formed on the first semiconductor layer 101a and the second semiconductor layer 102a by evaporation or deposition, and may be formed on the second insulating layer opening 502a of the second group. The above contact layer opening 602a is formed to expose the reflective layer 40a or barrier layer 41a and the fin area 600a is defined in the geometric center of the light emitting device 1 or light emitting device 2 by lithography and etching. It is patterned by the method of. On the cross-sectional view of the light emitting element 1 or the light emitting element 2, the width of the contact layer opening 602a is larger than the width of any one of the second insulating layer openings 502a of the second group. On the top view of the light emitting device 1 or the light emitting device 2, the plurality of contact layer openings 602a are all close to one side of the substrate 11a, for example, to the left or right of the center line of the substrate 11a. The contact layer 60a may have a single-layer or multi-layer structure. In order to reduce the electrical resistance in contact with the first semiconductor layer 101a, the material of the contact layer 60a includes a metal material, such as chromium (Cr), titanium (Ti), and wolfram (W). , gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or alloys thereof. In one embodiment of the present invention, the contact layer 60a is preferably made of a metal other than gold (Au) or copper (Cu). In one embodiment of the present invention, the material of the contact layer 60a preferably includes a metal with high reflectivity, such as aluminum (Al) or platinum (Pt). In one embodiment of the present invention, one side of the contact layer 60a in contact with the first semiconductor layer 101a is chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101a. It is desirable to include.

In one embodiment of the present invention, the contact layer 60a covers all of the hole portions 100a and is extended to cover the second semiconductor layer 102a, and the contact layer 60a covers the second insulating layer 50a. It is insulated from the second semiconductor layer 102a through, and the contact layer 60a is in contact with the first semiconductor layer 101a through the hole portion 100a. When an external current is injected into the light emitting device 1 or 2, the current is conducted to the first semiconductor layer 101a through the plurality of hole portions 100a. In this embodiment, there is a first shortest distance between two adjacent hole portions 100a located on the same column, and any hole portion 100a adjacent to the edge of the light emitting device and the first shortest distance between the first semiconductor layer 101a There is a second shortest distance between the outer walls 1003a, and the first shortest distance is greater than the second shortest distance.

In another embodiment of the present invention, the contact layer 60a covers the surrounding portion 111a and the hole portion 100a, and is also extended to cover the second semiconductor layer 102a, and the contact layer 60a is It is insulated from the second semiconductor layer 102a through the second insulating layer 50a, and the contact layer 60a contacts the first semiconductor layer 101a through the surrounding portion 111a and the hole portion 100a. When an external current is injected into the light emitting device 1 or the light emitting device 2, some of the current is conducted to the first semiconductor layer 101a by the surrounding portion 111a, and the other current is conducted through the plurality of hole portions 100a. It conducts to the first semiconductor layer 101a. In this embodiment, there is a first shortest distance between two adjacent hole portions 100a located on the same column, and any hole portion 100a adjacent to the edge of the light emitting device and the first shortest distance of the first semiconductor layer 101a There is a second shortest distance between the outer walls 1003a, and the first shortest distance is equal to or smaller than the second shortest distance.

In another embodiment of the present invention, a plurality of hole parts 100a may be arranged in a first row and a second row, and a first shortest distance is formed between two adjacent hole parts 100a located on the same row, and a second shortest distance is provided. There is a second shortest distance between the hole part 100a in the first row and the hole part 100a located in the second row, and the first shortest distance is greater or smaller than the second shortest distance.

In one embodiment of the present invention, the plurality of hole parts 100a may be arranged in a first row, a second row, and a third row, and between the hole parts 100a on the first row and the hole parts 100a on the second row are There is a first shortest distance between the hole part 100a located on the second row and the hole part 100a located on the third row, and the first shortest distance is smaller than the second shortest distance.

In one embodiment of the present invention, the method of manufacturing the light emitting device 1 or the light emitting device 2 following the contact layer forming step as shown in FIGS. 6A, 6B, and 6C includes a third insulating layer forming step. And, as shown in the top view of FIG. 7A, FIG. 7B which is a cross-sectional view along line A-A' of FIG. 7A, and FIG. 7C which is a cross-sectional view along line B-B' of FIG. 7A, the third insulating layer 70a is It may be formed on the semiconductor structure 1000a by evaporation or deposition, and a first group of third insulating layer openings may be formed on the contact layer 60a to expose the contact layer 60a shown in FIG. 6A. 701a), and to form a second group of third insulating layer openings 702a on the one or more contact layer openings 602a to expose the reflective layer 40a or barrier layer 41a shown in FIG. 6A. , the contact layer 60a, which is patterned by a method of lithography and etching and located on the second semiconductor layer 102a, is interposed between the second insulating layer 50a and the third insulating layer 70a, and The third insulating layer openings 701a of the first group and the second insulating layer openings 501a of the first group are offset and do not overlap each other. The above-described fin area 600a is surrounded and covered by a third insulating layer. In this embodiment, as shown in FIG. 7A, the first group of third insulating layer openings 701a are separated from each other and are misaligned with the plurality of hole portions 100a. The second group of third insulating layer openings 702a are separated from each other and each corresponds to a plurality of contact layer openings 602a. In the top view of FIG. 7A, the first group of third insulating layer openings 701a are close to one side, for example, the right side, of the substrate 11a, and the second group of third insulating layer openings 702a are adjacent to the substrate 11a. The other side, for example, is close to the left side of the center line of the substrate 11a. On the cross-sectional view of the light-emitting element 1 or the light-emitting element 2, the width of the third insulating layer opening 702a of any one second group is smaller than the width of any one contact layer opening 602a, and 3 The insulating layer 70a is filled according to the contact layer opening 602a and covers the side wall of the contact layer opening 602a, exposing the reflective layer 40a or the barrier layer 41a, thereby forming a third insulating layer of the second group. Constructs an opening 702a. The third insulating layer 70a may have a single-layer or multi-layer structure. When the third insulating layer 70a is a multilayer film, the third insulating layer 70a is made by alternately stacking two or more materials with different refractive indexes to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The third insulating layer 70a is formed of a non-conductive material, and is made of Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, and cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

Following the third insulating layer forming step, the method of manufacturing the light emitting device 1 or 2 includes a bonding pad forming step. As shown in the plan view of FIG. 8, the first bonding pad 80a and the second bonding pad 90a may be formed on one or more semiconductor structures 1000a by electroplating, evaporation, or deposition, and It is patterned by lithography and etching methods. In the plan view of FIG. 8, the first bonding pad 80a is close to one side of the center line of the substrate 11a, for example, to the right, and the second bonding pad 90a is close to the other side, for example, to the left, of the center line of the substrate 11a. The first bonding pad 80a covers all of the third insulating layer openings 701a of the first group so as to contact the contact layer 60a, and also covers the first semiconductor layer through the contact layer 60a and the hole portion 100a. Forms an electrical connection with (101a). The second bonding pad 90a covers all the third insulating layer openings 702a of the second group and is in contact with the reflective layer 40a or the barrier layer 41a, and also covers the reflective layer 40a or the barrier layer 41a. An electrical connection is formed with the second semiconductor layer 102a. The first bonding pad 80a includes one or more first bonding pad openings 800a, a first side 802a, and a plurality of pieces extending from the first side 802a in a direction away from the second bonding pad 90a. It includes a first recess 804a. The second bonding pad 90a includes one or more second bonding pad openings 900a, a second side side 902a, and a plurality of pieces extending from the second side side 902a in a direction away from the first bonding pad 80a. It includes a second concave portion 904a. The position of the first bonding pad opening 800a and the second bonding pad opening 900a substantially correspond to the position of the hole portion 100a, and the position of the first concave portion 804a and the second concave portion 904a The position of almost corresponds to the position of the hole portion 100a. In other words, the first bonding pad 80a and the second bonding pad 90a do not cover any of the holes 100a, and the first bonding pad 80a and the second bonding pad 90a cover the hole 100a. By being formed around the hole portion 100a, the first bonding pad opening 800a or the second bonding pad opening 900a has a diameter larger than that of any hole portion 100a, and is formed in the first concave portion 804a or The second concave portion 904a has a width greater than the diameter of any of the hole portions 100a. In one embodiment of the present invention, the plurality of first recesses 804a are substantially aligned with the plurality of second recesses 904a in a plan view. In another embodiment of the present invention, the plurality of first recesses 804a are arranged to be offset from the plurality of second recesses 904a in the plan view. In one embodiment of the present invention, on the top view of the light emitting device 1 or 2, the shape of the first bonding pad 80a is the same as or different from the shape of the second bonding pad 90a.

FIG. 9A is a cross-sectional view taken along line A-A' of FIG. 8, and FIG. 9B is a cross-sectional view taken along line B-B' of FIG. 8. The light emitting device 1 disclosed in this embodiment is a flip chip type light emitting diode device. The light emitting device 1 includes a substrate 11a; One or more semiconductor structures 1000a located on a substrate 11a; A surrounding portion 111a surrounding one or more semiconductor structures 1000a; and a first bonding pad 80a and a second bonding pad 90a located on the semiconductor stack 10a. Each of the one or more semiconductor structures 1000a includes a semiconductor stack 10a, and the semiconductor stack 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, and a first semiconductor layer 101a and a second semiconductor layer 102a. It includes an active layer (103a) located between the semiconductor layers (102a). A plurality of semiconductor structures 1000a are connected to each other by the first semiconductor layer 101a. As shown in FIGS. 8, 9A, and 9B, the second semiconductor layer 102a and the active layer 103a around one or more semiconductor structures 1000a are removed to form a first surface of the first semiconductor layer 101a ( 1011a) is exposed. In other words, the surrounding portion 111a includes the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000a.

The light emitting device 1 includes one or more holes 100a penetrating the second semiconductor layer 102a and the active layer 103a to expose one or more second surfaces 1012a of the first semiconductor layer 101a; and is formed on the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000a and contact the first semiconductor layer 101a to form an electrical connection, and also forms an electrical connection with the first semiconductor layer 101a. It further includes a contact layer (60a) formed on one or more second surfaces (1012a) of the layer (101a) and covering one or more hole portions (100a) and contacting the first semiconductor layer (101a) to form an electrical connection. do. In this embodiment, on the top view of the light emitting device 1, the contact layer 60a has a total surface area greater than the total surface area of the active layer 103a, or the contact layer 60a has a total surface area greater than the length of the outer side of the active layer 103a. It has a large outer side length.

In one embodiment of the present invention, the first bonding pad 80a and/or the second bonding pad 90a cover a plurality of semiconductor structures 1000a.

In one embodiment of the present invention, the first bonding pad 80a includes one or more first bonding pad openings 800a, and the second bonding pad 90a includes one or more second bonding pad openings 900a. do. The formation position of the first bonding pad 80a and the second bonding pad 90a avoids the formation position of the hole portion 100a, so that the first bonding pad opening 800a and the second bonding pad opening 900a are formed. The position is made to overlap with the formation position of the hole portion 100a.

In one embodiment of the present invention, on the top view of the light emitting device 1, the shape of the first bonding pad 80a is the same as the shape of the second bonding pad 90a, for example, the first bonding pad 80a and the second bonding pad 80a. 2 The shape of the bonding pad 90a is a comb shape, and as shown in FIG. 8, the first bonding pad 80a is formed in an area other than the location of the plurality of hole portions 100a. The radius of curvature of the first bonding pad opening 800a and the radius of curvature of the first concave portion 804a are each larger than the radius of curvature of the hole portion 100a. The radius of curvature of the second bonding pad opening 900a and the curvature of the second concave portion 904a of the second bonding pad 90a so that the second bonding pad 90a is formed in an area other than the location of the plurality of holes 100a. The radius is larger than the radius of curvature of each hole portion 100a.

In one embodiment of the present invention, on the top view of the light emitting device 1, the shape of the first bonding pad 80a and the shape of the second bonding pad 90a are different. For example, when the shape of the first bonding pad 80a is rectangular and the shape of the second bonding pad 90a is comb-shaped, the first bonding pad 80a has a plurality of hole portions 100a. It includes a first bonding pad opening 800a so that it is formed in an area other than the plurality of hole portions 100a, and the second bonding pad 90a has a second concave portion so that the second bonding pad 90a is formed in an area other than the plurality of hole portions 100a. It includes 904a or includes both the second recess 904a and the second bonding pad opening 900a.

In one embodiment of the present invention, the size of the first bonding pad 80a and the size of the second bonding pad 90a are different, for example, the area of the first bonding pad 80a is greater than that of the second bonding pad 90a. It is bigger than the area. The first bonding pad 80a and the second bonding pad 90a may have a single-layer or multi-layer structure containing a metal material. The material of the first bonding pad 80a and the second bonding pad 90a includes metal, and the metal material is, for example, chromium (Cr), titanium (Ti), wolfram (W), aluminum (Al), and indium ( It is a metal such as In), tin (Sn), nickel (Ni), and platinum (Pt) or an alloy thereof. When the first bonding pad 80a and the second bonding pad 90a have a multi-layer structure, the first bonding pad 80a includes a first upper layer bonding pad 805a and a first lower layer bonding pad 807a, The second bonding pad 90a includes a second upper layer bonding pad 905a and a second lower layer bonding pad 907a. The upper layer bonding pad and the lower layer bonding pad each have different functions. The function of the upper layer bonding pad is mainly to weld and form lead lines. By means of the upper bonding pad, the light emitting device 1 is mounted on the package substrate using solder or Au-Sn eutectic bonding in a flip chip format. The specific metal materials of the upper bonding pad are nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), wolfram (W), zirconium (Zr), and molybdenum ( Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), etc. High ductility Includes materials of The upper bonding pad may be a single layer, alloy, or multilayer film of the above material. In one embodiment of the present invention, the material of the upper bonding pad preferably includes nickel (Ni) and/or gold (Au), and the upper bonding pad is a single layer or a multilayer. The function of the lower layer bonding pad is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, for example, the interfacial bonding strength between the first lower layer bonding pad 807a and the contact layer 60a. or improving the interfacial bonding strength between the second lower layer bonding pad 907a and the reflective layer 40a or barrier layer 41a. Another function of the lower bonding pad is to prevent tin (Sn) during the solder or Au-Sn process from diffusing into the reflective structure and damaging the reflectivity of the reflective structure. Therefore, the lower layer bonding pad is made of materials other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), zirconium (Zr), Molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), etc. It is preferable to include a metal material, and the lower layer bonding pad may be a single layer, alloy, or multilayer film of the above material. In one embodiment of the present invention, the lower bonding pad preferably includes a multilayer film of titanium (Ti) or aluminum (Al), or a multilayer film of chromium (Cr) or aluminum (Al).

In one embodiment of the present invention, in the cross-sectional view of the light emitting device 1, the portion of the contact layer 60a connected to the first semiconductor layer 101a is located below the second bonding pad 90a.

In one embodiment of the present invention, in the cross-sectional view of the light emitting device 1, the portion of the contact layer 60a connected to the first semiconductor layer 101a is located above the reflective layer 40a and/or the barrier layer 41a. do.

In one embodiment of the present invention, on the top view of the light emitting device 1, the hole portion 100a has a maximum width smaller than the maximum width of the first bonding pad opening 800a; And/or the hole portion 100a has a maximum width that is smaller than the maximum width of the second bonding pad opening 900a.

In one embodiment of the present invention, on the top view of the light emitting device 1, the plurality of hole portions 100a correspond to the plurality of first recesses 804a and the second bonding pad 90a of the first bonding pad 80a, respectively. It is located within the plurality of second recesses 904a.

Figure 10 is a cross-sectional view of the light emitting device 2 disclosed in one embodiment of the present invention. When comparing the light emitting device 2 with the light emitting device 1 in the above embodiment, the light emitting device 2 has a first bumper pad located below the first bonding pad 80a and the second bonding pad 90a, respectively. (810a) and a second bumper pad 910a. In addition, since the light emitting device 2 and the light emitting device 1 have almost the same structure, the light emitting device 2 of FIG. 10 and the light emitting device 1 of FIG. 9 Structures with the same name and symbol of the light emitting element 1 represent the same structure, have the same material, or have the same function, so descriptions are appropriately omitted or not explained in detail. In this embodiment, the light emitting device 2 includes a first bumper pad 810a located between the first bonding pad 80a and the semiconductor stack 10a, and a second bonding pad 90a and the semiconductor stack 10a. It includes a second bumper pad 910a located between them, and the first bumper pad 810a and the second bumper pad 910a cover part or the entire hole portion 100a, and in this embodiment, the bonding pad ( Since it includes a multi-layer insulating layer between 80a, 90a) and the semiconductor stack 10a, the bonding pads 80a, 90a of the light emitting device 2 are bonded to the bonding pad due to the stress generated during bonding with solder or Au-Sn process bonding. Since cracks occur in (80a, 90a) and the insulating layer, the bumper pads (810a, 910a) are located between the bonding pads (80a, 90a) and the third insulating layer (70a), respectively, and the first bumper pad (810a) and The second bumper pad 910a covers the entire hole portion 100a, and the formation positions of the first bonding pad 80a and the second bonding pad 90a avoid the formation position of the hole portion 100a, and the formation positions of the bumper pad 80a and the second bonding pad 90a are By selecting the material and reducing the thickness, the occurrence of stress between the bonding pad and the insulating layer is reduced. In other words, the first bonding pad 80a and the second bonding pad 90a do not cover the hole portion 100a.

In one embodiment of the present invention, as shown in FIG. 10, on the top view of the light emitting device 2, the shapes of the bumper pads 810a and 910a are the same as the shapes of the bonding pads 80a and 90a, respectively, for example The first bumper pad 810a and the first bonding pad 80a have a comb shape.

In one embodiment of the present invention, on the top view (not shown) of the light emitting device 2, the shapes of the bumper pads 810a and 910a are different from the shapes of the bonding pads 80a and 90a, respectively, for example, the first bumper pad The shape of 810a is rectangular, and the shape of the first bonding pad 80a is comb-shaped.

In another embodiment of the present invention, the sizes of the bumper pads 810a and 910a are different from the sizes of the bonding pads 80a and 90a, respectively, and for example, the area of the first bumper pad 810a is the size of the first bonding pad 80a. is larger than the area of , and the area of the second bumper pad 910a is larger than the area of the second bonding pad 90a.

In another embodiment of the present invention, the distance between the first bonding pad 80a and the second bonding pad 90a is greater than the distance between the first bumper pad 810a and the second bumper pad 910a.

In another embodiment of the present invention, compared to the bonding pads 80a and 90a, the bumper pads 810a and 910a have a relatively large area to release pressure during die bonding of the bonding pads 80a and 90a. In the cross-sectional view of the light emitting device 2, the width of the first bumper pad 810a is 1.5 to 2.5 times the width of the first bonding pad 80a, and is preferably 2 times the width.

In another embodiment of the present invention, compared to the bonding pads 80a and 90a, the bumper pads 810a and 910a have a relatively large area to release pressure during die bonding of the bonding pads 80a and 90a. In the cross-sectional view of the light emitting device 2, the extension distance of the first bumper pad 810a is more than 1 time its own thickness, and preferably is more than 2 times its own thickness.

In another embodiment of the present invention, the bonding pads 80a and 90a have a thickness of 1 to 100 μm, preferably 2 to 6 μm, and the bumper pads 810a and 910a are used for die bonding of the bonding pads 80a and 90a. It has a thickness greater than 0.5μm to release the pressure of the city.

In another embodiment of the present invention, the first bumper pad 810a and the second bumper pad 910a may have a single-layer or multi-layer structure including a metal material. The function of the first bumper pad 810a and the second bumper pad 910a is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, for example, the first bumper pad 810a Contacts the contact layer 60a, and the second bumper pad 910a contacts the reflective layer 40a or the barrier layer 41a. The bumper pads 810a and 910a are made of a metal material other than gold (Au) or copper (Cu), such as chromium (Cr) or nickel, to prevent tin (Sn) from diffusing into the light emitting device during the solder or Au-Sn process. (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum It is preferable to include (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os).

In another embodiment of the present invention, the first bumper pad 810a and/or the second bumper pad 910a include a multi-layer structure made of metal, and the multi-layer structure is formed by contacting or contacting the bonding pads 80a and 90a with solder. It includes a high ductility layer and a low ductility layer to prevent cracks from occurring in the insulating layer between the bonding pads 80a and 90a and the semiconductor stack 10a due to stress generated during Au-Sn process bonding. The high-ductility layer and the low-ductility layer include metals with different Young's modulus.

In another embodiment of the present invention, the high ductility layer of the first bumper pad 810a and the second bumper pad 910a has a thickness greater than or equal to the thickness of the low ductility layer.

In another embodiment of the present invention, the first bumper pad 810a and the second bumper pad 910a have a multi-layer structure including a metal material, and the first bonding pad 80a and the second bonding pad 90a are made of metal. In the case of a multi-layer structure containing materials, one surface where the first bumper pad 810a and the first bonding pad 80a are in contact includes the same metal material, and the second bumper pad 910a and the second bonding pad 90a One surface that is in contact includes the same metal material (e.g., chrome (Cr), nickel (Ni), titanium (Ti), and platinum (Pt)), thereby improving the interfacial bonding strength of the bonding pad and the bumper pad.

As shown in FIGS. 11A and 11B, the fourth insulating layer 110a may be formed on the first bumper pad 810a and the second bumper pad 910a by evaporation or deposition, lithography, etching, etc. It is patterned by the method, and the first bonding pad 80a and the second bonding pad 90a are formed on the first bumper pad 810a and the second bumper pad 910a, respectively, in the manner described above. 4 The insulating layer 110a surrounds the sidewalls of the first bumper pad 810a and the second bumper pad 910a. The fourth insulating layer 110a may have a single-layer or multi-layer structure. When the fourth insulating layer 110a is a multilayer film, the fourth insulating layer 110a is made by alternately stacking two or more materials with different refractive indices to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The material of the fourth insulating layer 110a is made of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, and cyclic olefin. Organic materials such as polymer (COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone ), inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgFx). do.

In one embodiment of the present invention, the manufacturing process of the first bonding pad 80a and the second bonding pad 90a may immediately follow the manufacturing process of the first bumper pad 810a and the second bumper pad 910a. . In another embodiment of the present invention, after the manufacturing process of the first bumper pad 810a and the second bumper pad 910a, the formation step of the fourth insulating layer 110a is first performed, and then the first bonding pad ( 80a) and the second bonding pad 90a are manufactured.

12A to 22 show a method of manufacturing the light emitting device 3 or 4 disclosed in one embodiment of the present invention.

As shown in FIG. 12B, which is a plan view of FIG. 12A and a cross-sectional view taken along line A-A' of FIG. 12A, the method of manufacturing the light emitting device 3 or 4 includes a platform forming step, and the platform forming step The step includes providing a substrate 11b; and forming a semiconductor stack (10b) on the substrate (11b), wherein the semiconductor stack (10b) includes a first semiconductor layer (101b), a second semiconductor layer (102b), and a first semiconductor layer (101b). and an active layer (103b) located between the second semiconductor layer (102b). The semiconductor stack 10b is patterned using lithography or etching to partially remove the second semiconductor layer 102b and the active layer 103b, thereby forming one or more semiconductor structures 1000b; And a surrounding portion 111b surrounding one or more semiconductor structures 1000b may be formed. The surrounding portion 111b exposes the first surface 1011b of the first semiconductor layer 101b. The one or more semiconductor structures 1000b each include one first outer wall 1003b, a second outer wall 1001b, and one inner wall 1002b, and the first outer wall 1003b includes a first semiconductor layer 101b. The second outer wall 1001b is the sidewall of the active layer 103b and/or the second semiconductor layer 102b, and one end of the second outer wall 1001b is the surface 102s of the second semiconductor layer 102b. is connected to, the other end of the second outer wall 1001b is connected to the first surface 1011b of the first semiconductor layer 101b, and one end of the inner wall 1002b is connected to the surface 102s of the second semiconductor layer 102b. ), the other end of the inner wall 1002b is connected to the second surface 1012b of the first semiconductor layer 101b, and the plurality of semiconductor structures 1000b are connected to each other by the first semiconductor layer 101b. do. As shown in Figure 12b, the inner wall 1002b of the semiconductor structure 1000b and the second surface 1012b of the first semiconductor layer 101b form an obtuse angle, and the first outer wall 1003b of the semiconductor structure 1000b The surface 11s of the substrate 11b forms an obtuse angle or a right angle, and the second outer wall 1001b of the semiconductor structure 1000b and the first surface 1011b of the first semiconductor layer 101b form an obtuse angle. The surrounding portion 111b surrounds the semiconductor structure 1000b, and the surrounding portion 111b is rectangular or polygonal in a plan view of the light emitting device 3 or 4.

In one embodiment of the invention, light emitting element 3 or light emitting element 4 has a side length of less than 30 mil. When an external current is injected into the light-emitting device 3 or the light-emitting device 4, the surrounding portion 111b surrounds the semiconductor structure 1000b, so that the light-emitting device 3 or the light-emitting device 4 is The light field distribution can be made uniform and the forward voltage of the light emitting device can be reduced.

In one embodiment of the invention, light emitting element 3 or light emitting element 4 has a side length greater than 30 mil. The semiconductor stack 10b is patterned using lithography or etching to partially remove the second semiconductor layer 102b and the active layer 103b, thereby forming one or more holes penetrating the second semiconductor layer 102b and the active layer 103b. 100b is formed, and one or more hole portions 100b expose one or more second surfaces 1012b of the first semiconductor layer 101b. When an external current is injected into the light-emitting device 3 or 4, the light of the light-emitting device 3 or 4 is illuminated by the distributed arrangement of the surrounding portion 111b and the plurality of hole portions 100b. The field distribution can be made uniform and the forward voltage of the light emitting device can be reduced.

In one embodiment of the present invention, the opening shape of the one or more hole portions 100b includes a circular shape, an oval shape, a rectangular shape, a polygonal shape, or an arbitrary shape. The plurality of hole parts 100b may be arranged in a plurality of rows, and the hole parts 100b in two adjacent rows may be arranged side by side or offset from each other.

In one embodiment of the present invention, the substrate 11b is a gallium arsenide (GaAs) wafer on which aluminum gallium indium phosphorus (AlGaInP) is grown, a sapphire (Al2O3) wafer on which insulium gallium nitrogen (InGaN) is grown, or a gallium nitride (GaN) wafer. ) It may be a growth substrate containing a wafer or a silicon carbide (SiC) wafer. Here, a photoelectric layer such as light-emitting lamination is formed on the substrate 11b using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxial method (MBE), hydride vapor deposition (HVPE), evaporation method, or ion plating method. A semiconductor layer 10b having characteristics can be formed.

In one embodiment of the present invention, the first semiconductor layer 101b and the second semiconductor layer 102b are, for example, a cladding layer or a confinement layer, and both have different conductivity types and electrical properties. , may have polarity, or provide electrons or holes depending on the doped element. For example, the first semiconductor layer 101b is a semiconductor with n-type electrical characteristics, and the second semiconductor layer 102b is a semiconductor with p-type electrical characteristics. It is a semiconductor. The active layer 103b is formed between the first semiconductor layer 101b and the second semiconductor layer 102b, and electrons and holes are recombined in the active layer 103b under current driving, converting electrical energy into light energy to emit light. emits The wavelength of light emitted by the light emitting device 3 or 4 is adjusted by changing the physical and chemical composition of a single or multilayer of the semiconductor stack 10b. The material of the semiconductor layer 10b includes a group III-V semiconductor material, for example, AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0x,y1; It is (x+y)1. Depending on the material of the active layer 103b, when the material of the semiconductor layer 10b is an AlInGaP-based material, red light with a wavelength of 610 nm to 650 nm and green light with a wavelength of 530 nm to 570 nm can be emitted, and the semiconductor layer If the material of (10b) is an InGaN-based material, it can emit blue light with a wavelength of 450 nm to 490 nm, or if the material of the semiconductor layer (10b) is an AlGaN-based material, the wavelength is 400 nm to 250 nm. Can emit external light. The active layer 103b has a single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), and multi-quantum well (MQW). ) can be. The material of the active layer 103b may be a semiconductor with neutral, p-type, or n-type electrical characteristics.

Following the platform forming step, the method of manufacturing the light-emitting device 3 or 4 includes forming a first insulating layer, as shown in the plan view of FIG. 13A and in FIG. 13B, which is a cross-sectional view taken along line A-A' of FIG. 13A. Including the formation stage. The first insulating layer 20b may be formed on the semiconductor structure 1000b by evaporation or deposition, and may be formed on the first surface 1011b of the surrounding portion 111b and the second surface of the hole portion 100b. (1012b) and patterned by lithography and etching to cover the second semiconductor layer 102b of the semiconductor structure 1000b, the second outer wall 1001b and the inner wall 1002b of the active layer 103b. And the first insulating layer 20b is a first insulating layer that covers the surrounding portion 111b so as to cover the first surface 1011b of the first semiconductor layer 101b located in the surrounding portion 111b. Rounding area (200b); a first group of first insulating layer cover areas 201b covering the hole portion 100b so as to cover the second surface 1012b of the first semiconductor layer 101b located in the hole portion 100b; and a second group of first insulating layer openings 202b exposing the surface 102s of the second semiconductor layer 102b. The first insulating layer cover areas 201b of the first group are separated from each other and each corresponds to a plurality of hole portions 100b. The first insulating layer 20b may have a single-layer or multi-layer structure. When the first insulating layer 20b is a single-layer film, the first insulating layer 20b can protect the sidewall of the semiconductor structure 1000b and prevent the active layer 103b from being damaged in a subsequent process. When the first insulating layer 20b is a multilayer film, the first insulating layer 20b is made by alternately stacking two or more materials with different refractive indices to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The first insulating layer 20b is formed of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin, cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, the method of manufacturing the light-emitting device 3 or the light-emitting device 4 following the first insulating layer forming step is as shown in Figure 14A, which is a plan view and a cross-sectional view taken along line A-A' in Figure 14A. As shown in 14b, it includes the step of forming a transparent conductive layer. The transparent conductive layer 30b may be formed on the semiconductor structure 1000b by evaporation or deposition, and is in contact with the second semiconductor layer 102b, and the transparent conductive layer 30b covers the hole portion 100b. I never do that. On the top view of the light emitting device 3 or 4, the transparent conductive layer 30b is formed on almost the entire surface of the second semiconductor layer 102b. Specifically, the transparent conductive layer 30b may be formed in the second group of first insulating layer openings 202b by evaporation or deposition, and may be formed on the outer edge 301b of the transparent conductive layer 30b and the first insulating layer. (20b) are spaced apart from each other to expose the surface (102s) of the second semiconductor layer (102b). The transparent conductive layer 30b includes one or more transparent conductive layer openings 300b, each corresponding to one or more hole portions 100b and/or each corresponding to the first group of first insulating layer cover areas 201b, The outer edge 301b of the transparent conductive layer opening 300b is spaced apart from the inner wall 1002b of the semiconductor structure 1000b and/or the outer edge of the hole portion 100b, and the outer edge of the transparent conductive layer opening 300b is spaced apart from the outer edge of the hole portion 100b ( 100b) Surrounds the outer edge or surrounds the first insulating layer cover area 201b of the first group. The material of the transparent conductive layer 30b includes a material that is transparent to the light emitted by the active layer 103b, and the transparent material is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the platform forming step, the transparent conductive layer forming step may be performed first, and then the first insulating layer forming step may be performed.

In another embodiment of the present invention, after the platform forming step, the forming step of the first insulating layer may be omitted and the transparent conductive layer forming step may be performed directly.

In one embodiment of the present invention, the method of manufacturing the light-emitting device 3 or the light-emitting device 4 following the transparent conductive layer forming step includes the top view of FIG. 15A and the cross-sectional view taken along line A-A' of FIG. 15A in FIG. 15B. As shown, it includes a reflective structure forming step. The reflective structure includes a reflective layer 40b and/or a barrier layer 41b, and may be formed directly on the transparent conductive layer 30b by evaporation or deposition, and the reflective layer 40b is formed on the transparent conductive layer 30b. and the barrier layer 41b. On the top view of the light emitting device 3 or 4, the reflective layer 40b and/or the barrier layer 41b are formed on almost the entire surface of the second semiconductor layer 102b. The outer edge 401b of the reflective layer 40b may be installed inside or outside the outer edge 301b of the transparent conductive layer 30b, or may be installed overlapping and aligned with the outer edge 301b of the transparent conductive layer 30b, The outer edge 411b of the barrier layer 41b may be installed inside or outside the outer edge 401b of the reflective layer 40b, or may be installed to overlap and be aligned with the outer edge 401b of the reflective layer 40b. The reflective layer 40b includes one or more reflective layer openings 400b each corresponding to one or more hole portions 100b, and the barrier layer 41b includes one or more barrier layer openings 410b corresponding to one or more hole portions 100b. Includes. The transparent conductive layer opening 300b, the reflective layer opening 400b, and the barrier layer opening 410b overlap each other. The outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b are spaced apart from the outer edge of the hole portion 100b, and the outer edge of the reflective layer opening 400b and/or the barrier layer opening 410b is spaced apart from the outer edge of the hole portion 100b. ) surrounds the outer periphery.

In another embodiment of the present invention, the forming step of the transparent conductive layer may be omitted, and the reflective structure forming step may be performed directly after the platform forming step or the first insulating layer forming step. For example, the reflective layer 40b and/or the barrier layer 41b are formed directly on the second semiconductor layer 102b, and the reflective layer 40b is located between the second semiconductor layer 102b and the barrier layer 41b. The reflective layer 40b may have a single-layer or multi-layer structure, and the multi-layer structure is, for example, a Bragg reflective structure. The material of the reflective layer 40b includes a metal material with a relatively high reflectivity, and the metal material is, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy thereof. Here, having a relatively high reflectance means having a reflectance of 80% or more for the wavelength of the light emitted by the light emitting device 3. In one embodiment of the present invention, the barrier layer 41b covers the reflective layer 40b to prevent the surface of the reflective layer 40b from being oxidized and the reflectivity of the reflective layer 40b to deteriorate. The material of the barrier layer 41b includes metal, and the metal material includes, for example, titanium (Ti), wolfram (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), and platinum ( It is a metal such as Pt) or an alloy thereof. The barrier layer 41b may have a single-layer or multi-layer structure, and the multi-layer structure is, for example, titanium (Ti)/aluminum (Al) and/or titanium (Ti)/wolfram (W). In one embodiment of the present invention, the barrier layer 41b includes a laminate structure of titanium (Ti)/aluminum (Al) on one side away from the reflective layer 40b and titanium (Ti) on one side close to the reflective layer 40b. )/Wolfram (W). In one embodiment of the present invention, the reflective layer 40b and the barrier layer 41b are preferably made of a metal other than gold (Au) or copper (Cu).

In one embodiment of the present invention, the method of manufacturing the light-emitting device 3 or the light-emitting device 4 following the step of forming the reflective structure is shown in the top view of FIG. 16A and the cross-sectional view taken along line A-A' in FIG. 16B in FIG. 16A. As shown, it includes forming a second insulating layer. The second insulating layer 50b may be formed on the semiconductor layer 10b by evaporation or deposition, and a first group of second insulating layer openings 501b may be formed to expose the first semiconductor layer 101b. is patterned by lithography and etching to form a second group of second insulating layer openings 502b to expose the reflective layer 40b or barrier layer 41b, and the second insulating layer 50b In the patterning process, the first insulating layer surrounding area 200b covered in the surrounding portion 111b in the above-described first insulating layer forming step and the first insulating layer covering area of the first group in the hole portion 100b ( 201b) is etched and removed to expose the first semiconductor layer 101b, and a first group of first insulating layer openings 203b are formed in the hole portion 100b to expose the first semiconductor layer 101b. . In one embodiment of the present invention, as shown in FIG. 16A, the first group of second insulating layer openings 501b are separated from each other and each corresponds to a plurality of hole portions 100b, and the second group of second insulating layer openings 501b are separated from each other and each corresponds to a plurality of hole portions 100b. The layer openings 502b are all close to one side of the substrate 11b, for example, to the left or right of the center line of the substrate 11b, and in one embodiment, the number of second insulating layer openings 502b in the second group is one or more. In this embodiment, the second group of second insulating layer openings 502b are connected to each other to commonly form one annular opening 5020b, and the annular opening 5020b is shown in the top view of the light emitting element 3. It may be comb-shaped, rectangular, oval, circular, or polygonal in shape. In one embodiment of the present invention, the second insulating layer 50b may have a single-layer or multi-layer structure. When the second insulating layer 50b is a multilayer film, the second insulating layer 50b is made by alternately stacking two or more materials with different refractive indices to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The second insulating layer 50b is formed of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin, cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, the method of manufacturing the light-emitting device 3 or the light-emitting device 4 following the second insulating layer forming step includes forming a contact layer, as shown in the plan view of FIG. 17A and the cross-sectional view of FIG. 17B. Includes steps. The contact layer 60b may be formed on the semiconductor layer 10b by evaporation or deposition, and may be patterned by lithography or etching to form the first contact layer 601b and the second contact layer 602b. I get angry. The first contact layer 601b covers all the first group of second insulating layer openings 501b, fills one or more hole portions 100b, contacts the first semiconductor layer 101b, and extends to form a second insulating layer opening 501b. It covers the insulating layer 50b and the second semiconductor layer 102b, and the first contact layer 601b is insulated from the second semiconductor layer 102b through the second insulating layer 50b. The second contact layer 602b is formed in the annular opening 5020b of the second insulating layer 50b and contacts the reflective layer 40b and/or the barrier layer 41b, and the sidewall of the second contact layer 602b ( 6021b) and the side wall 5021b of the annular opening 5020b are spaced apart from each other at a distance. The side wall 6011b of the first contact layer 601b is spaced apart from the side wall 6021b of the second contact layer 602b so that the first contact layer 601b is not connected to the second contact layer 602b. The first contact layer 601b and the second contact layer 602b are partially electrically insulated by the second insulating layer 50b. In plan view, the first contact layer 601b covers the surrounding portion 111b of the semiconductor stack 10b so as to surround the second contact layer 602b. In the top view of FIG. 17A, the second contact layer 602b is close to one side of the substrate 11b, for example, to the left or right of the center line of the substrate 11b. The contact layer 60b defines a fin region 600b at the geometric center on the semiconductor stack 10b. The fin area 600b is not connected to the first contact layer 601b and the second contact layer 602b, but is electrically insulated from each other, and the fin area 600b is connected to the first contact layer 601b and/or the second contact layer 602b. It contains the same material as the contact layer 602b. The fin area 600b is a structure that protects the epitaxial layer and prevents the epitaxial layer from being damaged by the probe during subsequent manufacturing processes such as die separation, die testing, and packaging. The contact layer 60b may have a single-layer or multi-layer structure. In order to reduce the electrical resistance in contact with the first semiconductor layer 101b, the material of the contact layer 60b includes a metal material, such as chromium (Cr), titanium (Ti), wolfram (W), It is a metal such as gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), and platinum (Pt) or an alloy thereof. In one embodiment of the present invention, the material of the contact layer 60b preferably includes a metal material other than gold (Au) and copper (Cu). In one embodiment of the present invention, the material of the contact layer 60b preferably includes a metal with high reflectivity, such as aluminum (Al) or platinum (Pt). In one embodiment of the present invention, one side of the contact layer 60b in contact with the first semiconductor layer 101b is made of chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101b. It is desirable to include.

In one embodiment of the present invention, the method of manufacturing the light emitting device 3 or the light emitting device 4 following the contact layer forming step shown in FIGS. 17A and 17B includes a third insulating layer forming step, as shown in FIG. 18A. As shown in FIG. 18B, which is a plan view and a cross-sectional view taken along line A-A' of FIG. 18A, the third insulating layer 70b may be formed on the semiconductor stack 10b by evaporation or deposition, etc. A third insulating layer opening 701b is formed on the first contact layer 601b to expose the first contact layer 601b shown in Fig. 17a, and the second contact layer 602b shown in Fig. 17a is exposed. The first contact is patterned by lithography and etching to form another third insulating layer opening 702b on the second contact layer 602b, and is partially located on the second semiconductor layer 102b. The layer 601b is sandwiched between the second insulating layer 50b and the third insulating layer 70b. In this embodiment, as shown in FIG. 18A, the third insulating layer opening 701b and the other third insulating layer opening 702b avoid one or more hole portions 100b. In this embodiment, the third insulating layer opening 701b and/or the other third insulating layer opening 702b is an annular opening, and the annular opening may be comb-shaped, rectangular, elliptical, circular, or polygonal in plan view. there is. In the plan view of FIG. 18A, the third insulating layer opening 701b is close to one side of the center line of the substrate 11b, for example, to the right, and the other third insulating layer opening 702b is close to the other side of the center line of the substrate 11b, for example, to the left. Getting close. In the cross-sectional view, the third insulating layer opening 701b has a width greater than the width of the other third insulating layer opening 702b. The third insulating layer 70b may have a single-layer or multi-layer structure. When the third insulating layer 70b is a multilayer film, the third insulating layer 70b is made by alternately stacking two or more materials with different refractive indices to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The third insulating layer 70b is formed of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin, cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

Following the third insulating layer forming step, the method of manufacturing the light emitting device 3 or 4 includes a bonding pad forming step. As shown in the plan view of FIG. 19, the first bonding pad 80b and the second bonding pad 90b can be formed on the semiconductor stack 10b by electroplating, evaporation, or deposition, or by lithography, It is patterned by an etching method. In the top view of FIG. 19, the first bonding pad 80b is close to one side of the center line of the substrate 11b, for example, to the right, and the second bonding pad 90b is close to the other side, for example, to the left, of the center line of the substrate 11b. The first bonding pad 80b is in contact with the first contact layer 601b through the third insulating layer opening 701b, and is electrically connected to the first semiconductor layer 101b through the first contact layer 601b. form The second bonding pad 90b contacts the reflective layer 40b and/or the barrier layer 41b through another third insulating layer opening 702b, and also through the reflective layer 40b and/or the barrier layer 41b. An electrical connection is formed with the second semiconductor layer 102b. The first bonding pad 80b includes a plurality of first convex portions 801b and a plurality of first concave portions 802b that are alternately connected to each other. The second bonding pad 90b includes a plurality of second convex portions 901b and a plurality of second concave portions 902b that are alternately connected to each other. The position of the first concave portion 802b of the first bonding pad 80b and the position of the second concave portion 902b of the second bonding pad 90b substantially correspond to the position of the hole portion 100b. In other words, the first bonding pad 801b and the second bonding pad 802b do not cover any of the holes 100b, and the first concave portion 802b of the first bonding pad 80b and the second bonding pad ( The second concave portion 902b of 90b) is formed around the hole portion 100b while avoiding the hole portion 100b, so that the width of the first concave portion 802b of the first bonding pad 80b or the second bonding pad ( The width of the second concave portion 902b of 90b) is larger than the diameter of any of the hole portions 100b. In one embodiment of the present invention, the plurality of first recesses 802b are aligned substantially side by side with the plurality of second recesses 902b in a plan view. In another embodiment of the present invention, the plurality of first recesses 802b are arranged to be offset from the plurality of second recesses 902b in the plan view.

In one embodiment of the present invention, as shown in Figure 19, the first bonding pad 80b covers the third insulating layer opening 701b, and the second bonding pad 90b covers the other third insulating layer. It covers the opening 702b, and the third insulating layer opening 701b has a maximum width greater than the maximum width of the other third insulating layer opening 702b, so the first bonding pad 80b is connected to the second bonding pad. It has a maximum width greater than that of (90b). The first bonding pad (80b) and the second bonding pad (90b) of different sizes are convenient for discerning the electrical characteristics of the bonding pads when welding the packaging, so that a situation occurs where bonding pads with different electrical characteristics are welded. prevent it from happening.

In one embodiment of the present invention, on the top view of the light emitting device, the third insulating layer opening 701b has an area equal to or larger than the area of the first bonding pad 80b.

In another embodiment of the present invention, the shortest distance between the first convex portion 801b and the second convex portion 901b is smaller than the maximum distance between the first concave portion 802b and the second concave portion 902b.

In another embodiment of the present invention, the first bonding pad 80b includes a first straight side 803b facing the first convex portion 801b and the first concave portion 802b, and a second bonding pad ( 90b) includes a second straight side 903b opposing the second convex portion 901b and the second concave portion 902b. The maximum distance between the first straight side 803b of the first bonding pad 80b and the first convex part 801b is greater than the shortest distance between the first convex part 801b and the second convex part 901b. . The maximum distance between the second straight side 903b of the second bonding pad 90b and the second convex part 901b is greater than the shortest distance between the first convex part 801b and the second convex part 901b. .

In another embodiment of the present invention, the radius of curvature of the plurality of first concave portions 802b of the first bonding pad 80b is the radius of curvature of the plurality of first convex portions 801b of the first bonding pad 80b. Different, for example, the radius of curvature of the plurality of first concave portions 802b of the first bonding pad 80b is larger or smaller than the radius of curvature of the plurality of first convex portions 801b of the first bonding pad 80b. In another embodiment of the present invention, the radius of curvature of the plurality of second concave portions 902b of the second bonding pad 90b is greater than the radius of curvature of the plurality of second convex portions 901b of the second bonding pad 90b. Big or small.

In another embodiment of the present invention, the radius of curvature of the first convex portion 801b of the first bonding pad 80b is larger or smaller than the radius of curvature of the second convex portion 901b of the second bonding pad 90b.

In another embodiment of the present invention, the plurality of first recesses 802b of the first bonding pad 80b face the plurality of second recesses 902b of the second bonding pad 90b, and the plurality of first recesses 802b of the first bonding pad 80b face each other. The radius of curvature of the first concave portion 802b is larger or smaller than the radius of curvature of the plurality of second concave portions 902b.

In another embodiment of the present invention, the shape of the first bonding pad 80b and the shape of the second bonding pad 90b are different, for example, the shape of the first bonding pad 80b is rectangular, and the shape of the second bonding pad (90b) is different. The shape of 90b) is a comb shape.

In another embodiment of the present invention, the size of the first bonding pad 80b and the size of the second bonding pad 90b are different, for example, the area of the first bonding pad 80b is greater than that of the second bonding pad 90b. It is bigger than the area.

FIG. 20 is a cross-sectional view taken along line A-A' in FIG. 19. The light emitting device 3 disclosed in this embodiment is a flip chip type light emitting diode device. The light emitting device 3 includes a substrate 11b; It is located on the substrate 11b and includes a semiconductor stack 10b, wherein the semiconductor stack 10b includes a first semiconductor layer 101b, a second semiconductor layer 102b, and a first semiconductor layer 101b and a second semiconductor layer. one or more semiconductor structures (1000b) including an active layer (103b) located between the layers (102b) and connected to each other by a first semiconductor layer (101b); a surrounding portion 111b surrounding one or more semiconductor structures 1000b and exposing the first surface 1011b of the first semiconductor layer 101b; and a first bonding pad 80b and a second bonding pad 90b located on one or more semiconductor structures 1000b. As shown in FIGS. 19 and 20, one or more semiconductor structures 1000b each include a plurality of outer walls 1001b and a plurality of inner walls 1002b, and one end of the outer wall 1001b is a second semiconductor layer ( It is connected to the surface 102s of the outer wall 102b, the other end of the outer wall 1001b is connected to the first surface 1011b of the first semiconductor layer 101b, and one end of the inner wall 1002b is connected to the second semiconductor layer 102b. ), and the other end of the inner wall 1002b is connected to the second surface 1012b of the first semiconductor layer 101b.

In one embodiment of the present invention, when the light emitting device 3 has a side length greater than 30 mil, the light emitting device 3 is configured to expose at least one second surface 1012b of the first semiconductor layer 101b. One or more holes 100b penetrating the second semiconductor layer 102b and the active layer 103b; and is located on the first surface 1011b of the first semiconductor layer 101b, surrounds the periphery of one or more semiconductor structures 1000b, and forms an electrical connection by contacting the first semiconductor layer 101b. 1 A contact layer (60b) formed on one or more second surfaces (1012b) of the semiconductor layer (101b) and covering one or more hole portions (100b) and contacting the first semiconductor layer (101b) to form an electrical connection; It further includes, the contact layer 60b includes a first contact layer 601b and a second contact layer 602b, the first contact layer 601b is located on the second semiconductor layer, and the contact layer 60b includes a first contact layer 601b and a second contact layer 602b. It surrounds the side wall and is connected to the first semiconductor layer, the second contact layer is located on the second semiconductor layer and connected to the second semiconductor layer, and the second contact layer 602b is located on the first contact layer 601b. Surrounded by, the first contact layer 601b and the second contact layer 602b do not overlap each other.

In one embodiment of the present invention, when the light emitting device 3 has a side length of less than 30 mil, the light emitting device 3 may not include any hole portion 100b in order to obtain a relatively large light emitting area.

In one embodiment of the present invention, in the top view of the light emitting device 3, the total surface area of the contact layer 60b is larger than the total surface area of the active layer 103b.

In one embodiment of the present invention, in the plan view of the light emitting device 3, the total length of the outer edge of the contact layer 60b is greater than the total length of the outer edge of the active layer 103b.

In one embodiment of the present invention, on the top view of the light emitting device 3, the first contact layer 601b has an area larger than the area of the second contact layer 602b.

In one embodiment of the present invention, the formation position of the first bonding pad 80b and the second bonding pad 90b is such that any hole 100b is formed by the first bonding pad 80b or the second bonding pad 90b. Avoid the hole part 100b so as not to cover it.

In one embodiment of the present invention, in the cross-sectional view of the light emitting device 3, the first contact layer 601b connected to the first semiconductor layer 101b is not located below the second bonding pad 90b.

In one embodiment of the present invention, the minimum distance between the first bonding pad 80b and the second bonding pad 90b is greater than 50 μm.

In one embodiment of the present invention, the distance between the first bonding pad 80b and the second bonding pad 90b is less than 300 μm.

In one embodiment of the present invention, the first bonding pad 80b and the second bonding pad 90b may have a single-layer or multi-layer structure including a metal material. The material of the first bonding pad 80b and the second bonding pad 90b includes metal, and the metal material is, for example, chromium (Cr), titanium (Ti), wolfram (W), aluminum (Al), and indium ( It is a metal such as In), tin (Sn), nickel (Ni), and platinum (Pt) or an alloy thereof. When the first bonding pad 80b and the second bonding pad 90b have a multi-layer structure, the first bonding pad 80b includes a first lower layer bonding pad (not shown) and a first upper layer bonding pad (not shown). And the second bonding pad 90b includes a second lower layer bonding pad (not shown) and a second upper layer bonding pad (not shown). The upper layer bonding pad and lower layer bonding pad each have different functions. The function of the upper layer bonding pad is mainly to weld and form lead lines, and by the upper layer bonding pad, the light emitting device 3 is mounted on a mounting substrate in a flip chip format using solder or Au-Sn process bonding. Specific metal materials of the upper bonding pad include highly ductile materials. Highly ductile materials include, for example, nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), and gold (Au). ), wolfram (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir) ), ruthenium (Ru), and osmium (Os). The upper bonding pad may be a single layer, alloy, or multilayer film of the above material. In one embodiment of the present invention, the material of the upper bonding pad preferably includes nickel (Ni) and/or gold (Au), and the upper bonding pad is a single layer or a multilayer. The function of the lower bonding pad is to form a stable interface with the contact layer 60b, the reflective layer 40b, or the barrier layer 41b, for example, to improve the bonding strength of the interface between the first lower bonding pad and the contact layer 60b. or improve the bonding strength of the interface between the second lower layer bonding pad and the reflective layer 40b and/or the barrier layer 41b. Another function of the lower layer bonding pad is to prevent tin (Sn) during the solder or Au-Sn process from diffusing into the reflective structure and damaging the reflectance of the reflective structure. Therefore, the lower layer bonding pad is made of materials other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), zirconium (Zr), Molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), etc. It is preferable to include a metal material, and the lower layer bonding pad may be a single layer, alloy, or multilayer film of the above material. In one embodiment of the present invention, the lower layer bonding pad preferably includes a multilayer film of titanium (Ti) or aluminum (Al), or a multilayer film of chromium (Cr) or aluminum (Al).

In one embodiment of the present invention, when the light emitting device 3 is mounted on a package substrate in a flip chip format by solder, there is a height difference (H) between the first bonding pad 80b and the second bonding pad 90b. There may be. As shown in FIG. 20, the second insulating layer 50b below the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b below the second bonding pad 90b covers the reflective layer 40b. Since the second insulating layer opening 502b is included to expose the reflective layer 40b or the barrier layer 41b, the first bonding pad 80b and the second bonding pad 90b each have a third insulating layer opening 701b. ) and other third insulating layer openings 702b, when comparing the top surface 80s of the first bonding pad 80b and the top surface 90s of the second bonding pad 90b, the first bonding pad ( The top surface (80s) of 80b) is higher than the top surface (90s) of the second bonding pad (90b). In other words, there is a height difference (H) between the top surface (80s) of the first bonding pad (80b) and the top surface (90s) of the second bonding pad (90b), and the first bonding pad (80b) and the second bonding pad (90b) The height difference H between 90b is almost equal to the thickness of the second insulating layer 50b. In one embodiment, the height difference between the first bonding pad 80b and the second bonding pad 90b may be 0.5 μm to 2.5 μm, for example, 1.5 μm. When the first bonding pad 80b and the second bonding pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, respectively, the first bonding pad 80b is formed in the third insulating layer opening 701b. It contacts the first contact layer 601b through the insulating layer opening 701b, extends from the third insulating layer opening 701b to cover a portion of the surface of the third insulating layer 70b, and has a second bonding pad 90b. ) is in contact with the second contact layer 602b through another third insulating layer opening 702b, and extends from the other third insulating layer opening 702b to cover a portion of the surface of the third insulating layer 70b.

Figure 21 is a plan view of the light emitting device 4 disclosed in one embodiment of the present invention. Figure 22 is a cross-sectional view of the light emitting device 4 disclosed in one embodiment of the present invention. Compared to the light emitting device 3 of the above embodiment, the light emitting device 4 and the light emitting device 3 are almost the same, except that the structures of the first bonding pad and the second bonding pad are different. In terms of structure, the light emitting device 4 includes elements with the same symbols as the light emitting device 3, so description is omitted. When the light emitting device 4 is mounted on a package substrate in a flip chip format by Au-Sn process bonding, the first bonding pad 80b and the second bonding pad 90b are used to increase the rigidity between the bonding pad and the package substrate. ), the smaller the height difference between them, the better. As shown in FIG. 22, the second insulating layer 50b below the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b below the second bonding pad 90b covers the reflective layer 40b. It includes a second insulating layer opening 502b to expose the reflective layer 40b or the barrier layer 41b. In this embodiment, in order to reduce the height difference between the top surface (80s) of the first bonding pad (80b) and the top surface (90s) of the second bonding pad (90b), the third insulating layer opening (701b) is formed by another 3 It has a width greater than the width of the insulating layer opening 702b. When the first bonding pad 80b and the second bonding pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, respectively, the first bonding pad 80b is formed in the third insulating layer opening 701b. It is formed entirely within the insulating layer opening 701b and contacts the first contact layer 601b, and the second bonding pad 90b is formed in the other third insulating layer opening 702b to form the reflective layer 40b and/or the barrier layer. The second bonding pad 90b is in contact with 41b and extends from the third insulating layer opening 702b to cover a portion of the surface of the third insulating layer 70b. In other words, the third insulating layer is not formed under the first bonding pad 80b, but a portion of the third insulating layer is formed under the second bonding pad 90b. In this embodiment, the height difference between the first bonding pad 80b and the second bonding pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm.

Figure 23 is a cross-sectional view of the light emitting device 5 disclosed in one embodiment of the present invention. Compared to the light emitting device 3 and the light emitting device 4 of the above embodiment, the light emitting device 5 is different from the light emitting device 3 and the light emitting device 4, except that the structure of the second bonding pad is different. Since the light-emitting device 5 has almost the same structure as the device 4 and includes devices with the same symbols as the light-emitting device 3 and the light-emitting device 4, description thereof will be omitted. When the light emitting device 5 is mounted on a package substrate in a flip chip format by Au-Sn process bonding, the first bonding pad 80b and the second bonding pad 90b are used to increase the robustness between the bonding pad and the package substrate. ), the smaller the height difference between them, the better. As described above, in addition to forming some third insulating layers on the lower side of the second bonding pad 90b, a second bumper pad 910b is formed on the lower side of the second bonding pad 90b to form a first bonding pad. The height difference between the top surface of 80b and the top surface of the second bonding pad 90b can be reduced. As shown in FIG. 23, the second insulating layer 50b below the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b below the second bonding pad 90b covers the reflective layer 40b. It includes a second insulating layer opening 502b to expose the reflective layer 40b or the barrier layer 41b. In this embodiment, the first bonding pad 80b is formed entirely within the third insulating layer opening 701b and contacts the first contact layer 601b, and the second bonding pad 90b is formed through another third insulating layer opening 701b. It is formed entirely within 702b and is in contact with the second contact layer 602b. In other words, the third insulating layer is not formed below the first bonding pad 80b and the second bonding pad 90b. In this embodiment, the upper surface of the first bonding pad 80b and the second bonding pad 90b are formed by the second bumper pad 910b located between the second bonding pad 90b and the second contact layer 602b. ), and the second bumper pad 910b is made of gold (Au) and copper (Cu) to prevent tin (Sn) from diffusing into the light emitting device 5 during the Au-Sn process. Other metal materials, such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta) , it is preferable to include metal materials such as aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os). . In this embodiment, the height difference between the top surface of the first bonding pad 80b and the top surface of the second bonding pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm. . In this embodiment, the second bumper pad 910b has a thickness substantially equal to the thickness of the second insulating layer 50b.

Figure 24 is a cross-sectional view of the light emitting device 6 disclosed in one embodiment of the present invention. The light emitting device 6 is a light emitting device compared to the light emitting device 3 and the light emitting device 4 of the above embodiment, except that the structure of the third insulating layer 70b below the first bonding pad 80b is different. (6) has almost the same structure as the light-emitting element (3) and the light-emitting element (4), and the light-emitting element (6) includes elements with almost the same symbols as the light-emitting element (3) and the light-emitting element (4). Omit it. As shown in FIG. 24, the third insulating layer 70b can be formed on the semiconductor stack 10b by evaporation or deposition, and is patterned by lithography or etching to form a first contact layer ( A third insulating layer opening 701b is formed on 601b) to expose the first contact layer 601b, and another third insulating layer opening 702b is formed on the second contact layer 602b to expose the second contact layer 601b. The contact layer 602b is exposed. The first bonding pad 80b and the second bonding pad 90b may be formed on the semiconductor stack 10b using electroplating, evaporation, or deposition, or may be patterned using lithography or etching. The first bonding pad 80b is in contact with the first contact layer 601b through the third insulating layer opening 701b, and is electrically connected to the first semiconductor layer 101b through the first contact layer 601b. form During the etching process of the third insulating layer opening 701b, the first contact layer 601b and the second insulating layer 50b on the lower side of the first bonding pad 80b are overetched when the third insulating layer 70b is etched. In order to prevent the reflective layer 40b and/or the barrier layer 41b from being removed by etching, the third insulating layer 70b below the first bonding pad 80b is etched to form a third insulating layer opening ( By reducing the area of 701b), the third insulating layer 70b of the first portion is located between the first bonding pad 80b and the first contact layer 601b, and is completely covered by the first bonding pad 80b. Left to be covered, the third insulating layer 70b of the other second part is located around the first bonding pad 80b, and the gap between the third insulating layer 70b of the first part and the second part is 3 Constructs an insulating layer opening 701b. Specifically, the third insulating layer 70b of the first portion completely covered by the first bonding pad 80b has a width greater than the width of the third insulating layer opening 701b on the lower side of the bonding pad 80b. . In this embodiment, on the top view of the light emitting device, the third insulating layer opening 701b is an annular opening.

Figures 25 to 34b are diagrams showing the manufacturing method and structure of the light emitting device 7 disclosed in one embodiment of the present invention.

As shown in Figure 25, the method of manufacturing the light emitting device 7 includes providing a substrate 11c; and forming a semiconductor layer 10c on the substrate 11c, wherein the semiconductor layer 10c includes a first semiconductor layer 101c, a second semiconductor layer 102c, and a first semiconductor layer 101c. It includes an active layer 103c located between the second semiconductor layers 102c.

In one embodiment of the present invention, the substrate 11c is a gallium arsenide (GaAs) wafer on which aluminum gallium indium phosphorus (AlGaInP) is grown, a sapphire (Al2O3) wafer on which insulium gallium nitrogen (InGaN) is grown, or a gallium nitride (GaN) wafer. ) It may be a growth substrate containing a wafer or a silicon carbide (SiC) wafer.

In one embodiment of the present invention, light is emitted on the substrate 11c by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxial method (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating method. A semiconductor layer 10c having photoelectric properties, such as a light-emitting layer, is formed, and physical vapor deposition includes sputtering or evaporation. The first semiconductor layer 101c and the second semiconductor layer 102c may be a cladding layer or a confinement layer, and both have different conductivity types, electrical properties, polarity, or are doped. Electrons or holes are provided depending on the element. For example, the first semiconductor layer 101c is a semiconductor with n-type electrical characteristics, and the second semiconductor layer 102c is a semiconductor with p-type electrical characteristics. The active layer 103c is formed between the first semiconductor layer 101c and the second semiconductor layer 102c, and electrons and holes are recombined in the active layer 103c under current driving, converting electrical energy into light energy to emit light. emits The wavelength of light emitted by the light emitting element 7 is adjusted by changing the physical and chemical composition of the single or multilayer in the semiconductor stack 10c. The material of the semiconductor layer 10c includes a group III-V semiconductor material, for example, AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0x,y1;(x+y)1. Depending on the material of the active layer 103c, when the material of the semiconductor layer 10c is an AlInGaP-based material, red light with a wavelength of 610 nm to 650 nm and green light with a wavelength of 530 nm to 570 nm can be emitted, and the semiconductor layer If the material of (10c) is an InGaN-based material, it can emit blue light with a wavelength of 450 nm to 490 nm, or if the material of the semiconductor layer (10c) is an AlGaN-based or AlInGaN-based material, it can emit blue light with a wavelength of 400 nm to 400 nm. It can emit ultraviolet light of 250 nm. The active layer 103c has a single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), and multi-quantum well (MQW). ) can be. The material of the active layer 103c may be a semiconductor with neutral, p-type, or n-type electrical characteristics.

In an embodiment of the present invention, PVD aluminum nitride (AlN) is formed as a buffer layer between the semiconductor stack 10c and the substrate 11c, thereby improving the epitaxial quality of the semiconductor stack 10c. In an embodiment, the target forming PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target made of aluminum is used to react with the aluminum target in the environment of a nitrogen source to form aluminum nitride.

As shown in FIG. 26B, which is a plan view of FIG. 26A and a cross-sectional view taken along line A-A' of FIG. 26A, after forming the semiconductor stack 10c on the substrate 11c, the method of manufacturing the light emitting device 7 is Includes platform formation stage. By patterning the semiconductor layer 10c using lithography and etching, part of the second semiconductor layer 102c and the active layer 103c are removed to form one or more semiconductor structures 1000c and around the one or more semiconductor structures 1000c. A surrounding portion 111c exposing the first surface 1011c of the first semiconductor layer 101c and one or more hole portions 100c exposing the second surface 1012c of the first semiconductor layer 101c are formed. .

In one embodiment of the present invention, the plurality of semiconductor structures 1000c are separated from each other to expose the surface 11s of the substrate 11c or are connected to each other by the first semiconductor layer 101c. The one or more semiconductor structures 1000c each include a first outer wall 1003c, a second outer wall 1001c, and one or more inner walls 1002c, and the first outer wall 1003c is a sidewall of the first semiconductor layer 101c. The second outer wall 1001c is the active layer 103c and/or the sidewall of the second semiconductor layer 102c, and one end of the second outer wall 1001c is connected to the surface 102s of the second semiconductor layer 102c. The other end of the second outer wall 1001c is connected to the first surface 1011c of the first semiconductor layer 101c, and one end of the inner wall 1002c is connected to the surface 102s of the second semiconductor layer 102c. connected, and the other end of the inner wall 1002c is connected to the second surface 1012c of the first semiconductor layer 101c. As shown in FIG. 26B, the inner wall 1002c of the semiconductor structure 1000c and the second surface 1012c of the first semiconductor layer 101c form an obtuse angle or a right angle, and the first outer wall 1002c of the semiconductor structure 1000c (1003c) and the surface 11s of the substrate 11c form an obtuse angle or a right angle, and the second outer wall 1001c of the semiconductor structure 1000c and the first surface 1011c of the first semiconductor layer 101c form an obtuse angle or It forms a right angle.

In one embodiment of the present invention, the surrounding portion 111c is rectangular or polygonal when viewed from a top view of the light emitting device 7 shown in FIG. 26A.

In one embodiment of the present invention, the opening shape of the hole portion 100c is circular, oval, rectangular, polygonal, or any other shape. The plurality of hole parts 100c may be arranged in a plurality of rows, and the hole parts 100c on any two adjacent rows or on two adjacent rows may be arranged side by side or offset from each other.

In one embodiment of the present invention, a plurality of hole parts 100c may be arranged in a first row and a second row, and a first shortest distance is provided between two adjacent hole parts 100c located on the same row, There is a second shortest distance between the hole part 100c located on the first row and the hole part 100c located on the second row, and the first shortest distance is greater or smaller than the second shortest distance. When an external current is injected into the light emitting device 7, the light field distribution of the light emitting device 7 can be made uniform and the forward voltage of the light emitting device 7 can be reduced by distributing the plurality of hole portions 100c. You can do it.

In one embodiment of the present invention, the plurality of hole parts 100c may be arranged in a first row, a second row, and a third row, with the hole part 100c located on the first row and the hole part 100c located on the second row. There is a first shortest distance between the hole units 100c, and there is a second shortest distance between the hole units 100c located on the second row and the hole units 100c located on the third row, and the first shortest distance is the 2 Less than the shortest distance. When an external current is injected into the light emitting device 7, the light field distribution of the light emitting device 7 can be made uniform and the forward voltage of the light emitting device 7 can be reduced by dispersing the plurality of hole portions 100c. You can do it.

In one embodiment of the present invention, when the light emitting device 7 has a side length greater than 30 mil, the light emitting device 7 includes a surrounding portion 111c and one or more hole portions 100c. There is a first shortest distance between two adjacent hole parts 100c, and a second shortest distance is between any hole part 100c and the first outer wall 1003c of the first semiconductor layer 101c. The distance is less than the second shortest distance. When an external current is injected into the light emitting device 7, the light field distribution of the light emitting device 7 can be made uniform by dispersing the surrounding portion 111c and the one or more hole portions 100c, and the light emitting device ( 7) The forward voltage can be reduced.

In one embodiment of the present invention, when the light emitting device 7 has a side length of less than 30 mil, the light emitting device 7 includes a surrounding portion 111c to increase the area of the active layer capable of emitting light. , does not include the hole portion 100c. When an external current is injected into the light-emitting device 7, the light field distribution of the light-emitting device 7 can be made uniform by the structure in which the surrounding portion 111c surrounds the semiconductor structure 1000c, and the light-emitting device 7 The forward voltage in (7) can be reduced.

Following the platform forming step, the method of manufacturing the light emitting device 7 includes a first insulating layer forming step, as shown in FIG. 27B, which is a plan view of FIG. 27A and a cross-sectional view taken along line A-A' of FIG. 27A. A first insulating layer 20c is formed on the semiconductor structure 1000c using a method such as physical vapor deposition or chemical vapor deposition, and the first insulating layer 20c is patterned using lithography or etching to form the surrounding portion. A first insulating layer surrounding area 200c is formed to cover a portion of the first surface 1011c of 111c and also covers the second outer wall 1001c of the semiconductor structure 1000c, and a plurality of hole portions 100c are formed. Forming a first insulating layer cover area 201c grouped to cover the second surface 1012c and also covering the inner wall 1002c of the semiconductor structure 1000c, and also forming a surface of the second semiconductor layer 102c. A first insulating layer opening 202c is formed to expose 102s. The grouped first insulating layer cover areas 201c are separated from each other and each corresponds to a plurality of hole portions 100c. The first insulating layer 20c may have a single-layer or laminated structure. When the first insulating layer 20c has a single-layer structure, the first insulating layer 20c can protect the sidewall of the semiconductor structure 1000c and prevent the active layer 103c from being damaged by a subsequent manufacturing process. When the first insulating layer 20c has a laminated structure, the first insulating layer 20c not only protects the semiconductor structure 1000c, but also forms a Bragg reflector ( By forming a DBR) structure, light of a specific wavelength can be selectively reflected. The first insulating layer 20c is formed of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin, cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, the method of manufacturing the light emitting device 7 following the first insulating layer forming step is as shown in FIG. 28B, which is a plan view of FIG. 28A and a cross-sectional view taken along line A-A' of FIG. 28A. , including the step of forming a transparent conductive layer. A transparent conductive layer 30c is formed in the opening 202c of the first insulating layer by a method such as physical vapor deposition or chemical vapor deposition, and the outer edge 301c of the transparent conductive layer 30c and the first insulating layer 20c are separated by a distance. are spaced apart from each other to expose a portion of the surface 102s of the second semiconductor layer 102c. Since the transparent conductive layer 30c is formed on almost the entire surface of the second semiconductor layer 102c and is in contact with the second semiconductor layer 102c, the current is transmitted to the second semiconductor layer 102c by the transparent conductive layer 30c. It spreads evenly throughout. The material of the transparent conductive layer 30c includes a material that is transparent to the light emitted by the active layer 103c, and the transparent material is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the platform forming step, the transparent conductive layer forming step may be performed first, and then the first insulating layer forming step may be performed.

In another embodiment of the present invention, after the platform forming step, the forming step of the first insulating layer may be omitted and the transparent conductive layer forming step may be proceeded directly.

In one embodiment of the present invention, the method of manufacturing the light emitting device 7 following the transparent conductive layer forming step is as follows: a top view of FIG. 29A, a partial enlargement of area B in FIG. 29B, a partial enlargement of area C in FIG. 29C, FIG. As shown in the partial enlarged view of area E in FIGS. 29D and 29E, which are cross-sectional views along line A-A' of 29A, a reflective structure forming step is included. A reflective structure 400 is formed on the transparent conductive layer 30c by a method such as physical vapor deposition or chemical vapor deposition, and the reflective structure 400 includes a reflective layer 40c and/or a barrier layer 41c, and the reflective layer (40c) is located between the transparent conductive layer (30c) and the barrier layer (41c). In one embodiment of the present invention, the outer edge 401c of the reflective layer 40c may be installed inside or outside the outer edge 301c of the transparent conductive layer 30c, or the outer edge 301c of the transparent conductive layer 30c. ) can be installed to be aligned with the barrier layer (41c), and the outer edge (411c) of the barrier layer (41c) is installed inside or outside the outer edge (401c) of the reflective layer (40c), or while overlapping with the outer edge (401c) of the reflective layer (40c). Can be installed aligned. As shown in the partially enlarged view of FIGS. 29b and 29c and the partially enlarged view of FIG. 29e, the outer edge 401c of the reflective layer 40c does not overlap the outer edge 301c of the transparent conductive layer 30c, and is transparent and conductive. The outer edge 301c of the layer 30c is covered by the reflective layer 40c, preventing the barrier layer 41c from connecting with the transparent conductive layer 30c.

In another embodiment of the present invention, the forming step of the transparent conductive layer can be omitted, and after the platform forming step or the first insulating layer forming step, the reflective structure forming step must be directly performed, for example, the reflective layer 40c and/or The barrier layer 41c is formed directly on the second semiconductor layer 102c, and the reflective layer 40c is located between the second semiconductor layer 102c and the barrier layer 41c.

The reflective layer 40c may have a single-layer or laminated structure, and the laminated structure is, for example, a Bragg reflective structure. The material of the reflective layer 40c includes a metal material with a relatively high reflectivity, and the metal material is, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy thereof. Here, having a relatively high reflectance means having a reflectance of 80% or more for the wavelength of the light emitted by the light emitting device 7. In one embodiment of the present invention, the barrier layer 41c covers the reflective layer 40c to prevent the surface of the reflective layer 40c from being oxidized and the reflectivity of the reflective layer 40c to deteriorate. The material of the barrier layer 41c includes a metal material, such as titanium (Ti), wolfram (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), and platinum ( It is a metal such as Pt) or an alloy thereof. The barrier layer 41c may have a single-layer or laminated structure, and the laminated structure is, for example, titanium (Ti)/aluminum (Al) and/or titanium (Ti)/wolfram (W). In one embodiment of the present invention, the barrier layer 41c includes a titanium (Ti)/wolfram (W) laminated structure on one side close to the reflective layer 40c, and titanium (Ti) on one side away from the reflective layer 40c. )/Aluminum (Al) laminated structure. In one embodiment of the present invention, the material of the reflective layer 40c and the barrier layer 41c includes a metal material other than gold (Au) or copper (Cu). As a result, in the subsequent manufacturing process, metals such as tin (Sn) in the package solder diffuse into the light-emitting device 7, and metal materials inside the light-emitting device 7, such as gold (Au) or copper (Cu), and the process ( By forming a copolymer, structural deformation of the light emitting device 7 can be prevented.

In one embodiment of the present invention, the method of manufacturing the light emitting device 7 following the forming step of the reflective structure is as shown in the plan view of FIG. 30A and the cross-sectional view taken along line A-A' of FIG. 30A in FIG. 30B, It includes forming a second insulating layer. A second insulating layer 50c is formed on the semiconductor structure 1000c using a method such as physical vapor deposition or chemical vapor deposition, and the second insulating layer 50c is patterned using lithography or etching to form a first semiconductor layer. Forming one or a first group of second insulating layer openings 501c to expose 101c, and forming one or a second group of second insulating layer openings 501c to expose reflective layer 40c or barrier layer 41c. In the process of forming (502c) and patterning the second insulating layer (50c), the first insulating layer surrounding area (200c) and the hole portion (200c) covered by the surrounding portion (111c) in the first insulating layer forming step are formed. The first group of first insulating layer cover areas 201c in 100c) are partially etched and removed to expose the first semiconductor layer 101c, and the first group of first insulating layer openings 203c are formed in the hole portion 100c. is formed to expose the first semiconductor layer 101c.

In this embodiment, as shown in the plan view of FIG. 30A and the cross-sectional view of FIG. 30B, the first group of second insulating layer openings 501c include a shape or number corresponding to the shape or number of the hole portions 100c. do. The second insulating layer opening 501c located on the first semiconductor layer 101c and the second insulating layer opening 502c located on the second semiconductor layer 102c include different shapes, widths, and numbers. The top view opening shapes of the second insulating layer openings 501c and 502c are annular openings.

In this embodiment, as shown in FIG. 30A, the second insulating layer openings 501c located on the first semiconductor layer 101c are separated from each other and correspond to a plurality of hole portions 100c, and the second semiconductor layer 101c is separated from each other and corresponds to a plurality of holes 100c. The second insulating layer opening 502c located on the layer 102c is close to one side of the substrate 11c, for example, to the left or right of the center line C-C' of the substrate 11c. The second insulating layer 50c may have a single-layer or laminated structure. When the second insulating layer 50c has a single-layer structure, the second insulating layer 50c can protect the sidewall of the semiconductor structure 1000c and prevent the active layer 103c from being damaged by a subsequent manufacturing process. When the second insulating layer 50c has a laminated structure, the second insulating layer 50c is made by alternately stacking two or more materials with different refractive indices to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The second insulating layer 50c is made of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin, and cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In an embodiment of the present invention, the method of manufacturing the light emitting device 7 following the second insulating layer forming step is as shown in FIG. 31B, which is a plan view of FIG. 31A and a cross-sectional view taken along line A-A' of FIG. 31A, It includes a contact layer forming step. A contact layer 60c is formed on the semiconductor layer 10c using a method such as physical vapor deposition or chemical vapor deposition, and the contact layer 60c is patterned using lithography or etching to form a first contact layer 601c. , forming a second contact layer 602c and a fin region 600c. The first contact layer 601c is filled in the hole portion 100c and covers the second insulating layer opening 501c, contacts the first semiconductor layer 101c, and extends to form the second insulating layer 50c and the first contact layer 601c. 2 The partial surface of the semiconductor layer 102c is covered, and the first contact layer 601c is insulated from the second semiconductor layer 102c through the second insulating layer 50c. The second contact layer 602c is formed within the annular opening 502c of the second insulating layer 50c and partially contacts the reflective layer 40c and/or the barrier layer 41c.

In one embodiment of the present invention, the first contact layer 601c, the second contact layer 602c, and the fin area 600c are spaced apart from each other. The second contact layer 602c is formed by partially extending into the annular opening 502c of the second insulating layer 50c, and the sidewall 6021c of the second contact layer 602c and the sidewall of the annular opening 502c ( 5021c) are spaced apart from each other, and the side wall 6011c of the first contact layer 601c is spaced apart from the side wall 6021c of the second contact layer 602c, so that the first contact layer 601c is It is not connected to the second contact layer 602c, and the first contact layer 601c and the second contact layer 602c are partially electrically insulated by the second insulating layer 50c. On the plan view of the light emitting device 7, the first contact layer 601c is surrounded by a surrounding portion of the semiconductor stack 10c so that the first contact layer 601c surrounds a plurality of side walls of the second contact layer 602c. 111c) is covered.

In one embodiment of the present invention, the first contact layer 601c contacts the first semiconductor layer 101c by the surrounding portion 111c and the hole portion 100c. When an external current is injected into the light emitting device 7, some of the current is conducted to the first semiconductor layer 101c by the surrounding portion 111c, and other portions of the current are conducted to the first semiconductor layer 101c by the plurality of hole portions 100c. It continues until (101c).

As shown in FIG. 31A, the second contact layer 602c is close to one side of the substrate 11c, for example, to the left or right of the center line C-C' of the substrate 11c. The fin area 600c is located at the geometric center of the semiconductor stack 10c. The fin area 600c is connected to the first contact layer 601c and the second contact layer 602c, and is electrically insulated from the first contact layer 601c and the second contact layer 602c, and the fin area ( 600c) includes the same material as the first contact layer 601c and/or the second contact layer 602c. The fin area 600c is a structure that protects the epitaxial layer and prevents the epitaxial layer from being damaged by external forces such as probes or pins during subsequent manufacturing processes such as die separation, die testing, and packaging. The shape of the fin area 600c is rectangular, oval, or circular.

In one embodiment of the present invention, fin area 600c is located at the geometric center on semiconductor stack 10c. The fin area 600c is connected to the first contact layer 601c or the second contact layer 602c, and the fin area 600c is connected to the first contact layer 601c and/or the second contact layer 602c. Contains the same material.

In one embodiment of the present invention, the contact layer 60c may have a single-layer or laminated structure. In order to reduce the electrical resistance in contact with the first semiconductor layer 101c, the material of the contact layer 60c includes a metal material, such as chromium (Cr), titanium (Ti), wolfram (W), It is a metal such as gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), and platinum (Pt) or an alloy thereof. The material of the contact layer 60c includes a metal material other than gold (Au) and copper (Cu), and accordingly, during the subsequent manufacturing process, metals such as tin (Sn) in the package solder diffuse into the light emitting device 7. , it is possible to prevent structural deformation of the light emitting device 7 by forming a eutectic with metal materials, such as gold (Au) and copper (Cu), in the light emitting device 7.

In one embodiment of the present invention, the material of the contact layer 60c includes a metal with high reflectivity, such as aluminum (Al) or platinum (Pt).

In one embodiment of the present invention, in order to increase the bonding strength between the contact layer 60c and the first semiconductor layer 101c, one side of the contact layer 60c in contact with the first semiconductor layer 101c is chromium (Cr). ) or titanium (Ti).

In an embodiment of the present invention, following the contact layer forming step in FIGS. 31A and 31B, the method of manufacturing the light emitting device 7 includes a third insulating layer forming step, as shown in the top view of FIG. 32A and A-A in FIG. 32A. As shown in FIG. 32b, which is a cross-sectional view along the line, the third insulating layer 70c is formed on the semiconductor structure 1000c by a method such as physical vapor deposition or chemical vapor deposition, and the third insulating layer 70c is formed by lithography or etching. The insulating layer 70c is patterned to form third insulating layer openings 701c and 702c to expose the first contact layer 601c and the second contact layer 602c, respectively; forming a first portion 7011c of the third insulating layer 70c surrounded by the third insulating layer opening 701c; forming a second portion 7022c of the third insulating layer 70c surrounded by the third insulating layer opening 702c; A connecting portion 7000c of the third insulating layer 70c is formed between the third insulating layer opening 701c and the third insulating layer opening 702c. As shown in FIG. 32A, the connecting portion 7000c of the third insulating layer 70c surrounds the first portion 7011c and the second portion 7022c of the third insulating layer 70c, respectively. As shown in FIG. 32b, the connection portion 7000c of the third insulating layer 70c is located on both sides of the first portion 7011c of the third insulating layer 70c, and the connection portion 7000c of the third insulating layer 70c The portion 7000c is located on both sides of the second portion 7022c of the third insulating layer 70c. The third insulating layer opening 701c is formed by the first side 70111 of the first portion 7011c of the third insulating layer 70c and the side 70001 of the connecting portion 7000c of the third insulating layer 70c. Constructed, the third insulating layer opening 702c is formed on the second side 70222c of the second portion 7022c of the third insulating layer 70c and the other side of the connecting portion 7000c of the third insulating layer 70c. It consists of (70002c).

In one embodiment of the present invention, the first contact layer 601c located on the second semiconductor layer 102c is interposed between the second insulating layer 50c and the third insulating layer 70c. The fin area 600c is surrounded and covered by the connecting portion 7000c of the third insulating layer 70c.

In one embodiment of the present invention, as shown in FIG. 32A, the third insulating layer openings 701c and 702c and the plurality of hole portions 100c are staggered and do not overlap each other. In other words, the third insulating layer opening 701c and the second insulating layer opening 501c are staggered and do not overlap each other. The third insulating layer opening 702c may be surrounded by the second insulating layer opening 502c. In the plan view of FIG. 32A, the third insulating layer openings 701c and 702c are on both sides of the center line C-C' of the substrate 11c, for example, the third insulating layer opening 701c is on the right side of the center line C-C' of the substrate 11c. and the third insulating layer opening 702c is located on the left side of the center line C-C' of the substrate 11c.

In one embodiment of the present invention, the third insulating layer opening 701c has a width smaller than the width of the second insulating layer opening 501c, and the third insulating layer opening 702c has a width smaller than the width of the second insulating layer opening 502c. It has a width smaller than the width of .

In one embodiment of the present invention, the third insulating layer opening 701c has a width greater than the width of the second insulating layer opening 501c, and the third insulating layer opening 702c has a width greater than the width of the second insulating layer opening 502c. It has a width greater than the width of .

The third insulating layer 70c may have a single-layer or laminated structure. When the third insulating layer 70c has a laminated structure, the third insulating layer 70c is made by alternately stacking two or more materials with different refractive indices to form a Bregg reflector (DBR) structure, which selectively transmits light of a specific wavelength. It can be reflected. The third insulating layer 70c is formed of a non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin, cyclic olefin polymer ( Organic materials such as COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone, Includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

Following the third insulating layer forming step, the manufacturing method of the light emitting device 7 includes a bonding pad forming step. As shown in the plan view of FIG. 33A and in FIG. 33B, which is a cross-sectional view taken along line A-A' of FIG. 33A, first bonding on one or more semiconductor structures 1000c by electroplating, physical vapor deposition, or chemical vapor deposition. A pad 80c and a second bonding pad 90c are formed. In the plan view of FIG. 33A, the first bonding pad 80c is close to one side of the substrate 11c, for example, to the right of the center line C-C' of the substrate 11c, and the second bonding pad 90c is adjacent to the substrate 11c. The other side, for example, is close to the left side of the center line C-C' of the substrate 11c. The first bonding pad 80c covers the third insulating layer opening 701c, contacts the first contact layer 601c, and forms the first semiconductor layer ( 101c) and forms an electrical connection. The second bonding pad 90c covers the third insulating layer opening 702c, contacts the second contact layer 602c, and connects the second contact layer 602c, the reflective layer 40c, or the barrier layer 41c. An electrical connection is formed with the second semiconductor layer 102c. As shown in FIG. 33A, the first bonding pad 80c and the second bonding pad 90c do not cover all of the hole portion 100c, and the hole portion 100c covers the first bonding pad 80c and the second bonding pad. It is formed in an area other than the pad 90c.

In one embodiment of the present invention, the first bonding pad 80c has a size that is the same as or different from that of the second bonding pad 90c, and the size may be a width or an area.

In one embodiment of the present invention, as shown in Figure 33b, the first bonding pad 80c includes a side side 801c, and the side side 801c of the first bonding pad 80c and the third insulating layer ( The first side 70111 of the first part 7011c of 70c) or the side 70001 of the connecting part 7000c of the third insulating layer 70c are spaced apart from each other at a distance, and the distance is less than 100 μm. Preferred, smaller than 50 μm is more preferred, and smaller than 20 μm is most preferred. The second bonding pad 90c includes a side side 902c, and the side side 902c of the second bonding pad 90c is the second side 70222c of the second portion 7022c of the third insulating layer 70c. Or, it is spaced apart from the other side 70002c of the connecting portion 7000c of the third insulating layer 70c at a distance, and the distance is preferably less than 100 μm, more preferably less than 50 μm, and less than 20 μm. It is most desirable.

In one embodiment of the present invention, on the top view of the light emitting device 7, the side edge 801c of the first bonding pad 80c is disposed along the side sides 70001 and 70111 of the third insulating layer opening 701c, The side edge 902c of the second bonding pad 90c is disposed along the side sides 70002c and 70222c of the third insulating layer opening 702c.

FIG. 33A is a plan view of the light-emitting device 7, and FIG. 33B is a cross-sectional view of the light-emitting device 7. The light emitting device 7 disclosed in this embodiment is a flip chip type light emitting diode device. The light emitting element 7 includes a substrate 11c; One or more semiconductor structures (1000c) located on the substrate (11c); a surrounding portion (111c) surrounding one or more semiconductor structures (1000c); and a first bonding pad 80c and a second bonding pad 90c located on the semiconductor stack 10c. The one or more semiconductor structures 1000c each include a semiconductor stack 10c, and the semiconductor stack 10c includes a first semiconductor layer 101c, a second semiconductor layer 102c, and a first semiconductor layer 101c and a second semiconductor layer 102c. It includes an active layer 103c located between the semiconductor layers 102c.

As shown in FIGS. 33A and 33B, the periphery of one or more semiconductor structures 1000c is surrounded by a surrounding portion 111c. In one embodiment of the present invention, the plurality of semiconductor structures 1000c are connected to each other by the first semiconductor layer 101c, and the surrounding portion 111c is a first semiconductor structure surrounding the plurality of semiconductor structures 1000c. and a first surface 1011c of layer 101c. In another embodiment of the present invention, the plurality of semiconductor structures 1000c are separated from each other and spaced apart from each other to expose the surface 11s of the substrate 11c.

The light emitting device 7 further includes one or more hole portions 100c that penetrate the second semiconductor layer 102c and the active layer 103c and expose one or more second surfaces 1012c of the first semiconductor layer 101c. .

The light emitting element 7 is formed on the first surface 1011c of the first semiconductor layer 101c, surrounds the periphery of the semiconductor structure 1000c, and forms an electrical connection by contacting the first semiconductor layer 101c. , Also, a first contact layer formed on one or more second surfaces 1012c of the first semiconductor layer 101c and covering one or more hole portions 100c and contacting the first semiconductor layer 101c to form an electrical connection. (601c); and a second contact layer 602c formed on the surface 102s of the second semiconductor layer 102c. In one embodiment of the present invention, as shown in FIG. 31A, which is a top view of the light emitting device 7, the first contact layer 601c surrounds a plurality of side walls of the second contact layer 602c.

In one embodiment of the present invention, the first bonding pad 80c and/or the second bonding pad 90c cover a plurality of semiconductor structures 1000c.

In one embodiment of the present invention, the formation position of the first bonding pad 80c and the second bonding pad 90c avoids the formation position of the hole portion 100c, and the formation position of the first bonding pad 80c and the second bonding pad 90c is The formation position of (90c) does not overlap with the formation position of the hole portion (100c).

In one embodiment of the present invention, on the top view of the light emitting device 7, the shape of the first bonding pad 80c and the shape of the second bonding pad 90c are the same, and as shown in FIG. 33A, for example, the shape of the second bonding pad 80c is the same. The shape of the first bonding pad 80c and the second bonding pad 90c is rectangular.

In one embodiment of the present invention, the size of the first bonding pad 80c and the size of the second bonding pad 90c are different, for example, the area of the first bonding pad 80c is greater than that of the second bonding pad 90c. Larger or smaller than area. The material of the first bonding pad 80c and the second bonding pad 90c includes metal, and the metal material is, for example, chromium (Cr), titanium (Ti), wolfram (W), aluminum (Al), and indium ( It is a metal such as In), tin (Sn), nickel (Ni), and platinum (Pt) or an alloy thereof. The first bonding pad 80c and the second bonding pad 90c may have a single-layer or laminated structure. When the first bonding pad 80c and the second bonding pad 90c have a stacked structure, the first bonding pad 80c includes a first upper bonding pad and a first lower bonding pad, and the second bonding pad 90c ) includes a second upper layer bonding pad and a second lower layer bonding pad. The upper layer bonding pad and the lower layer bonding pad each include different functions.

In one embodiment of the present invention, the function of the upper bonding pad is primarily to weld and form lead lines. By means of the upper bonding pad, the light emitting device 7 is mounted on the package substrate in a flip chip format using solder or Au-Sn eutectic bonding. The metal material of the upper bonding pad includes a highly ductile material, and the highly ductile material is, for example, tin (Sn), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), and copper (Cu). , gold (Au), wolfram (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh). , iridium (Ir), ruthenium (Ru), osmium (Os), etc., or alloys thereof. The upper bonding pad may have a single-layer or laminated structure of the above materials. In an embodiment of the present invention, the material of the upper bonding pad includes nickel (Ni) and/or gold (Au), and the upper bonding pad has a single layer or laminated structure.

In one embodiment of the present invention, the function of the lower bonding pad is to form a stable interface with the contact layer 60c, the reflective layer 40c, or the barrier layer 41c, for example, the first lower bonding pad and the first contact layer. The interfacial bonding strength of 601c is improved or the interfacial bonding strength of the second lower layer bonding pad and the reflective layer 40c or the barrier layer 41c is improved. Another function of the lower layer bonding pad is to prevent tin (Sn) in the solder or Au-Sn fixation from diffusing into the reflective structure and damaging the reflectivity of the reflective structure. Therefore, the lower layer bonding pad is made of metal materials other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), and zirconium (Zr). , molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os) etc., metals or alloys thereof, and the lower layer bonding pad may have a single layer or laminated structure of the above materials. In one embodiment of the present invention, the lower layer bonding pad includes a titanium (Ti)/aluminum (Al) stacked structure, or a chromium (Cr)/aluminum (Al) stacked structure.

In one embodiment of the present invention, this is to prevent tin (Sn) from diffusing into the reflective structure during the solder or Au-Sn process and damaging the reflectance of the reflective structure. Accordingly, one side where the first contact layer 601c and the first bonding pad 80c are connected includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt). One side where the second contact layer 602c and the second bonding pad 90c are connected includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt).

FIG. 34A is a plan view of the light-emitting device 8 in an embodiment of the present invention, and FIG. 34B is a cross-sectional view of the light-emitting device 8. When comparing the light emitting device 8 with the light emitting device 7 of the above embodiment, the light emitting device 8 has a metal layer surrounding a plurality of side walls of the first bonding pad 80d and/or the second bonding pad 90d ( 900d) and a first electrode block 810d and a second electrode block 910d located above the first bonding pad 80d and the second bonding pad 90d, respectively. In addition, since the light-emitting device 8 and the light-emitting device 7 have almost the same structure, the light-emitting device 8 in FIGS. 34A and 34B and the light-emitting device 7 in FIGS. 33A and 33B have the same names and symbols. Since they have a structure, represent the same structure, have the same material, or have the same function, descriptions are omitted or not appropriately provided here.

The light emitting device 8 disclosed in this embodiment is a flip chip type light emitting diode device. The light emitting element 8 includes a substrate 11c; One or more semiconductor structures (1000c) located on the substrate (11c); a surrounding portion (111c) surrounding one or more semiconductor structures (1000c); A first bonding pad (80d) and a second bonding pad (90d) located on the semiconductor stack (10c); and a first electrode block 810d and a second electrode block 910d located above the first bonding pad 80d and the second bonding pad 90d, respectively. Each of the one or more semiconductor structures 1000c includes a semiconductor stack 10c, and the semiconductor stack 10c includes a first semiconductor layer 101c, a second semiconductor layer 102c, and a first semiconductor layer 101c and a second semiconductor layer 102c. It includes an active layer 103c located between the semiconductor layers 102c.

As shown in FIGS. 34A and 34B, the periphery of one or more semiconductor structures 1000c is surrounded by a surrounding portion 111c. In one embodiment of the present invention, the plurality of semiconductor structures 1000c may be connected to each other by the first semiconductor layer 101c, and the surrounding portion 111c may be a first layer surrounding the plurality of semiconductor structures 1000c. It includes a first surface 1011c of the semiconductor layer 101c. In another embodiment of the present invention, the plurality of semiconductor structures 1000c are separated from each other and spaced apart from each other to expose the surface 11s of the substrate 11c.

The light emitting device 8 further includes one or more hole portions 100c that penetrate the second semiconductor layer 102c and the active layer 103c and expose one or more second surfaces 1012c of the first semiconductor layer 101c. .

The light emitting element 8 is formed on the first surface 1011c of the first semiconductor layer 101c, surrounds the periphery of the semiconductor structure 1000c, and forms an electrical connection by contacting the first semiconductor layer 101c. , Also, a first contact layer formed on one or more second surfaces 1012c of the first semiconductor layer 101c and covering one or more hole portions 100c and contacting the first semiconductor layer 101c to form an electrical connection. (601c); and a second contact layer 602c formed on the surface 102s of the second semiconductor layer 102c to form an electrical connection with the second semiconductor layer 102c. In one embodiment of the present invention, on the top view of the light emitting device 2, the first contact layer 601c surrounds a plurality of side walls of the second contact layer 602c, and the second contact layer 602c is connected to the first contact layer 602c. It has a size (eg, area) smaller than the size of the contact layer 601c.

In one embodiment of the present invention, the first bonding pad 80d partially or entirely covers the hole portion 100c and/or the second bonding pad 90d partially or entirely covers the hole portion 100c. As shown in FIG. 34A, the first bonding pad 80d covers a partial hole portion 100c, and the second bonding pad 90d does not cover all of the hole portion 100c.

When a light emitting device is mounted on a package substrate in a flip chip format, the insulating layer on the surface of the light emitting device is easily damaged by impact of external force, so solder or AuSn material of eutectic bonding is used to prevent the light emitting device from cracking the insulating layer. enters the inside, causing malfunction of the light emitting element. In one embodiment of the present invention, the light emitting device 8 includes a metal layer 900d located on the semiconductor stack 10c to protect the lower insulating layer, thereby preventing the insulating layer from being damaged by impact of external force. do. As shown in FIG. 34A, the metal layer 900d surrounds a plurality of side walls of the second bonding pad 90d, and the metal layer 900d and the second bonding pad 90d are spaced apart from each other. The metal layer 900d covers the partial hole portion 100c, and a portion of the first contact layer 601c is located below the metal layer 900d and is insulated from the metal layer 900d by the third insulating layer 70c.

In one embodiment of the present invention, the first bonding pad 80d, the second bonding pad 90d, and the metal layer 900d are spaced apart from each other and are not connected to each other.

In an embodiment of the present invention, the light emitting device 8 includes a third insulating layer 70c, and the third insulating layer 70c exposes the first contact layer 601c and the second contact layer 602c. It includes one or more openings 701c and 702c, and there is a gap between the metal layer 900d and the second bonding pad 90d to expose a partial surface of the third insulating layer 70c.

In one embodiment of the present invention, on the top view of the light emitting device 8, the shape of the first bonding pad 80d and the shape of the second bonding pad 90d are different, for example, the shape of the first bonding pad 80d is rectangular, and the shape of the second bonding pad 90d is comb-shaped.

In one embodiment of the present invention, on the top view of the light emitting device 8, the first bonding pad 80d has a size (eg, area) that is different from the size of the second bonding pad 90d.

In one embodiment of the present invention, the sizes of the first bonding pad 80d and the second bonding pad 90d are different from the sizes of the first electrode block 810d and the second electrode block 910d, respectively, for example, 1 The area of the bonding pad 80d is larger than the area of the first electrode block 810d, and the area of the second bonding pad 90d is larger than the area of the second electrode block 910d.

In one embodiment of the present invention, the distance between the first bonding pad 80d and the second bonding pad 90d is smaller than the distance between the first electrode block 810d and the second electrode block 910d.

In one embodiment of the present invention, on the top view of the light emitting device 8, the shape of the first electrode block 810d is close to or the same as the shape of the second electrode block 910d, for example, the first electrode block 810d And the shape of the second electrode block 910d is a comb shape, and as shown in Figure 10c, the first electrode block 810d has a plurality of first convex portions 811d and a plurality of first concave portions alternately connected to each other. Includes part 812d. The second electrode block 910d includes a plurality of second convex portions 911d and a plurality of second concave portions 912d alternately connected to each other. The position of the first concave portion 812d of the first electrode block 810d and the position of the second concave portion 912d of the second electrode block 910d substantially correspond to the position of the hole portion 100c. In other words, the width of the first concave portion 812d of the first electrode block 810d or the width of the second concave portion 912d of the second electrode block 910d is larger than the diameters of all hole portions 100c, and The first electrode block 810d and the second electrode block 910d do not cover all of the hole portions 100c, and the first concave portion 812d of the first electrode block 810d and the first concave portion 812d of the second electrode block 910d 2 The concave portion 912d is formed around the hole portion 100c while avoiding the hole portion 100c. In one embodiment of the present invention, the plurality of first recesses 812d are aligned substantially parallel with the plurality of second recesses 912d in a plan view. In another embodiment of the present invention, the plurality of first recesses 812d are arranged to be offset from the plurality of second recesses 912d in the plan view.

In one embodiment of the present invention, when the light emitting device 8 is mounted on a package substrate in a flip chip format, a multi-layer insulation is formed between the first bonding pad 80d, the second bonding pad 90d, and the semiconductor stack 10c. It includes a layer, and the first bonding pad 80d and the second bonding pad 90d of the light emitting device 8 are caused by external force, for example, by stress generated during solder or Au-Sn process bonding (eutectic bonding), Since cracks occur in the first bonding pad (80d), the second bonding pad (90d) and the insulating layer, the light emitting element (8) is located above the first bonding pad (80d) and the second bonding pad (90d), respectively. It includes a first electrode block 810d and a second electrode block 910d and is connected to the outside by the first electrode block 810d and the second electrode block 910d, and the first electrode block 810d and the second electrode block 910d The formation position of the electrode block 910d avoids the formation position of the hole portion 100c, thereby reducing the occurrence of stress between the bonding pad and the insulating layer due to external force.

In another embodiment of the present invention, compared to the first electrode block 810d and the second electrode block 910d, the pressure during die bonding of the first electrode block 810d and the second electrode block 910d is To emit light, the first bonding pad 80d and the second bonding pad 90d have a relatively large area. In the cross-sectional view of the light emitting device 8, the first bonding pad 80d has a width that is 1.2 to 2.5 times, preferably 2 times, the width of the first electrode block 810d.

In another embodiment of the present invention, compared to the first electrode block 810d and the second electrode block 910d, the pressure during die bonding of the first electrode block 810d and the second electrode block 910d is The first bonding pad 80d and the second bonding pad 90d have a relatively large area to emit light. In the cross-sectional view of the light emitting device 8, the extension distance of the first bonding pad 80d is preferably at least 1 time its own thickness, and preferably at least 2 times its own thickness.

In another embodiment of the present invention, the first electrode block 810d and the second electrode block 910d have a thickness of 1 to 100 μm, preferably 1.5 to 6 μm, and the first electrode block 810d and the second electrode block It is mounted on the package substrate in flip chip format by 910d. The first bonding pad 80d and the second bonding pad 90d have a thickness greater than 0.2 μm to release the pressure during the solid crystal of the first electrode block 810d and the second electrode block 910d, and preferably Larger than 0.5μm and smaller than 1μm.

In another embodiment of the present invention, the first bonding pad 80d, the second bonding pad 90d, and the metal layer 900d include the same metal material and/or the same metal layer.

The first bonding pad 80d, the second bonding pad 90d, and the metal layer 900d may have a single-layer or laminated structure. The function of the first bonding pad 80d and the second bonding pad 90d is to form a stable interface with the first contact layer 601c, the reflective layer 40c, or the barrier layer 41c, for example, the first bonding pad (80d) is in contact with the first contact layer (601c), and the second bonding pad (90d) is in contact with the reflection layer (40c) or the barrier layer (41c). The first bonding pad 80d and the second bonding pad 90d are formed when tin (Sn) during the solder or Au-Sn process diffuses into the light emitting device 8, and the first bonding pad 80d and the second bonding pad ( To prevent eutectic formation with metals such as gold (Au) and copper (Cu) included in 90d), metal materials other than gold (Au) and copper (Cu), such as chromium (Cr) and nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum It includes metals such as (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os), or alloys thereof. The metal layer 900d is made of metal materials other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), Zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), Includes metals such as osmium (Os) or alloys thereof. One side of the metal layer 900d connected to the third insulating layer 70c is chromium (Cr), nickel (Ni), and titanium (Ti) to improve the interfacial bonding strength between the metal layer 900d and the third insulating layer 70c. , or platinum (Pt).

In another embodiment of the present invention, the first bonding pad 80d and/or the second bonding pad 90d have a laminated structure, and the laminated structure occurs when bonding the bonding pads 80d and 90d using a solder or Au-Sn process. It includes a high-ductility layer and a low-ductility layer to prevent cracks from occurring in the insulating layer between the bonding pads 80d and 90d and the semiconductor stack 10a due to the stress. The high ductility layer and the low ductility layer include metals of different Young's modulus.

In another embodiment of the present invention, the high ductility layer of the first bonding pad 80d and/or the second bonding pad 90d has a thickness equal to or greater than the thickness of the low ductility layer.

In another embodiment of the present invention, the first bonding pad 80d and the second bonding pad 90d have a stacked structure, the first electrode block 810d and the second electrode block 910d have a stacked structure, and the first electrode block 810d and the second electrode block 910d have a stacked structure. The surface where the bonding pad 80d and the first electrode block 810d are connected includes the same metal material, and the surface where the second bonding pad 90d and the second electrode block 910d are connected includes the same metal material (e.g. By including chromium (Cr), nickel (Ni), titanium (Ti), or platinum (Pt)), the interfacial bonding strength of the bonding pad and the bumper pad is improved.

In another embodiment of the present invention, the method of manufacturing the light emitting device 8 following the bonding pad forming step includes forming a fourth insulating layer. A fourth insulating layer (not shown) is formed on the first bonding pad 80d and the second bonding pad 90d by a method such as physical vapor deposition or chemical vapor deposition, and the first electrode block 810d and the second electrode block are formed. 910d is formed on the first bonding pad 80d and the second bonding pad 90d, respectively, and the fourth insulating layer surrounds the sidewalls of the first bonding pad 80d and the second bonding pad 90d. . The fourth insulating layer may have a single-layer or laminated structure. When the fourth insulating layer has a laminated structure, two or more materials with different refractive indices are alternately laminated to form a Bragg reflector (DBR) structure, and can selectively reflect light of a specific wavelength. The material of the fourth insulating layer is made of non-conductive material, Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, and cyclic olefin polymer (COC). ), organic materials such as polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and fluorocarbon polymer, or silicone and glass. (Glass), inorganic materials, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In one embodiment of the present invention, the manufacturing process of the first electrode block 810d and the second electrode block 910d may immediately follow the manufacturing process of the first bonding pad 80d and the second bonding pad 90d. . In another embodiment of the present invention, after the manufacturing process of the first bonding pad 80d and the second bonding pad 90d, the forming step of the fourth insulating layer is first performed, and then the first electrode block 810d and the second bonding pad 90d are formed. 2 The manufacturing process of the electrode block 910d proceeds.

Figure 35 is a schematic diagram of a light emitting device according to an embodiment of the present invention. The semiconductor light-emitting device 1, light-emitting device 2, light-emitting device 3, light-emitting device 4, light-emitting device 5, light-emitting device 6, light-emitting device 7, or light-emitting device of the above-described embodiments. (8) is mounted on the first pad 511 and the second pad 512 of the package substrate 51 in a flip chip format. The first pad 511 and the second pad 512 are electrically insulated by an insulating portion 53 containing an insulating material. When mounting the flip chip, one side of the growth substrates 11a and 11b opposite the electrode formation surface is set as the main light extraction surface. In order to increase the light extraction effect of the light emitting device, semiconductor light emitting device (1), light emitting device (2), light emitting device (3), light emitting device (4), light emitting device (5), light emitting device (6), light emitting device ( 7) Alternatively, a reflective structure 54 may be installed around the light emitting element 8.

Figure 36 is a schematic diagram of a light emitting device according to an embodiment of the present invention. The bulb 600 includes a lamp shade 602, a reflector 604, a light emitting module 610, a lamp holder 612, a heat sink 614, a connection part 616, and an electrically connected element 618. Includes. The light emitting module 610 includes a mounting portion 606 and a plurality of light emitting devices 608 located on the mounting portion 606, and the plurality of light emitting devices 608 include the semiconductor light emitting devices 1 of the above-described embodiments, It may be a light-emitting device (2), a light-emitting device (3), a light-emitting device (4), a light-emitting device (5), a light-emitting device (6), a light-emitting device (7), or a light-emitting device (8).

Each embodiment illustrated in the present invention is only for illustrating the present invention and is not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention shall not depart from the spirit and scope of the present invention.

1, 2, 3, 4, 5, 6 light emitting elements
11a, 11b substrate
10a, 10b semiconductor layer
101a, 101b first semiconductor layer
102a, 102b second semiconductor layer
103a, 103b active layer
100a, 100b odd part
102s surface
1011a, 1011b first surface
1012a, 1012b second surface
110a fourth insulating layer
111a, 111b surrounding part
20a, 20b first insulating layer
200a, 200b first insulating layer surrounding area
201a, 201b first insulating layer cover area
202a, 202b first insulating layer opening
203a, 203b first insulating layer opening
30a, 30b transparent conductive layer
300b transparent conductive layer opening
301a, 301b transparent conductive layer outer edge
40a, 40b reflective layer
400b reflective layer opening
401a, 401b reflective layer outer edge
41a, 41b barrier layer
410b barrier layer opening
411a, 411b barrier layer outer edge
50a, 50b second insulating layer
501a, 501b second insulating layer opening
502a, 502b second insulating layer opening
5020b annular aperture
5021b sidewall
60a, 60b contact layer
600a, 600b pin area
602a contact layer opening
601b first contact layer
6011b first contact layer side wall
602b second contact layer
6021b second contact layer side wall
70a, 70b third insulating layer
701a, 702a third insulating layer opening
701b, 702b third insulating layer opening
80a, 80b first bonding pad
90a, 90b second bonding pad
800a first bonding pad opening
801b first convex portion
802a first side
802b first recess
803b 1st flat
804a first recess
805a first upper layer bonding pad
807a First lower layer bonding pad
810a first bumper pad
900a second bonding pad opening
901b second convex portion
902a second side
902b second recess
903b second straight side
904a second recess
905a second upper layer bonding pad
907a second lower layer bonding pad
910a, 910b 2nd bumper pad
1000a, 1000b semiconductor structure
1001a, 1001b second outer wall
1002a, 1002b inner wall
1003a, 1003b first outer wall
51 package substrate
511 1st pad
512 2nd pad
53 insulation part
54 Reflective structure
600 bulbs
602 lamp shade
604 reflector
606 Mounting part
608 light emitting device
610 light emitting module
612 lamp holder
614 heat sink
616 connection
618 electrically connected elements

Claims (10)

In light emitting devices,
It includes a semiconductor stack, a surrounding portion, a plurality of hole portions, a first contact layer, a second contact layer, a first bonding pad, and a second bonding pad,
The semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer;
the surrounding portion surrounds the semiconductor layer and exposes a first surface of the first semiconductor layer;
the plurality of hole portions penetrate the active layer to expose a second surface of the first semiconductor layer;
the first contact layer covers the first semiconductor layer through the surrounding portion and the plurality of hole portions;
the second contact layer is located on the second semiconductor layer and is surrounded by the first contact layer;
the first bonding pad is located on the first contact layer;
The second bonding pad is located on the second contact layer, and in a plan view, the first bonding pad and the second bonding pad are formed in areas other than the positions of the plurality of holes. According to paragraph 1,
The plurality of hole portions include two adjacent hole portions located on the same column, and a first shortest distance is included between the two adjacent hole portions, and the plurality of hole portions further include a hole portion adjacent to an edge of the light emitting device. and a second shortest distance between the hole portion and the first outer wall of the first semiconductor layer, and the first shortest distance is greater than the second shortest distance. According to paragraph 1,
The plurality of hole portions include two adjacent hole portions located on the same column, and a first shortest distance is included between the two adjacent hole portions, and the plurality of hole portions further include a hole portion adjacent to an edge of the light emitting device. and a second shortest distance between the hole portion and the first outer wall of the first semiconductor layer, and the first shortest distance is smaller than the second shortest distance. According to paragraph 1,
The plurality of hole portions include two adjacent hole portions located on the same column, and a first shortest distance is included between the two adjacent hole portions, and the plurality of hole portions further include a hole portion adjacent to an edge of the light emitting device. and a second shortest distance between the hole portion and the first outer wall of the first semiconductor layer, and the first shortest distance is equal to the second shortest distance. According to paragraph 1,
A light emitting device further comprising a first insulating layer covering a sidewall of the active layer, wherein the first insulating layer has a first insulating layer opening to expose the second semiconductor layer. According to clause 5,
A light emitting device further comprising a transparent conductive layer located within the opening of the first insulating layer, wherein an outer edge of the transparent conductive layer is spaced apart from the first insulating layer. According to paragraph 1,
It further includes a reflective layer located on the second semiconductor layer and a barrier layer located on the reflective layer, wherein the outer edge of the barrier layer is located further outside than the outer edge of the reflective layer or is positioned to overlap the outer edge of the reflective layer. Light emitting device. According to paragraph 1,
The first contact layer is not located below the second bonding pad, and the first contact layer and the second contact layer do not overlap each other. According to paragraph 1,
A light emitting device wherein the area included in the first contact layer is larger than the area included in the second contact layer. According to paragraph 1,
A light emitting device wherein the first contact layer includes a metal material other than an alloy.