KR102649177B1 - Gate drivign circuit, display panel and display device - Google Patents

Abstract

Embodiments of the present invention relate to a gate driving circuit, a display panel, and a device, wherein the scan driving circuit arranged on both sides of the display panel is driven by a dual feeding method, and the light emission driving circuit has a buffer transistor arranged horizontally with the signal wire. By operating in a single feeding method in a structured structure, luminance deviation depending on the area of the display panel is prevented, and the bezel area of the display panel can be minimized by reducing the size of the buffer transistor and the width of the light emission driving circuit.

Description

Gate driving circuit, display panel and display device {GATE DRIVIGN CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE}

Embodiments of the present invention relate to a gate driving circuit, a display panel, and a display device.

As the information society develops, the demand for display devices that display images is increasing, and various types of display devices such as liquid crystal display devices and organic light emitting display devices are being utilized.

Among these display devices, organic light emitting display devices provide advantages in response speed, contrast ratio, luminous efficiency, luminance, and viewing angle by using organic light emitting diodes that emit light on their own.

Such an organic light emitting display device includes, for example, a display panel on which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are arranged, a gate driving circuit that drives the plurality of gate lines, and a plurality of data lines. It may include a data driving circuit, a gate driving circuit, and a controller that controls the data driving circuit.

Here, the gate driving circuit may be disposed in the bezel area of the display panel and includes a scan driving circuit that controls the operating timing of the switching transistor in the subpixel, and a light emission driving circuit that controls the operating timing of the light emitting transistor in the subpixel. can do.

Therefore, there are many difficulties in reducing the width of the bezel area of the display panel due to the arrangement of the gate driving circuit.

The purpose of embodiments of the present invention is to provide a gate driving circuit capable of reducing the width of the bezel area of a display panel while preventing luminance deviation within the active area of the display panel, and a display panel and device including the same.

The purpose of embodiments of the present invention is to provide a scan driving circuit, a light emission driving circuit, and a driving method having a structure that can reduce the bezel area of a display panel.

In one aspect, embodiments of the present invention include a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of subpixels disposed, a plurality of scan driving circuits disposed on both sides of the display panel, and both sides of the display panel. It provides a display device that includes a plurality of light emission driving circuits arranged in, and the buffer transistor included in each of the plurality of light emission driving circuits is arranged in the same direction as the direction in which the signal wires arranged in the light emission driving circuit are arranged.

In another aspect, embodiments of the present invention include a plurality of gate lines, a plurality of subpixels driven by the plurality of gate lines and arranged in an active area, a plurality of scan driving circuits arranged on both sides of the active area, and It includes a plurality of light emission driving circuits arranged on both sides of the active area, and a buffer transistor included in each of the plurality of scan driving circuits is arranged in a direction crossing the direction in which the signal wires arranged in the scan driving circuit are arranged. The buffer transistor included in each light emission driving circuit provides a display panel arranged in the same direction as the signal wires arranged in the light emission driving circuit.

In another aspect, embodiments of the present invention correspond to 2K scan driving circuits including a first scan driving circuit, a second scan driving circuit arranged to correspond to the first scan driving circuit, and the first scan driving circuit. It includes a first light emission driving circuit and a second light emission driving circuit arranged to correspond to the first light emission driving circuit, and the buffer transistor included in the first light emission driving circuit and the second light emission driving circuit is connected to the first light emission driving circuit. and a gate driving circuit arranged in the same direction as the direction in which the signal wires arranged in the second light emission driving circuit are arranged.

According to embodiments of the present invention, the scan driving circuit and the light emission driving circuit are arranged on both sides of the display panel, and the buffer transistor disposed in the light emission driving circuit is arranged along the same direction as the signal wire, thereby reducing the width of the light emission driving circuit. By reducing the width of the bezel area of the display panel.

According to embodiments of the present invention, the scan driving circuit is driven by a dual feeding method and the light emission driving circuit is driven by a single feeding method, thereby preventing luminance deviation within the display panel and within the light emission driving circuit. By reducing the size of the buffer transistor, the width of the light emission driving circuit can be reduced.

1 is a diagram showing the schematic configuration of a display device according to embodiments of the present invention.
Figure 2 is a diagram showing an example of a circuit structure of a subpixel included in a display device according to embodiments of the present invention.
Figure 3 is a diagram showing an example of a gate driving circuit included in a display device according to embodiments of the present invention.
Figure 4 is a diagram showing another example of a gate driving circuit included in a display device according to embodiments of the present invention.
FIG. 5 is a diagram showing an example of the arrangement structure of circuit elements in the light emission driving circuit shown in FIG. 4.
Figure 6 is a diagram showing another example of a gate driving circuit included in a display device according to embodiments of the present invention.
Figure 7 is a diagram showing another example of a gate driving circuit included in a display device according to embodiments of the present invention.
FIG. 8 is a diagram showing an example of the arrangement structure of circuit elements in the light emission driving circuit shown in FIGS. 6 and 7.
FIG. 9 is a diagram showing an example of a structure in which a logic transistor and a buffer transistor are arranged within the light emission driving circuit shown in FIG. 7.
FIG. 10 is a diagram showing an example of the arrangement structure of circuit elements in the light emission driving circuit shown in FIG. 9.
FIG. 11 is a diagram showing another example of a structure in which a logic transistor and a buffer transistor are arranged within the light emission driving circuit shown in FIG. 7.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the essence, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

Figure 1 is a diagram showing the schematic configuration of a display device 100 according to embodiments of the present invention.

Referring to FIG. 1, the display device 100 according to embodiments of the present invention includes a display panel 110 in which a plurality of subpixels (SP) including light-emitting elements are arranged, and driving the display panel 110. It may include a gate driving circuit 120, a data driving circuit 130, and a controller 140.

In the display panel 110, a plurality of gate lines (GL) and a plurality of data lines (DL) are arranged, and a subpixel (SP) is arranged in an area where the gate line (GL) and the data line (DL) intersect. . Each of these subpixels (SP) may include a light emitting element, and two or more subpixels (SP) may constitute one pixel.

The gate driving circuit 120 is controlled by the controller 140 and sequentially outputs scan signals to the plurality of gate lines GL disposed on the display panel 110 to determine the driving timing of the plurality of subpixels SP. control.

Additionally, the gate driving circuit 120 may output a light emission signal that controls the light emission timing of the light emitting device included in the subpixel SP. The circuit that outputs the scan signal and the circuit that outputs the light emission signal may be implemented integrally or separately.

The gate driving circuit 120 may include one or more gate driver integrated circuits (GDIC, Gate Driver Integrated Circuit), and may be located on only one side or both sides of the display panel 110 depending on the driving method. . Additionally, the gate driving circuit 120 may be implemented in the form of a Gate In Panel (GIP) disposed in the bezel area of the display panel 110.

The data driving circuit 130 receives image data from the controller 140 and converts the image data into an analog data voltage. Then, the data voltage is output to each data line (DL) in accordance with the timing when the scan signal is applied through the gate line (GL), so that each subpixel (SP) expresses brightness according to the image data.

The data driving circuit 130 may include one or more source driver integrated circuits (SDIC).

The controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130.

The controller 140 causes the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and converts the externally received image data to fit the data signal format used by the data driving circuit 130. The converted image data is output to the data driving circuit 130.

The controller 140 externally sends various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE, Data Enable), and a clock signal (CLK) along with video data. Receive from (e.g. host system).

The controller 140 may generate various control signals using various timing signals received from the outside and output them to the gate driving circuit 120 and the data driving circuit 130.

As an example, the controller 140 uses a gate start pulse (GSP, Gate Start Pulse), a gate shift clock (GSC), and a gate output enable signal (GOE, Outputs various gate control signals (GCS) including Gate Output Enable.

Here, the gate start pulse (GSP) controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 120. The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal. The gate output enable signal (GOE) specifies timing information for one or more gate driver integrated circuits.

In addition, the controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE) to control the data driving circuit 130. Outputs various data control signals (DCS) including Output Enable.

Here, the source start pulse (SSP) controls the data sampling start timing of one or more source driver integrated circuits constituting the data driving circuit 130. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data in each source driver integrated circuit. The source output enable signal (SOE) controls the output timing of the data driving circuit 130.

This display device 100 supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc., or has a power management integrated circuit that controls the various voltages or currents to be supplied. More may be included.

In the display panel 110, in addition to the gate line (GL) and data line (DL), voltage lines to which various signals or voltages may be supplied may be disposed, and each subpixel (SP) may include a light emitting element and a transistor for driving the same. etc. may be placed.

FIG. 2 is a diagram illustrating an example of a circuit structure of a subpixel (SP) arranged on the display panel 110 of the display device 100 according to embodiments of the present invention.

Referring to FIG. 2, the subpixels (SP) arranged on the display panel 110 include an organic light-emitting diode (OLED), a plurality of display driving transistors for driving the organic light-emitting diode (OLED), and a storage capacitor (Cst). ) can be placed.

Figure 2 shows an example of a 6T1C structure in which six display driving transistors (T1, T2, T3, T4, T5, T6) and one storage capacitor (Cst) are arranged in the subpixel (SP). In addition, SP) can be implemented in various ways depending on the number and connection relationship of circuit elements arranged in the subpixel (SP).

In addition, although the display driving transistor disposed in the subpixel SP is of the P type as an example, the subpixel SP may be composed of an N type display driving transistor.

The first transistor T1 may be electrically connected between the data driving circuit 130 that supplies the data voltage and the storage capacitor Cst. And, it can be controlled by a scan signal supplied through the gate line (GL).

The first transistor T1 causes the data voltage supplied from the data driving circuit 130 to be applied to one surface of the storage capacitor Cst when a turn-on level scan signal is applied through the gate line GL.

This first transistor T1 is also called a switching transistor because it controls the timing at which the data voltage is applied to the storage capacitor Cst.

The second transistor T2 may be electrically connected between the line to which the driving voltage VDD is supplied and the fifth transistor T5. Additionally, the gate electrode of the second transistor T2 may be electrically connected to the storage capacitor Cst.

This second transistor (T2) is also called a driving transistor, and controls the current flowing through the organic light-emitting diode (OLED) according to the voltage applied to the gate electrode of the second transistor (T2) to adjust the brightness displayed by the organic light-emitting diode (OLED). You can control it.

The third transistor T3 may be electrically connected between the gate electrode and the drain electrode or source electrode of the second transistor T2. Additionally, the third transistor T3 can be controlled by a scan signal supplied through the gate line GL.

This third transistor T3 is used to compensate for the threshold voltage of the second transistor T2, and is also called a compensation transistor.

That is, the second transistor T2 is a driving transistor and must control the current flowing through the organic light emitting diode (OLED) according to the data voltage applied to the subpixel (SP). However, the second transistor T2 disposed in each subpixel (SP) Due to the deviation of the threshold voltage of (T2), the organic light emitting diode (OLED) disposed in each subpixel (SP) may not display the desired brightness.

Accordingly, the threshold voltage of the second transistor T2 disposed in each subpixel SP can be compensated through the third transistor T3.

For example, when a scan signal that turns on the third transistor (T3) is applied through the gate line (GL), the voltage obtained by subtracting the threshold voltage of the second transistor (T2) from the driving voltage (VDD) is applied to the second transistor (T3). It is applied to the gate electrode of (T2).

By allowing the data voltage to be applied to one side of the storage capacitor (Cst) while the driving voltage (VDD) with the reduced threshold voltage is applied to the gate electrode of the second transistor (T2), the threshold voltage of the second transistor (T2) Ensure that compensation is provided.

Here, the first transistor T1, which controls the application of the data voltage to one surface of the storage capacitor Cst, and the third transistor T3, which performs threshold voltage compensation of the second transistor T2, have the same gate line GL. ) may be controlled by a scan signal supplied to the other gate line (GL).

In this way, by compensating for the deviation in the threshold voltage of the second transistor T2 through the third transistor T3, the deviation in luminance shown by the subpixel SP due to the difference in the threshold voltage of the second transistor T2 is reduced. Make it possible to prevent it.

The fourth transistor T4 may be electrically connected between the storage capacitor Cst and the line to which the reference voltage Vref is supplied. Also, the fourth transistor T4 can be controlled by the light emission signal supplied through the gate line GL.

This fourth transistor T4 initializes the voltage on one side of the storage capacitor Cst when a turn-on level light emission signal is applied through the gate line GL, or stores the data applied to one side of the storage capacitor Cst. The voltage can be slowly discharged and the current according to the data voltage can flow to the organic light emitting diode (OLED).

The fifth transistor T5 is electrically connected between the second transistor T2 and the organic light emitting diode (OLED). And, the fifth transistor T5 can be controlled by the light emission signal supplied through the gate line GL.

The fifth transistor (T5) turns - with the data voltage applied to one side of the storage capacitor (Cst) and the driving voltage (VDD) with threshold voltage compensation applied to the gate electrode of the second transistor (T2). When an on-level light emitting signal is applied, it is turned on to allow current to flow through the organic light emitting diode (OLED).

These fourth transistors (T4) and fifth transistors (T5) control the light emission timing of the organic light emitting diode (OLED), so they are also called light emitting transistors.

The sixth transistor T6 may be electrically connected between a line to which the reference voltage Vref is supplied and the anode electrode of the organic light emitting diode (OLED). And, it can be controlled by a scan signal supplied through the gate line (GL).

When a scan signal at the turn-on level is applied through the gate line GL, the sixth transistor T6 applies the reference voltage Vref to the anode electrode of the organic light emitting diode (OLED) or the second transistor T2 and the second transistor T2. 5 The node between transistors (T5) can be initialized.

In this way, the display driving transistor disposed in the subpixel (SP) operates by a scan signal and a light emission signal, and allows current according to the data voltage to flow to the organic light emitting diode (OLED), so that the subpixel (SP) generates image data. It allows the brightness to be displayed according to .

A scan signal or a light emission signal that controls the operation timing of the transistor disposed in the subpixel SP may be output by the gate driving circuit 120 disposed on one side of the display panel 110.

FIG. 3 is a diagram illustrating an example of the gate driving circuit 120 included in the display device 100 according to embodiments of the present invention.

Referring to FIG. 3, the gate driving circuit 120 according to embodiments of the present invention may be disposed on one side of the display panel 110.

In addition, the gate driving circuit 120 includes a plurality of scan driving circuits (SDC) that output scan signals through switching transistors disposed in the subpixel (SP), and emit light through light emitting transistors disposed in the subpixel (SP). It may include a plurality of light emission driving circuits (EDC) that output signals.

Each of these multiple scan driving circuits (SDC) and multiple light emission driving circuits (EDC) may be arranged to correspond to one subpixel (SP) line.

Alternatively, each of the plurality of scan driving circuits (SDC) may be arranged to correspond to one subpixel (SP) line, and each of the plurality of emission driving circuits (EDC) may be arranged to correspond to two or more subpixel (SP) lines. there is.

Each of the plurality of scan driving circuits (SDC) and the plurality of light emission driving circuits (EDC) may include circuit elements such as a plurality of transistors and capacitors for outputting scan signals or light emission signals.

As an example, looking at the first light emission driving circuit (EDC1) as an example, the first light emission driving circuit (EDC1) includes a buffer transistor group (BTG) that controls the output of the light emission signal, and a gate electrode of the buffer transistor (BT). It may include a logic transistor (LTG) that controls the voltage level.

The buffer transistor group (BTG) includes a first buffer transistor (BT1) that controls the output of a turn-on level light emitting signal to the gate line (GL), and a first buffer transistor (BT1) that controls the output of a turn-off level light emitting signal to the gate line (GL). It may include a second buffer transistor (BT2) that controls .

The first buffer transistor BT1 is controlled by the voltage level of the Q node, and, for example, can control output of the gate low voltage VGL to the gate line GL. In addition, the second buffer transistor BT2 is controlled by the voltage level of the Qb node, and, for example, can control output of the gate high voltage VGH to the gate line GL.

The voltage levels of the Q node and Qb node, which control the on-off of the buffer transistor (BT), can be controlled by a plurality of logic transistors (LT) included in the logic transistor group (LTG).

That is, the plurality of logic transistors (LT) included in the logic transistor group (LTG) are turned on and off by the start signal (VST), clock signal (CLK), etc. input to the first light emission driving circuit (EDC1) and are connected to the Q node and Controls the voltage level of the Qb node. Here, two or more clock signals CLK having different phases may be used, and the gate driving circuit 120 shown in FIG. 3 may be used when two clock signals CLK are used. is shown as an example, but is not limited thereto.

Also, by controlling the voltage levels of the Q node and Qb node, a light emitting signal having a low level or high level is output to the gate line GL through the buffer transistor BT.

Here, the multiple logic transistors (LT) constituting the logic transistor group (LTG) may be implemented in various ways. Additionally, the scan driving circuit (SDC) may also be composed of a logic transistor group (LTG) and a buffer transistor group (BTG), similar to the emission driving circuit (EDC).

In this way, the scan driving circuit (SDC) and the light emission driving circuit (EDC) supply scan signals or light emission signals to the subpixels (SP) and control the operation timing of each subpixel (SP).

At this time, when the gate driving circuit 120 is disposed on only one side of the display panel 110, the load increases as the distance from the gate driving circuit 120 increases, which may cause a luminance deviation within the display panel 110.

Embodiments of the present invention arrange the scan driving circuit (SDC) and the light emission driving circuit (EDC) on both sides of the display panel 110 and supply the scan signal and the light emission signal to the subpixel (SP), so that the display panel ( 110) to prevent luminance deviation within the range.

FIG. 4 is a diagram showing another example of the gate driving circuit 120 included in the display device 100 according to embodiments of the present invention.

Referring to FIG. 4, the gate driving circuit 120 according to embodiments of the present invention includes a plurality of scan driving circuits (SDC) and a plurality of emission driving circuits (EDC) disposed on both sides of the display panel 110. It can be included.

The plurality of scan driving circuits (SDC) are a plurality of first scan driving circuits (SDC11, SDC21, SDC31, SDC41, SDC51, SDC61, SDC71, SDC81, hereinafter referred to as “SDC1”) disposed on one side of the display panel 110. ), and a plurality of second scan driving circuits (SDC12, SDC22, SDC32, SDC42, SDC52, SDC62, SDC72, SDC82, hereinafter, arranged to correspond to the first scan driving circuit (SDC1) on the other side of the display panel 110. SDC2") may be included.

Additionally, the first scan driving circuit (SDC1) and the second scan driving circuit (SDC2) may supply scan signals to the same subpixel (SP) line.

The plurality of light emission driving circuits (EDC) include a plurality of first light emission driving circuits (EDC11, EDC21, EDC31, EDC41, hereinafter referred to as “EDC1”) disposed on one side of the display panel 110, and the display panel 110. It may include a plurality of second light emission driving circuits (EDC12, EDC22, EDC32, EDC42, hereinafter referred to as “EDC2”) arranged to correspond to the first light emission driving circuit (EDCX1) on the other side of .

Here, one light emission driving circuit (EDC) can be arranged to correspond to two scan driving circuits (SDC) (2 stage design).

In addition, the first light emission driving circuit (EDC1) and the second light emission driving circuit (EDC2) can supply a light emission signal through the same subpixel (SP) line and can supply light emission signals through two subpixel (SP) lines. .

Therefore, after the application of the data voltage to the subpixel SP according to the scan signal supplied by the scan driving circuit (SDC) disposed on both sides of the display panel 110 is completed, the two A light emitting signal is sequentially supplied for each subpixel (SP) line, so that the subpixel (SP) can emit light.

In this way, the scan driving circuit (SDC) and the light emission driving circuit (EDC) are placed on both sides of the display panel 110 and the scan signal and the light emission signal are supplied through a dual feeding method, thereby increasing the luminance according to the area of the display panel 110. Deviations can be prevented.

FIG. 5 is a diagram showing an example of the arrangement structure of circuit elements in the light emission driving circuit (EDC) shown in FIG. 4.

Referring to FIG. 5, the light emission driving circuit (EDC) according to embodiments of the present invention includes a buffer transistor (BT) that controls the output of the light emission signal, and a logic transistor (BT) that controls the voltage levels of the Q node and Qb node. LT) may be included.

Here, the gate (Gate) represents the gate electrode of the transistor disposed in the light emission driving circuit (EDC), and the source/drain (S/D) represents the source/drain electrodes of the transistor or wiring to which various signals/voltages are applied. Additionally, Active represents the channel area of the transistor, and the capacitor electrode (CE) represents an electrode that forms a capacitor within the light emission driving circuit (EDC).

As an example, the light emission driving circuit (EDC) may include a plurality of logic transistors (LT1, LT2, LT3, LT4, LT5, LT6, LT7, LT8, LT9) and two buffer transistors (BT1, BT2).

Here, the first logic transistor LT1 is controlled by the second light-emitting clock signal ECLK2 and controls the voltage levels of the fifth logic transistor LT5 and the Q node. The second logic transistor LT2 is controlled by the first emission clock signal ECLK2 and controls the voltage level of the Q node together with the third logic transistor LT3.

The fourth logic transistor LT4 is controlled by the second light-emitting clock signal ECLK2 and controls the third logic transistor LT3.

The fifth logic transistor LT5 controls the sixth logic transistor LT6 and, together with the seventh logic transistor LT7, controls the voltage level of the Qb node. Additionally, the eighth logic transistor LT8 is controlled by the start signal VST supplied when the first logic transistor LT1 is turned on, and controls the voltage level of the Qb node.

The ninth logic transistor LT9 is controlled by the reset signal RESET and initializes the light emission signal output to the gate line GL to the turn-off level.

That is, the plurality of logic transistors (LT) are controlled according to various signals input to the light emission driving circuit (EDC) and control the voltage levels of the Q node and Qb node in the light emission driving circuit (EDC). Figure 5 shows the logic transistors. This shows an example of a structure in which (LT) is arranged, and may be implemented in various ways.

Among the two buffer transistors BT, the first buffer transistor BT1 is controlled by the voltage level of the Q node and outputs a turn-on level light emitting signal to the gate line GL.

Additionally, the second buffer transistor BT2 is controlled by the voltage level of the Qb node and outputs a turn-off level light emission signal to the gate line GL.

Here, embodiments of the present invention are explained by taking the case where the transistor disposed in the subpixel SP is implemented as a P type, so the first buffer transistor BT1 controls the output of the gate low voltage VGL and The second buffer transistor BT2 can control the output of the gate high voltage VGH.

Since the first buffer transistor BT1 and the second buffer transistor BT2 control the light emission signal output to the gate line GL, they may have a larger size than the logic transistor LT.

Therefore, the width of the channel area of the buffer transistor (BT), that is, the width of the buffer transistor (BT) must be above a certain level, so as in the example shown in FIG. 5, the channel area of the buffer transistor (BT) is connected to the signal wiring. It can be separated and arranged in the same direction as.

That is, the buffer transistor (BT) is arranged in a direction that intersects the signal wires arranged in the light emission driving circuit (EDC), and the channel area is separated in the same direction as the signal wires, thereby securing a channel above a certain level.

On the other hand, the width (Wa = 178㎛) of the light emission driving circuit (EDC) may increase depending on the arrangement structure of the buffer transistor (BT). Additionally, among the signal wires arranged in the light emission driving circuit (EDC), signal wires (eg, signal wires to which the gate low voltage (VGL) is applied) may be arranged separately.

In this way, luminance deviation within the display panel 110 can be prevented through dual feeding driving of the scan driving circuit (SDC) and the emission driving circuit (EDC) disposed on both sides of the display panel 110, but the emission driving circuit ( There may be difficulty in reducing the bezel area of the display panel 110 due to the width of the EDC).

Embodiments of the present invention allow the buffer transistor (BT) disposed in the light emission driving circuit (EDC) to be disposed in the same direction as the signal wire disposed in the light emission driving circuit (EDC), thereby It reduces the width and prevents luminance deviation depending on the area of the display panel 110.

FIG. 6 is a diagram showing another example of the gate driving circuit 120 included in the display device 100 according to embodiments of the present invention.

Referring to FIG. 6, the gate driving circuit 120 according to embodiments of the present invention may include a plurality of scan driving circuits (SDC) and a plurality of emission driving circuits (EDC).

The plurality of scan driving circuits (SDC) include a plurality of first scan driving circuits (SDC1) disposed on one side of the display panel 110 and each first scan driving circuit (SDC1) on the other side of the display panel 110. It may include a plurality of second scan driving circuits (SDC2) arranged to correspond to.

And, the first scan driving circuit (SDC1) and the second scan driving circuit (SDC2) corresponding to each other output scan signals through the same subpixel (SP) line.

The plurality of light emission driving circuits (EDC) include a plurality of first light emission driving circuits (EDC1) disposed on one side of the display panel 110 and each first light emission driving circuit (EDC1) on the other side of the display panel 110. It may include a plurality of second light emission driving circuits EDC2 arranged to correspond to.

Additionally, the first and second light emission driving circuits EDC1 and EDC2 corresponding to each other may output scan signals through the same subpixel (SP) line.

Here, each light emission driving circuit (EDC) can be arranged to correspond to four scan driving circuits (SDC) (4 stage design).

Accordingly, the first light emission driving circuit EDC1 and the second light emission driving circuit EDC2 can output light emission signals through the same four subpixel (SP) lines. Also, since the first light emission driving circuit (EDC1) and the second light emission driving circuit (EDC2) output light emission signals through the same subpixel (SP) line, each can receive a separate start signal (VST).

At this time, by arranging the light emission driving circuit (EDC) to correspond to the four scan driving circuits (SDC), placement of the buffer transistor (BT) having the largest size within the light emission driving circuit (EDC) can be facilitated.

For example, the buffer transistor BT disposed in the light emission driving circuit EDC may be disposed in the same direction as the signal wire disposed in the light emission driving circuit EDC.

As the buffer transistor (BT) is arranged in the same direction as the signal wire, it is possible to prevent the source/drain (S/D) protruding from the signal wire from being placed to form the source or drain electrode of the buffer transistor (BT). there is.

That is, the source electrode or drain electrode of the buffer transistor (BT) may be formed integrally with the signal wire or may be formed to overlap the signal wire.

Accordingly, it is possible to prevent the width of the light emission driving circuit (EDC) from increasing due to the buffer transistor (BT) disposed in the light emission driving circuit (EDC).

Additionally, since the channel region of the buffer transistor (BT) can be arranged in one direction without separating it, the buffer transistor (BT) with a wider width than the logic transistor (LT) can be easily arranged.

Also, at least some of the logic transistors LT disposed in the light emission driving circuit EDC may be disposed in a direction that intersects the signal wires disposed in the light emission driving circuit EDC.

In addition, the buffer transistor (BT) disposed in the scan driving circuit (SDC) is designed as a 1-stage scan driving circuit (SDC), so the buffer transistor (BT) of the light emission driving circuit (EDC) designed as a 2-stage It may be arranged in a direction crossing the signal wires arranged in the driving circuit (SDC).

Meanwhile, as the light emission driving circuit (EDC) is designed in 4 stages, the buffer transistor (BT) is arranged in a horizontal direction with the signal wire, which reduces the width of the light emission transistor (EDC), but only one light emission driving circuit is used. The load may increase as the circuit (EDC) supplies the luminous signal to the four subpixel (SP) lines.

Accordingly, the size of the buffer transistor (BT) for outputting the light emitting signal can be increased.

Embodiments of the present invention allow the light emission driving circuit (EDC) disposed on both sides of the display panel 110 to output a light emission signal in a single feeding method, thereby further reducing the width of the light emission driving circuit (EDC).

FIG. 7 is a diagram showing another example of the gate driving circuit 120 included in the display device 100 according to embodiments of the present invention.

Referring to FIG. 7, the gate driving circuit 120 according to embodiments of the present invention includes a plurality of scan driving circuits (SDC) and a plurality of emission driving circuits (EDC) disposed on both sides of the display panel 110. Includes.

The plurality of scan driving circuits (SDC) are disposed on both sides of the display panel 110 such that the first scan driving circuit (SDC1) and the second scan driving circuit (SDC2) correspond to each other, and are connected to the same subpixel (SP) line. Outputs a scan signal.

The plurality of light emission driving circuits (EDC) are arranged to correspond to the first light emission driving circuit (EDC1) disposed on one side of the display panel 110 and the first light emission driving circuit (EDC1) on the other side of the display panel 110. may include a second light emission driving circuit (EDC2).

Additionally, each light emission driving circuit (EDC) can be arranged to correspond to four scan driving circuits (SDC) (4 stage design).

Here, the first light emission driving circuit EDC1 and the second light emission driving circuit EDC2 arranged to correspond to each other may output light emission signals through different subpixel (SP) lines.

For example, when the light emission driving circuit (EDC) is designed in 4 stages, the first light emission driving circuit (EDC1) and the second light emission driving circuit (EDC2) each output a light emission signal to two different subpixel (SP) lines. can do.

Accordingly, the start signal VST can be input only to either the first light emission driving circuit EDC1 or the second light emission driving circuit EDC2, and the start signal ( When VST) is input, the light emission signal output from the first light emission driving circuit (EDC1) may be input as the start signal (VST) of the second light emission driving circuit (EDC2).

The light emission signal output from the light emission driving circuit (EDC) is applied as a turn-on level signal for most of the period for the light emitting element in the subpixel (SP) to emit light, so it does not affect current fluctuations in the subpixel (SP). Therefore, it can be operated in a single feeding method.

In this way, as the light emission driving circuits (EDC) disposed on both sides of the display panel 110 are driven in a single feeding method, the subpixel (SP) line driven by one light emission driving circuit (EDC) is reduced to emit light. The size of the buffer transistor (BT) disposed in the driving circuit (EDC) can be reduced.

Additionally, due to a reduction in the size of the buffer transistor (BT) disposed in the light emission driving circuit (EDC), the width of the light emission driving circuit (EDC) can be reduced, thereby further reducing the width of the bezel area of the display panel 110. .

That is, the scan driving circuit (SDC) disposed on both sides of the display panel 110 operates in a dual feeding method to prevent luminance deviation depending on the area of the display panel 110, and the emission driving circuit (EDC) has 4 stages. By designing and operating in a single feeding method, luminance deviation is prevented and the bezel area of the display panel 110 can be reduced.

Here, the case where the light emission driving circuit (EDC) is designed as 4 stages is explained as an example, but assuming that the number of subpixel (SP) lines driven by one light emission driving circuit (EDC) is K, each The light emission drive circuit (EDC) can be designed with a 2K stage.

In addition, in a structure in which the buffer transistor disposed in the light emitting driving circuit (EDC) is disposed in a horizontal direction with the signal wire disposed in the light emitting driving circuit (EDC), the light emitting driving circuit (EDC) driven in a single feeding method is all according to the present invention. It may be included in the embodiments of.

FIG. 8 is a diagram showing an example of the arrangement structure of circuit elements in the light emission driving circuit (EDC) shown in FIGS. 6 and 7.

Referring to FIG. 8, the light emission driving circuit (EDC) according to embodiments of the present invention includes a buffer transistor (BT) that controls the output of the light emission signal, and a logic transistor (BT) that controls the voltage levels of the Q node and Qb node. LT) may be included.

Here, the functions of each of the logic transistor (LT) and buffer transistor (BT) are the same as those described in FIG. 5 and are therefore omitted.

At least a portion of the logic transistor LT disposed in the light emission driving circuit EDC may be disposed in a direction crossing the signal wires disposed in the light emission driving circuit EDC.

Additionally, the buffer transistor BT disposed in the light emission driving circuit EDC may be disposed in the same direction as the signal wire disposed in the light emission driving circuit EDC.

That is, as the light emission driving circuit (EDC) is designed in four stages, the buffer transistor (BT) can be arranged along the same direction as the signal wire. Additionally, the source electrode or drain electrode of the buffer transistor BT may be formed integrally with the signal wire or may be formed to overlap the signal wire.

As the buffer transistor (BT) is arranged in the same direction as the signal wire, the buffer transistor (BT) can be placed adjacent to the signal wire, and thus the light emission driving circuit (EDC) can be configured more compactly.

Additionally, since the width of the buffer transistor (BT) increases along the signal wire, the channel region of the buffer transistor (BT) can be arranged in one direction without being separated.

In this way, the light emission driving circuit (EDC) is designed in 4 stages and driven by a single feeding method, so that the buffer transistor (BT) of the light emission driving circuit (EDC) is placed horizontally with the signal wire and the size can be reduced. , allowing the width (Wb=98㎛) of the light emission driving circuit (EDC) to be further reduced.

The buffer transistor (BT) disposed in this light emission driving circuit (EDC) is symmetrically disposed in the first light emission driving circuit (EDC1) and the second light emission driving circuit (EDC2) disposed on both sides of the display panel 110. It may be, or it may be arranged asymmetrically.

FIG. 9 is a diagram showing an example of a structure in which a logic transistor (LT) and a buffer transistor (BT) are arranged within the light emission driving circuit (EDC) shown in FIG. 7, and FIG. 10 is a diagram showing an example of a structure in which the light emission driving circuit (EDC) shown in FIG. This is a diagram showing an example of the arrangement structure of circuit elements within an EDC.

Referring to FIG. 9, the buffer transistor group BTG included in each of the first and second light emission driving circuits EDC1 and EDC2 disposed on both sides of the display panel 110 may be arranged symmetrically to each other. You can. Additionally, the logic transistor group LTG included in each of the first and second light emission driving circuits EDC1 and EDC2 may be arranged symmetrically.

In addition, since the first light emission driving circuit (EDC1) and the second light emission driving circuit (EDC2) are driven by a single feeding method, when the start signal (VST) is input to the first light emission driving circuit (EDC1), the first light emission driving circuit (EDC2) The light emission signal output by EDC1) is input as the start signal (VST) of the second light emission driving circuit (EDC2).

Additionally, the light emission signal output by the second light emission driving circuit (EDC2) is input as the start signal (VST) of the first light emission driving circuit (EDC1), so that single feeding driving can be performed.

10 shows the arrangement structure of circuit elements in the light emission driving circuit (EDC) when the first light emission driving circuit (EDC1) and the second light emission driving circuit (EDC2) are arranged symmetrically, as shown in FIG. 9. It shows an example.

As shown in FIG. 10, the first light emission driving circuit (EDC1) and the second light emission driving circuit (EDC2) disposed on both sides of the display panel 110 are disposed symmetrically, so that both sides of the display panel 110 The light emission driving circuit (EDC) disposed in can be easily implemented.

Alternatively, since the light emission driving circuit (EDC) is driven by a single feeding method, the first light emission driving circuit (EDC1) and the second light emission driving circuit are connected in consideration of the subpixel (SP) line driven by the light emission driving circuit (EDC). (EDC2) can also be implemented asymmetrically.

FIG. 11 is a diagram showing another example of a structure in which a logic transistor (LT) and a buffer transistor (BT) are arranged within the light emission driving circuit (EDC) shown in FIG. 7.

Referring to FIG. 11, the buffer transistor group BTG included in each of the first and second light emission driving circuits EDC1 and EDC2 disposed on both sides of the display panel 110 may be asymmetrically disposed. You can.

The buffer transistor BT included in the first light emission driving circuit EDC1 may be disposed adjacent to the subpixel SP line to which the light emission signal is applied by the first light emission driving circuit EDC1.

Additionally, the buffer transistor BT included in the second light emission driving circuit EDC2 may be disposed adjacent to the subpixel SP line to which the light emission signal is applied by the second light emission driving circuit EDC2.

That is, the buffer transistor (BT) included in each light emission driving circuit (EDC) is arranged adjacent to the subpixel (SP) line driven by the light emission driving circuit (EDC), so that the output from the light emission driving circuit (EDC) The load can be reduced by reducing the path through which the light-emitting signal reaches the subpixel (SP) line.

According to the above-described embodiments of the present invention, the buffer transistor (BT) included in the light emission driving circuit (EDC) disposed on both sides of the display panel 110 is oriented in the same direction as the signal wire disposed in the light emission driving circuit (EDC). By arranging the display panel 110, the bezel area of the display panel 110 can be reduced by reducing the width of the light emission driving circuit (EDC).

In addition, each of the light emission driving circuits (EDC) disposed on both sides of the display panel 110 is driven by a single feeding method that drives K subpixel (SP) lines, so that the luminance difference depending on the area of the display panel 110 is prevented and the size of the buffer transistor (BT) can be reduced, thereby minimizing an increase in the width of the bezel area of the display panel 110 due to the arrangement of the light emission driving circuit (EDC).

The above description is merely an illustrative explanation of the technical idea of the present invention, and various modifications and variations will be possible to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but rather to explain it, and therefore the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display device 110: display panel
120: gate driving circuit 130: data driving circuit
140: controller

Claims (20)

A display panel on which a plurality of gate lines, a plurality of data lines and a plurality of subpixels are arranged;
a plurality of scan driving circuits disposed on both sides of the display panel; and
Comprising a plurality of light emission driving circuits disposed on both sides of the display panel,
The buffer transistor included in each of the plurality of light emission driving circuits is arranged in the same direction as the signal wire disposed in the light emission driving circuit, and the buffer transistor included in each of the plurality of scan driving circuits is arranged in the scan driving circuit. A display device arranged in a direction that intersects the direction in which the signal wires arranged are arranged.
delete According to paragraph 1,
A display device wherein at least one of the plurality of logic transistors included in each of the plurality of light emission driving circuits is arranged in a direction that intersects the direction in which the signal wires arranged in the light emission driving circuit are arranged.
According to paragraph 1,
Among the plurality of scan driving circuits, a first scan driving circuit and a second scan driving circuit arranged to correspond to each other output scan signals to the same subpixel line,
A display device wherein among the plurality of light emission driving circuits, the first light emission driving circuit and the second light emission driving circuit arranged to correspond to each other output light emission signals through different subpixel lines.
According to paragraph 4,
A display device wherein the buffer transistor included in the first light emission driving circuit and the buffer transistor included in the second light emission driving circuit are arranged symmetrically.
According to paragraph 4,
A display device wherein the buffer transistor included in the first light emission driving circuit and the buffer transistor included in the second light emission driving circuit are asymmetrically disposed.
According to clause 6,
The buffer transistor included in the first light emission driving circuit is disposed adjacent to the subpixel line to which the light emission signal is applied by the first light emission driving circuit, and the buffer transistor included in the second light emission driving circuit is disposed adjacent to the subpixel line to which the light emission signal is applied by the first light emission driving circuit. A display device disposed adjacent to a subpixel line to which a light emitting signal is applied by a driving circuit.
According to paragraph 4,
A display device wherein the light emission signal output by the first light emission driving circuit is input as a start signal to the second light emission driving circuit.
According to paragraph 1,
Each of the plurality of light emission driving circuits outputs a light emission signal through K subpixel lines,
A display device in which one light emission driving circuit is arranged to correspond to 2K scan driving circuits.
multiple gate lines;
a plurality of subpixels driven by the plurality of gate lines and arranged in an active area;
a plurality of scan driving circuits disposed on both sides of the active area; and
comprising a plurality of light emission driving circuits disposed on both sides of the active area,
The buffer transistor included in each of the plurality of scan driving circuits is arranged in a direction that intersects the direction in which the signal wires arranged in the scan driving circuit are arranged,
A display panel wherein the buffer transistors included in each of the plurality of light emission driving circuits are arranged in the same direction as the signal wires arranged in the light emission driving circuits.
According to clause 10,
A display panel wherein at least one of the plurality of logic transistors included in each of the plurality of light emission driving circuits is arranged in a direction that intersects the direction in which the signal wires arranged in the light emission driving circuit are arranged.
According to clause 10,
Among the plurality of scan driving circuits, a first scan driving circuit and a second scan driving circuit arranged to correspond to each other output scan signals to the same subpixel line,
A display panel wherein among the plurality of light emission driving circuits, the first light emission driving circuit and the second light emission driving circuit arranged to correspond to each other output light emission signals through different subpixel lines.
According to clause 12,
A display panel wherein the buffer transistor included in the first light emission driving circuit and the buffer transistor included in the second light emission driving circuit are arranged symmetrically.
According to clause 12,
A display panel wherein the buffer transistor included in the first light emission driving circuit and the buffer transistor included in the second light emission driving circuit are asymmetrically disposed.
According to clause 14,
The buffer transistor included in the first light emission driving circuit is disposed adjacent to the subpixel line to which the light emission signal is applied by the first light emission driving circuit, and the buffer transistor included in the second light emission driving circuit is disposed adjacent to the subpixel line to which the light emission signal is applied by the first light emission driving circuit. A display panel disposed adjacent to a subpixel line to which a light emitting signal is applied by a driving circuit.
a first scan driving circuit;
a second scan driving circuit arranged to correspond to the first scan driving circuit;
a first light emission driving circuit arranged to correspond to 2K scan driving circuits including the first scan driving circuit; and
A second light emission driving circuit arranged to correspond to the first light emission driving circuit,
The buffer transistors included in the first light emission driving circuit and the second light emission driving circuit are arranged in the same direction as the signal wires arranged in the first light emission driving circuit and the second light emission driving circuit, and the A gate driving circuit in which the buffer transistor included in the first scan driving circuit and the second scan driving circuit is arranged in a direction that intersects the direction in which the signal wires arranged in the first scan driving circuit and the second scan driving circuit are arranged.
delete According to clause 16,
A gate driving circuit wherein the buffer transistor included in the first light emission driving circuit and the buffer transistor included in the second light emission driving circuit are arranged symmetrically.
According to clause 16,
The buffer transistor included in the first light emission driving circuit and the buffer transistor included in the second light emission driving circuit are asymmetrically disposed,
The buffer transistor included in the first light emission driving circuit is disposed adjacent to the subpixel line to which the light emission signal is applied by the first light emission driving circuit, and the buffer transistor included in the second light emission driving circuit is disposed adjacent to the subpixel line to which the light emission signal is applied by the first light emission driving circuit. A gate driving circuit disposed adjacent to the subpixel line to which the light emitting signal is applied by the driving circuit.
According to clause 16,
The first scan driving circuit and the second scan driving circuit output scan signals to the same subpixel line,
A gate driving circuit that outputs light emission signals from the first light emission driving circuit and the second light emission driving circuit to different subpixel lines.

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