KR20200068822A - Organic light emitting display apparatus - Google Patents

Abstract

An objective of the present invention is to provide an organic light emitting display device having stages capable of generating a scan signal and an emission signal. The organic light emitting display device comprises: an organic light emitting display panel; a data driver; a gate driver; and a control unit.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY APPARATUS}

The present invention relates to an organic light emitting display device.

The pixel driving circuit provided in each pixel of the organic light emitting display panel includes a switching transistor for controlling the timing at which the data voltage is charged in the storage capacitor, a driving transistor for controlling the amount of current supplied to the organic light emitting diode according to the data voltage, and An emission transistor is provided to control the light emission timing of the organic light emitting diode.

The switching transistor is turned on or off according to the scan signal, and the emission transistor is turned on or off according to the emission signal.

In the organic light emitting display device, the scan signal is generated by the scan signal generator of the gate driver, and the emission signal is generated by the emission signal generator of the gate driver.

In a conventional organic light emitting display device, the scan signal generation unit and the emission signal generation unit are independently provided in a non-display area in which an image outside the organic light emitting display panel is not output.

Therefore, in the conventional organic light emitting display device, the width of the non-display area is increasing, and accordingly, it is difficult to provide an organic light emitting display device having a non-display area having a small size width desired by a user.

An object of the present invention proposed to solve the above-described problem is to provide an organic light emitting display device having stages capable of generating a scan signal and an emission signal.

An organic light emitting display device according to the present invention for achieving the above-described technical problems includes an organic light emitting diode, a pixel driving circuit for driving the organic light emitting diode, a scan line connected to a switching transistor provided in the pixel driving circuit, and the pixel driving assembly An organic light emitting display panel including pixels including an emission line provided in a furnace and connected to an emission transistor to control the emission timing of the organic light emitting diode, and a data line connected to the switching transistor, of the organic light emitting display panel It includes a data driver for supplying a data voltage to the data line provided in a first direction, a gate driver including stages, and a control unit for driving the data driver and the gate driver. Each of the stages outputs two scan signals and one emission signal.

According to the present invention, the scan signal and the emission signal can be generated in one stage.

Therefore, in the organic light emitting display device according to the present invention, the scan signal generating unit for generating the scan signal and the emission signal generating unit for generating the emission signal need not be provided separately, and accordingly, the organic light emitting display panel The width of the non-display area may be narrower than the width of the non-display area of the conventional organic light emitting display panel.

Therefore, according to the present invention, an organic light emitting display device having a narrower non-display area than the prior art can be provided.

1 is an exemplary view showing a configuration of an organic light emitting display device according to the present invention.
2 is an exemplary view showing a configuration of a pixel applied to an organic light emitting display device according to the present invention.
3 is an exemplary view showing a configuration of a gate driver applied to the organic light emitting display device according to the present invention.
4 is an exemplary view showing the configuration of one of the stages shown in FIG. 3;
5 is an exemplary view showing waveforms of signals applied to the stage illustrated in FIG. 4.
6 to 12 are exemplary views showing a method of driving a stage applied to the organic light emitting display device according to the present invention.
13 is another exemplary view showing the configuration of one of the stages shown in FIG. 3;
14 is an exemplary view showing waveforms of signals applied to the stage illustrated in FIG. 13.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and have ordinary knowledge in the technical field to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the invention is only defined by the scope of the claims.

It should be noted that in this specification, when adding reference numerals to components of each drawing, the same components have the same number as possible, even if they are displayed on different drawings.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in the description of the present invention, when it is determined that detailed descriptions of related known technologies may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. When'include','have','consist of', etc. mentioned in the specification are used, other parts may be added unless'~man' is used. When a component is expressed as a singular number, the plural number is included unless otherwise specified.

In interpreting the components, it is interpreted as including the error range even if there is no explicit description.

In the case of the description of the positional relationship, for example, when the positional relationship of two parts is described as'~top','~upper','~bottom','~side', etc.,'right' Alternatively, one or more other parts may be located between the two parts unless'direct' is used.

In the case of a description of a time relationship, for example,'after','following','~after','~before', etc. When a temporal sequential relationship is described,'right' or'direct' It may also include cases that are not continuous unless it is used.

It should be understood that the term “at least one” includes all possible combinations from one or more related items. For example, the meaning of'at least one of the first item, the second item, and the third item' means 2 of the first item, the second item, and the third item, as well as the first item, the second item, or the third item, respectively. Any combination of items that can be presented from more than one dog.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Each of the features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving may be possible, and each of the embodiments may be independently implemented with respect to each other or may be implemented together in an association relationship. It might be.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a configuration of an organic light emitting display device according to the present invention, FIG. 2 is an exemplary view showing a configuration of a pixel applied to an organic light emitting display device according to the present invention, and FIG. 3 is an organic view according to the present invention This is an exemplary view showing a configuration of a gate driver applied to a light emitting display device. 2, a pixel driving circuit (PDC) composed of P-type transistors is illustrated, but the organic light emitting display device according to the present invention is not limited to the pixel driving circuit (PDC) composed of P-type transistors.

1 and 2, the organic light emitting display device according to the present invention includes an organic light emitting display panel 100, a data driver 300, a gate driver 200 and a control unit.

In the organic light emitting display panel, pixels 110 are provided. Each of the pixels 110 is an organic light emitting diode (OLED), a pixel driving circuit (PDC) driving the organic light emitting diode (OLED), and a scan connected to a switching transistor (TP2) provided in the pixel driving circuit (PDC) Line GL, an emission line EL provided in the pixel driving circuit PDC and connected to emission transistors TP3 and TP4 for controlling the light emission timing of the organic light emitting diode OLED, and the switching transistor TP2 ) And a data line DL connected thereto. The data driver 300 supplies a data voltage to the data line DL provided along the first direction of the organic light emitting display panel 100. The gate driver 200 includes stages. The control unit 400 drives the data driver 300 and the gate driver 200. Here, each of the stages outputs two scan signals and one emission signal.

In the following, the components are described sequentially.

In the organic light emitting display panel 100, as illustrated in FIGS. 1 and 2, the pixels 110, data lines DL1 to Dld connected to the data driver 300, and the scan lines GL ), initialization lines IL to which the initialization voltage is supplied, the emission lines EL, the first driving voltage lines PLA to which the first driving voltage VDD is supplied, and the second driving voltage ( VSS) may be provided with second driving voltage lines PLB. An auxiliary scan line SCL connected to a switching transistor provided in another pixel driving circuit may be connected to the pixel driving circuit PDC. The n-2 scan signal SCAN(n-2) may be supplied to the auxiliary scan line SCL from the pixel driving circuit PDC illustrated in FIG. 2. The n-2 scan signal SCAN(n-2) supplied to the auxiliary scan line SCL is also one of scan signals generated by the gate driver 200.

Each of the pixels 110 is provided with the organic light emitting diode (OLED) and the pixel driving circuit (PDC).

The pixel driving circuit PDC is connected to the organic light emitting diode OLED and controls a current supplied to the organic light emitting diode OLED and the driving transistor Tdr as shown in FIG. 2. It may be formed in various forms including a driving unit 111 for driving (Tdr).

The driving unit 111 may include at least one capacitor and at least one transistor.

For example, the driving unit 111 has one end connected to the data line DL, the other end connected to the first terminal of the driving transistor Tdr, and a gate connected to the gate driver 200. One switching transistor TP2 and one storage capacitor Cst for charging the data voltage Vdata supplied from the data line DL through the switching transistor TP2 may be included.

In addition, a compensation circuit for compensating for a change in threshold voltage or mobility due to deterioration of the driving transistor Tdr may be further provided in the driving unit 111.

The compensation circuit may be configured such that the current supplied to the organic light emitting diode OLED through the driving transistor Tdr is not affected by the threshold voltage or mobility of the driving transistor Tdr. This type of compensation circuit is called an internal compensation circuit. Since the internal compensation circuit is currently used in various structures and methods, detailed description thereof is omitted.

In addition, the compensation circuit may be configured to sense the threshold voltage of the driving transistor Tdr and transmit the sensed threshold voltage to the data driver. This type of compensation circuit is called an external compensation circuit. Since the external compensation circuit is also currently used in various structures and methods, detailed description thereof is omitted.

That is, the driving unit 111 applied to the present invention may be formed of a simple structure for driving the driving transistor Tdr according to a data voltage, and may include at least two transistors for internal compensation or external compensation. It might be.

As an example of the driving unit 111, FIG. 2 includes six transistors TP1 to TP6 and one storage capacitor Cst, and a driving unit using an internal compensation scheme is illustrated, but the structure illustrated in FIG. 2 is illustrated. In addition, the driving unit 111 may be formed in various structures.

For example, the driver 111 may include 5 transistors and 1 capacitor, 5 transistors and 2 capacitors, and 6 transistors to use an internal compensation scheme. And two capacitors, four transistors and two capacitors, and seven or more transistors.

The feature of the present invention is not in the structure of the driving unit 111, and the driving unit 111 may be formed in various structures in addition to the structure shown in FIG. 2, as described above. Therefore, hereinafter, the structure and operation method of the driving unit 111 will be briefly described.

That is, the driving unit 111, as shown in Figure 2, the first terminal is connected to the gate of the driving transistor Tdr, the second terminal is connected to the second terminal of the driving transistor Tdr , A first transistor TP1 to which an n-th scan signal SCAN(n) is supplied to a gate, a first terminal is connected to the data line DL, and a second terminal is the first of the driving transistor Tdr. Terminal, a second transistor TP2 to which the n-th scan signal SCAN(n) is supplied to a gate, a first terminal is connected to the first driving voltage line PLA, and a second terminal is The third terminal TP3 is connected to the first terminal of the driving transistor Tdr, the emission signal EM is supplied to the gate, and the first terminal is connected to the second terminal of the driving transistor Tdr. , A second transistor connected to the organic light emitting diode (OLED), a fourth transistor TP4 to which the emission signal EM is supplied to a gate, and an initialization line to which a first terminal is supplied with an initialization voltage (Vinit) ( IL), a second terminal is connected to the gate of the driving transistor Tdr, and the fifth transistor TP5, the n-2 scan signal SCAN(n-2) is supplied to the gate. A sixth transistor (1 terminal) is connected to the initialization line (IL), a second terminal is connected to the second terminal of the fourth transistor, and the nth scan signal (SCAN(n)) is supplied to a gate ( TP6) and a storage capacitor Cst having one end connected to the first terminal of the third transistor and the other end connected to the gate of the driving transistor Tdr.

For example, when the n-2 scan signal SCAN(n-2) is supplied to the driving unit 111, the fifth transistor TP5 is turned on so that the initialization voltage Vinit is the storage. It is supplied to the other end of the capacitor Cst and the gate of the driving transistor Tdr. Accordingly, the gate of the storage capacitor Cst and the driving transistor Tdr may be initialized with the initialization voltage Vinit.

When the n-th scan signal SCAN(n) is supplied to the driver 111 after the initialization voltage Vinit is supplied, the second transistor TP2, the driving transistor Tdr, and the first The transistor TP1 is turned on, and accordingly, the data voltage Vdata supplied from the data line DL and the threshold voltage of the driving transistor Tdr are charged in the storage capacitor Cst.

After the data voltage Vdata and the threshold voltage are charged, when the third transistor TP3 and the fourth transistor TP4 are turned on by the emission signal, the third transistor and the driving transistor Tdr ) And a current flows through the fourth transistor TP4 to the organic light emitting diode OLED. The organic light emitting diode OLED outputs light having a brightness corresponding to the current.

In this case, the voltage of the gate of the driving transistor Tdr is the sum of the data voltage Vdata and the threshold voltage Vth, and the voltage of the source of the driving transistor Tdr is the first driving voltage VDD. )to be.

The current Ioled passing through the driving transistor Tdr is the threshold voltage Vth of the driving transistor Tdr from the difference voltage (Vgs=Vdata+Vth-VDD) between the gate and the source of the driving transistor Tdr. It is proportional to the square of the subtracted voltage (=Vdata+Vth-VDD-Vth).

That is, the current (Ioled) supplied to the organic light emitting diode (OLED) through the driving transistor (Tdr) can be expressed by the following [Equation 1].

In [Equation 1], k is a proportionality constant determined by various factors.

That is, the current (Ioled) supplied to the organic light emitting diode (OLED) through the driving transistor (Tdr) is determined by the data voltage (Vdata) and the first driving voltage (VDD), the driving transistor (Tdr) ) Is not determined by the threshold voltage (Vth).

In general, the driving transistor Tdr may deteriorate as the organic light emitting display device is used for a long time, and accordingly, the threshold voltage Vth of the driving transistor Tdr may be changed.

In addition, the degree of deterioration of the driving transistor Tdr provided in the pixel 110 formed in the organic light emitting display panel 100 may be different from each other due to various causes.

When the deterioration levels of the driving transistors Tdr are changed, threshold voltages of the driving transistors Tdr are also different.

When the threshold voltages of the driving transistors Tdr are changed, even if the same data voltages Vdata are supplied to the driving transistors Tdr, the current supplied to the organic light emitting diodes OLEDs through the driving transistors Tdr is Sizes may vary. Therefore, the organic light emitting diodes OLEDs provided in the pixels supplied with the same data voltage Vdata can output light having different brightness.

That is, the driving unit 111 may be configured such that the current flowing through the organic light emitting diode OLED is not affected by the threshold voltage Vth of the driving transistor Tdr, as described above. have. Accordingly, the driving unit 111 may be changed to various structures in which the purpose as described above can be achieved in addition to the structure illustrated in FIG. 2.

In this case, while the switching transistor TP2 is turned on and the data voltage Vdata is charged to the storage capacitor Cst, the emission transistors, that is, the third transistor TP3 and the fourth transistor (TP4) should be turned off. After the data voltage Vdata is charged, when the third transistor TP3 and the fourth transistor TP4 are turned on, a current flows through the organic light emitting diode OLED, and accordingly, the organic The light emitting diode OLED outputs light having a brightness corresponding to the magnitude of the current Ioled.

Therefore, the emission signal generation unit 500, while the data voltage (Vdata) is charged to the storage capacitor (Cst), that is, while the switching transistor (TP2) is turned on, the emission transistor ( An emission turnoff signal for turning off TP3 and PT4 should be supplied to the pixel driving circuit PDC, and at the timing when the organic light emitting diode OLED outputs light, the emission transistors TP3, The emission signal to turn on TP4) must be supplied to the pixel driving circuit (PDC).

When the emission transistors TP3 and TP4 are P-type transistors, as shown in FIG. 2, the voltage capable of turning on the emission transistors TP3 and TP4 is a low level voltage, and the emission The voltage capable of turning off the transistors TP3 and TP4 is a high level voltage.

In addition, in the present invention, since one emission signal EM is supplied to two adjacent pixels 110 along the data line DL, the emission turnoff signal is the data line DL. The switching transistors TP2 provided in the adjacent two pixels 110 must be supplied to the two pixels until they are all turned on.

Therefore, the width of the emission turn-off signal should be at least twice the width of the scan turn-on signal that turns on the switching transistor TP2. Hereinafter, an emission signal in which the width of the emission turn-off signal is 5 times the width of the scan turn-on signal or an emission signal in which the emission signal is 4 times is described as an example of the present invention. However, as described above, the width of the emission turn-off signal applied to the present invention can be variously adjusted to be more than twice the width of the scan turn-on signal.

Hereinafter, for convenience of description, the present invention will be described using the pixel driving circuit (PDC) shown in FIG. 2.

The gate driver 200 supplies scan turn-on signals to the scan lines GL1 to GLg using the gate control signals GCS transmitted from the control unit 400, and the emission line EL Emissions provide emission turn-on signals.

Here, the scan turn-on signal means a signal capable of turning on the switching transistor TP2 connected to the scan lines GL1 to GLg and the data lines DL1 to DLd. The signal capable of turning off the switching transistor TP2 is called a scan turnoff signal. The scan turn-on signal and the scan turn-off signal are collectively referred to as a scan signal (SCAN).

The emission signal EM also includes an emission turn-on signal that can turn on the emission transistors TP3 and TP4, and an emission turn-off signal that can turn off the emission transistors TP3 and TP4. It includes.

The gate driver 200 is formed independently of the organic light emitting display panel 100, and the organic light emitting display panel is formed through a tape carrier package (TCP), a chip on film (COF), or a flexible printed circuit board (FPCB). It can be connected to (100). However, the gate driver 200, using a gate in panel (GIP) method, through the manufacturing process of the pixel driving circuits (PDCs), the outer portion of the organic light emitting display panel 100, that is , May be directly formed in the non-display area 130.

The display region 120 of the organic light emitting display panel 100 means a portion in which an image is output by the pixels 110, and the non-display region 130 means a portion in which an image is not output. The non-display area 130 is provided outside the display area 120.

The gate driver 200 supplies the scan signals SCAN to the scan lines GL1 to GLg, and supplies the emission signal EM to the emission lines EL. As shown in FIG. 3, it includes first to e stages (Stage 1 to Stage e).

Each of the stages is connected to two scan lines GL and one emission line EL. Accordingly, each of the stages outputs two scan signals SCAN and one emission signal EM.

In the present invention, each of the two scan signals SCAN is supplied to pixels provided in a line along a second direction different from the first direction, and the emission line EL is the data line DL The emission signal EM is supplied to two pixels 110 adjacent to each other.

Here, the first direction means, for example, the vertical direction of FIGS. 1 and 2, and the second direction means, for example, the horizontal direction of FIGS. 1 and 2.

To further explain, assuming that the pixels 110 arranged in a line along the second direction are provided in a horizontal line that is a virtual line, the stage is as shown in FIG. 3, The scan signal Scan is supplied to the pixels 110 provided in one horizontal line, and the emission signal EM is provided to the pixels 110 provided in two horizontal lines adjacent to each other. Supplies.

In this case, the scan signal supplied to the pixels provided in one horizontal line may also be supplied to the pixels provided in another horizontal line. For example, the n-2 scan signal SCAN(n-2) illustrated in FIG. 3 is supplied to the pixels provided in the first horizontal line of FIG. 3, but the pixel driving circuit PDC is When configured as shown in FIG. 2, pixels 110 provided in the third horizontal line to which the n-th scan signal SCAN(n) is supplied may also be supplied.

The stage is driven by a gate start signal GVST, an emission start signal EVSST, and clocks CLK1 to CLK4. In this case, the gate start signal GVST supplied to the stage is one of two scan signals output from another stage, and the emission start signal supplied to the stage is an emission output from the front stage. It is a signal.

For example, in FIG. 3, the n-2nd scan signal SCAN(n-2) of the two scan signals output from the first stage Stage 1 is supplied to the second stage Stage 2 have. In this case, the n-th scan signal SCAN(n-2) becomes the gate start signal GVST of the second stage Stage2.

In addition, in FIG. 3, the first emission signal EM1 output from the first stage Stage 1 is supplied to the second stage Stage 2. In this case, the first emission signal EM1 output from the first stage Stage 1 becomes the emission start signal EVST of the second stage Stage 2.

However, the present invention is not limited to this. That is, the gate start signal EVST and the emission start signal EVST input to any one stage may be supplied from at least one of the remaining stages other than the one stage.

The stage which operates for the first time among the stages may receive the gate start signal GVST and the emission start signal EVST from the controller 400.

To this end, the control unit 400 transmits the gate clocks CLK1 to CLK4 and the emission start signal EVST and the gate start signal GVST to the gate driver 200.

The power supply unit supplies power to the gate driver 200, the data driver and the control unit 400.

The control unit 400 uses the timing synchronization signal input from an external system to control the driving of the gate driver 200, the gate control signal GCS, and the data for controlling the driving of the data driver 300. Each control signal DCS is generated. In addition, the control unit 400 converts input image data input from the external system into image data, and transmits the image data to the data driver 300.

In order to perform the above-described function, the control unit 400 rearranges the input image data transmitted from the external system by using the timing synchronization signal transmitted from the external system, and rearranges the rearranged image data to the data driver. A data alignment unit for supplying to 300, a control signal generation unit for generating the gate control signal GCS and the data control signal DCS using the timing synchronization signal, and the timing transmitted from the external system The input unit for distributing the synchronization signal and the input image data to the data alignment unit and the control signal generation unit, and the image data generated by the data alignment unit and the control signals generated by the control signal generation unit (DCS, GCS) may include an output unit for outputting the data driver 300 or the gate driver 200.

The gate control signal GCS may include the gate clocks CLK, the gate start signal GVST, and the emission start signal EVST.

The gate start signal GVST transmitted from the control unit 400 drives any one of the stages 1 to Gstage e, and the remaining stages are generated in other stages, as described above. The scanned scan signal Scan may be used as the gate start signal GVST.

In addition, the emission start signal EVST transmitted from the control unit 400 drives any one of the stages 1 to Stage e, and the other stages are another stage, as described above. The emission signal EM generated from any one of these may be used as the emission start signal EVST.

The data driver 300 converts the image data Data transmitted from the control unit 400 to the data voltages Vdata, and converts the data voltages Vdata to the data lines DL1 to DLd. Is supplied to the pixel driving units (PDCs).

4 is an exemplary view showing a configuration of one of the stages shown in FIG. 3, and FIG. 5 is an exemplary view showing waveforms of signals applied to the stage shown in FIG. 4. In particular, the stage shown in FIG. 4 is the second stage (Stage 2) shown in FIG. 3. That is, as shown in FIGS. 2 and 3, the second stage (Stage 2) receives the n-2 scan signal (SCAN(n-2)) as the gate start signal (GVST), and the first em The Sean signal EM1 is received as the emission start signal EVST. In addition, the second stage (Stage 2) outputs the n-th scan signal SCAN(n), the n+1 scan signal SCAN(n+1), and the second emission signal EM2. In the following description, the present invention is described using the pixel driving part PDC shown in FIG. 2 in which the switching transistor TP2 and the emission transistors TP3 and TP4 are formed in a P type. Therefore, the scan turn-on signal and the emission turn-on signal that can turn on the switching transistor and the emission transistor have a low level, and the scan turn-off signal and the emission that can turn off the switching transistor and the emission transistor. The turn-off signal has a high level.

The organic light emitting display device according to the present invention, as described with reference to Figures 1 to 3, the organic light emitting display panel 100, the data driver 300, the gate driver 200 and the control unit 400 ). The gate driver 200 includes a plurality of stages (Stage 1 to Stage e).

Each of the stages, as shown in FIG. 4, includes a first scan generator 220, a second scan generator 230, an emission generator 240, and a stage controller 210.

The first scan generating unit 220 generates an nth scan signal SCAN(n) among the two scan signals SCAN(n) and SCAN(n+1).

In order to perform the above-described function, the first scan generator 220 converts the first clock CLK1 into the nth scan signal SCAN(n) under the control of the stage control unit 210. A second transistor T2 outputting a first voltage VSS having a high level under the control of the outputting first transistor T1 and the stage control unit 210 as the nth scan signal SCAN(n). It includes.

The gate of the first transistor T1 is connected to the second terminal of the eighth transistor T8, the second terminal is connected to the first terminal of the second transistor T2, and the first transistor T1 is The first clock CLK1 is supplied to the first terminal of.

The gate of the second transistor T2 is connected to the second terminal of the eleventh transistor T11, the first terminal is connected to the second terminal of the first transistor T1, and the second terminal is the twelfth terminal. It is connected to the second terminal of the transistor T12, the second terminal of the tenth transistor T10, the second terminal of the fourth transistor T4, and the second terminal of the sixth transistor T6.

The second scan generator 230 generates an n+1 scan signal SCAN(n+1) among the two scan signals SCAN(n) and SCAN(n+1).

In order to perform the above-described function, the second scan generation unit 230 transmits a second clock CLK2 under the control of the stage control unit 210 to the n+1 scan signal SCAN(n+ 1)) the first voltage VSS having a high level under the control of the third transistor T3 and the stage control unit 210 output to the n+1 scan signal SCAN(n+1). And a fourth transistor T4 to be output.

The gate of the third transistor T3 is connected to the gate of the first transistor T1, the second terminal is connected to the first terminal of the fourth transistor T4, and the third transistor T3 is connected to the gate of the third transistor T3. The second clock CLK2 is supplied to the first terminal.

The gate of the fourth transistor T4 is connected to the gate of the second transistor T2, the first terminal is connected to the second terminal of the third transistor T3, and the second terminal is a twelfth transistor It is connected to the second terminal of (T12), the second terminal of the tenth transistor (T10), the second terminal of the second transistor (T2), and the second terminal of the sixth transistor (T6).

The emission generation unit 240 generates the emission signal EM2.

In order to perform the above-described function, the emission generation unit 240 outputs an emission voltage EMVDD having a low level as the emission signal EM2 under the control of the stage control unit 210. And a sixth transistor T6 outputting the first voltage VSS having a high level to the emission signal EM under the control of the fifth transistor T5 and the stage controller 210.

The gate of the fifth transistor T5 is connected to the gate of the fourth transistor T4, the second terminal is connected to the first terminal of the sixth transistor T6, and the gate of the fifth transistor T5 is The emission voltage EMVDD is supplied to the first terminal.

The gate of the sixth transistor T6 is connected to the gate of the third transistor T3, the first terminal is connected to the second terminal of the fifth transistor T5, and the second terminal is a twelfth transistor It is connected to the second terminal of (T12), the second terminal of the tenth transistor (T10), the second terminal of the second transistor (T2), and the second terminal of the fourth transistor (T4).

The stage control unit 210 receives the gate start signal GVST and the emission start signal EVST, and the first scan generation unit 220, the second scan generation unit 230, and the emission generation unit Control 240.

In order to perform the above-described function, the stage control unit 210 includes seventh to twelfth transistors T7 to T12.

The seventh transistor T7 is turned on or off by the gate start signal GVST. The first terminal of the seventh transistor T7 is connected to the first terminal of the ninth transistor T9, and the second terminal is the first terminal of the twelfth transistor T12 and the eighth transistor T8. It is connected to the first terminal of the, the gate start signal (GVST) is supplied to the gate.

The first terminal of the eighth transistor T8 is connected to the second terminal of the seventh transistor T7, and the second terminal is the first scan generator 220 and the second scan generator 230. And the emission generation unit 240, and a gate connected to the first terminal of the ninth transistor T9 and the first terminal of the seventh transistor T7. The eighth transistor T8 is turned on by the second voltage VDD having a low level supplied to the gate.

The ninth transistor T9 is turned on or off by the fourth clock CLK4. The first terminal of the ninth transistor T9 is connected to the first terminal of the seventh transistor T7 and the gate of the eighth transistor T8, and the second terminal is connected to the first terminal of the tenth transistor T9. The fourth clock CLK4 is supplied to the gate.

The first terminal of the tenth transistor T10 includes the second terminal of the ninth transistor T9, the first scan generator 220, the second scan generator 230, and the emission generator ( 240), the second terminal is the second terminal of the twelfth transistor T12, the second terminal of the second transistor T2, the second terminal of the fourth transistor T4 and the sixth transistor It is connected to the second terminal of (T6), the gate is connected to the second terminal of the eighth transistor (T8). A first voltage VSS having a high level is supplied to the second terminal of the tenth transistor T10.

The first terminal of the eleventh transistor T11 is connected to the gate of the twelfth transistor T12, and the second terminal is the first scan generator 220, the second scan generator 230, and the It is connected to an emission generation unit 240, and the emission start signal EVST is supplied to the gate of the eleventh transistor T11.

The gate of the twelfth transistor T12 is connected to the first terminal of the eleventh transistor T11, the first terminal is connected to the second terminal of the seventh transistor T7, and the second terminal is the first terminal. 10 is connected to the second terminal of the transistor T10, the second terminal of the second transistor T2, the second terminal of the fourth transistor T4, and the second terminal of the sixth transistor T6. The first voltage VSS is supplied to the second terminal of the twelfth transistor T12.

That is, in each of the stages, a first clock is supplied to a first terminal, and a second terminal is a first transistor T1 connected to a scan line from which the nth scan signal is output among the two scan signals. The first terminal is connected to the second terminal of the first transistor, the second terminal is a second transistor T2 to which a first voltage having a high level is supplied, and a second clock is supplied to the first terminal, and the second is The terminal is a third transistor T3 connected to a scan line from which the n+1 scan signal is output among the two scan signals, and the first terminal is connected to the second terminal of the third transistor, and to the second terminal. Is a fourth transistor T4 to which the first voltage is supplied, an emission voltage having a low level is supplied to the first terminal, and a second terminal is a fifth transistor connected to an emission line from which the emission signal is output. (T5), the first terminal is connected to the second terminal of the fifth transistor, and the second terminal is a sixth transistor (T6) to which the first voltage is supplied, which is turned on or off by a gate start signal. 7 transistor (T7), a first terminal is connected to the second terminal of the seventh transistor, a second terminal is connected to the first scan generator, the second scan generator and the emission generator, and a gate An eighth transistor T8 turned on by a second voltage having a low level supplied to, and turned on or off by a fourth clock, and a first terminal of the first terminal and the eighth transistor of the seventh transistor A ninth transistor T9 connected to a gate, a first terminal connected to a second terminal of the ninth transistor, a gate of the first transistor, a gate of the third transistor, and a gate of the sixth transistor, the second terminal The first voltage is supplied to a terminal, a tenth transistor (T10) having a gate connected to the second terminal of the eighth transistor, an emission start signal is supplied to the gate, and a second terminal is a gate of the second transistor , A gate connected to the gate of the fourth transistor and the gate of the fifth transistor Twelve transistors T11 and a gate are connected to a first terminal of the eleventh transistor, a first terminal is connected to a second terminal of the seventh transistor, and a twelfth transistor to which the first voltage is supplied to a second terminal (T12).

The pulses constituting the first clock CLK1, the second clock CLK2, and the fourth clock CLK4, as shown in FIG. 5, have a width of two horizontal periods, and the first clock ( The phase of CLK1) is one horizontal period faster than the phase of the second clock CLK2, and the phase of the second clock CLK2 is two horizontal periods earlier than the phase of the fourth clock CLK4.

Here, one horizontal period 1H refers to a period during which the data voltage Vdata is supplied to the data line DL. That is, the data voltage Vdata is supplied to the data line DL within the one horizontal period. Therefore, the 2 horizontal period means a period in which 1 horizontal period is repeated twice.

The emission turn-off signal constituting the emission signal EM, that is, the emission signal EM at a high level, has a width of 5 horizontal periods 5H, as shown in FIG. 5. The 5 horizontal period (5H) means a period in which 1 horizontal period is repeated 5 times.

As described above, the gate start signal GVST may be any one of two scan signals output from another stage other than the stage illustrated in FIG. 4, and the emission start signal EVST May be an emission signal output from the front end stage.

Hereinafter, a driving method of the organic light emitting display device according to the present invention will be described with reference to FIGS. 1 to 12.

6 to 12 are exemplary views showing a method in which the stage applied to the organic light emitting display device according to the present invention is driven, in particular, in the first period (A) to the seventh period (G) shown in FIG. These are example diagrams showing how the stage is driven. In the following description, contents identical or similar to those described with reference to FIGS. 1 to 5 are omitted or simply described. In addition, in FIGS. 6 to 12, a line represented by a dotted line means a line through which a low level signal is transmitted, and a line represented by a bold line means a line through which a high level signal is transmitted, and a thinly expressed line. Means a line on which a meaningless signal is transmitted.

First, as shown in FIGS. 5 and 6, in the first period A, the gate start signal GVST is at a high level, the emission start signal EVST is at a high level, and the first voltage (VSS) is a high level, the second voltage (VDD) is a low level, the first clock (CLK1) is a low level, the second clock (CLK2) is a low level, the fourth clock (CLK4) ) Is a high level, and the emission voltage EMVDD is a low level.

In this case, the second voltage VDD and high having a low level are applied to the QB node QB connected to the gate of the fifth transistor T5 and the Q node Q connected to the gate of the sixth transistor T6. The first voltage VSS having a level is not supplied.

However, since the low-level voltage was supplied to the QB node QB before the first period A, a low-level voltage may be applied to the QB node also in the first period A. Accordingly, as illustrated in FIG. 6, the fifth transistor T5 may be turned on, and accordingly, the emission signal EM having a low level may be output.

In this case, since the low-level voltage is also supplied to the gates of the second transistor T2 and the fourth transistor T4, the second transistor T2 and the fourth transistor T4 are also turned on. Accordingly, the n-th scan signal SCAN(n) at a high level and the n+1 scan signal SCAN(n+1) at a high level may be output.

Further, even if the fifth transistor T5 is not turned on, since the sixth transistor T6 is also not turned on, the emission line EL is floating in the first period A. Accordingly, the emission signal prior to the first period A, that is, the emission signal at a low level may be continuously applied to the emission line EL.

Further, even if the second transistor T2 and the fourth transistor T4 are not turned on, the n-th scan signal and the n+1 scan signal are at a level before the first period A, that is, high Level can be maintained.

Since the high-level voltage was supplied to the cue node Q before the first period A, a high-level voltage may be applied to the cue node also in the first period A. Therefore, accordingly, as illustrated in FIG. 6, the sixth transistor T6 may be turned off.

When the sixth transistor T6 is not turned on, as described above, the fifth transistor T5 is also not turned on.

Accordingly, the emission signal EM having a low level may be supplied to the emission line EL in the first period A.

Next, as shown in FIGS. 5 and 7, in the second period B, the gate start signal GVST is at a low level, the emission start signal EVST is at a high level, and the first voltage (VSS) is a high level, the second voltage (VDD) is a low level, the first clock (CLK1) is a high level, the second clock (CLK2) is a low level, the fourth clock (CLK4) ) Is a high level, and the emission voltage EMVDD is a low level.

In this case, the second voltage VDD having a low level is supplied to the gate of the sixth transistor T6 through the seventh transistor and the eighth transistor. Accordingly, the sixth transistor T6 is turned on, and accordingly, the first voltage VSS having a high level is output to the emission line EL through the sixth transistor. That is, in the second period B, the emission signal EL is an emission turnoff signal.

Since the second voltage VDD having a low level is supplied to the queue node Q, the first transistor and the third transistor are also turned on. Accordingly, the first clock CLK1 at a high level is output to the nth scan signal SCAN(n) through the first transistor, and the second clock CLK2 at a low level is the third transistor. Through is output to the n + 1 scan signal (SCAN (n + 1)).

The first voltage VSS at a high level is supplied to the QB node QB. Accordingly, the second transistor, the fourth transistor, and the fifth transistor are turned off.

Next, as shown in FIGS. 5 and 8, in the third period C, the gate start signal GVST is at a low level, the emission start signal EVST is at a high level, and the first voltage (VSS) is a high level, the second voltage (VDD) is a low level, the first clock (CLK1) is a high level, the second clock (CLK2) is a high level, the fourth clock (CLK4) ) Is a low level, and the emission voltage EMVDD is a low level.

In this case, the second voltage VDD having a low level is supplied to the gate of the sixth transistor T6 through the seventh transistor and the eighth transistor. Accordingly, the sixth transistor T6 is turned on, and accordingly, the first voltage VSS having a high level is output to the emission line EL through the sixth transistor. That is, in the third period C, the emission signal EL is an emission turnoff signal.

Since the second voltage VDD having a low level is supplied to the queue node Q, the first transistor and the third transistor are also turned on. Accordingly, the first clock CLK1 at a high level is output to the nth scan signal SCAN(n) through the first transistor, and the second clock CLK2 at a high level is the third transistor. Through is output to the n + 1 scan signal (SCAN (n + 1)).

Both the second voltage VDD at a low level and the first voltage VSS at a high level are supplied to the QB node QB. However, since the first voltage VSS has a much larger value than the second voltage VDD, a high level is supplied to the QB node. Accordingly, the second transistor, the fourth transistor, and the fifth transistor are turned off.

Next, as shown in FIGS. 5 and 9, in the fourth period D, the gate start signal GVST is at a high level, the emission start signal EVST is at a high level, and the first voltage (VSS) is a high level, the second voltage (VDD) is a low level, the first clock (CLK1) is a low level, the second clock (CLK2) is a high level, the fourth clock (CLK4) ) Is a low level, and the emission voltage EMVDD is a low level.

In this case, the queue node is in a floating state, and thus, the voltage of the third period C, that is, a low level voltage is continuously applied to the queue node. Accordingly, a voltage having a low level is supplied to the gate of the sixth transistor T6 through the first transistor and the third transistor. Accordingly, the sixth transistor T6 is turned on, and accordingly, the first voltage VSS having a high level is output to the emission line EL through the sixth transistor. That is, in the fourth period D, the emission signal EL is an emission turnoff signal.

Since a low level voltage is applied to the queue node Q, the first transistor and the third transistor are also turned on. Accordingly, the first clock CLK1 at a low level is output to the nth scan signal SCAN(n) through the first transistor, and the second clock CLK2 at a high level is the third transistor. Through is output to the n + 1 scan signal (SCAN (n + 1)).

Both the second voltage VDD at a low level and the first voltage VSS at a high level are supplied to the QB node QB. However, since the first voltage VSS has a much larger value than the second voltage VDD, a high level is supplied to the QB node. Accordingly, the second transistor, the fourth transistor, and the fifth transistor are turned off.

Next, as shown in FIGS. 5 and 10, in the fifth period E, the gate start signal GVST is at a high level, the emission start signal EVST is at a low level, and the first voltage is (VSS) is a high level, the second voltage (VDD) is a low level, the first clock (CLK1) is a low level, the second clock (CLK2) is a low level, the fourth clock (CLK4) ) Is a high level, and the emission voltage EMVDD is a low level.

In this case, the queue node is in a floating state, and thus, the voltage of the queue node in the fourth period (D), that is, a low level voltage is continuously applied to the queue node. Accordingly, a voltage having a low level is supplied to the gate of the sixth transistor T6 through the first transistor and the third transistor. Accordingly, the sixth transistor T6 is turned on, and accordingly, the first voltage VSS having a high level is output to the emission line EL through the sixth transistor. That is, in the fifth period E, the emission signal EL is an emission turnoff signal.

Since a low level voltage is applied to the queue node Q, the first transistor and the third transistor are also turned on. Accordingly, the low-level first clock CLK1 is output to the n-th scan signal SCAN(n) through the first transistor, and the low-level second clock CLK2 is the third transistor. Through is output to the n + 1 scan signal (SCAN (n + 1)).

In the fifth period D, a high level voltage is applied to the QB node QB. Accordingly, the second transistor, the fourth transistor, and the fifth transistor are turned off.

Next, as shown in FIGS. 5 and 11, in the sixth period F, the gate start signal GVST is at a high level, the emission start signal EVST is at a low level, and the first voltage is (VSS) is a high level, the second voltage (VDD) is a low level, the first clock (CLK1) is a high level, the second clock (CLK2) is a low level, the fourth clock (CLK4) ) Is a high level, and the emission voltage EMVDD is a low level.

In this case, the queue node is in a floating state, and thus, the voltage of the queue node in the fifth period E, that is, a low level voltage is continuously applied to the queue node. Accordingly, a voltage having a low level is supplied to the gate of the sixth transistor T6 through the first transistor and the third transistor. Accordingly, the sixth transistor T6 is turned on, and accordingly, the first voltage VSS having a high level is output to the emission line EL through the sixth transistor. That is, in the sixth period F, the emission signal EL is an emission turnoff signal.

In the sixth period F, the cue node Q is in a floating state, and thus, the voltage of the cue node in the fifth period E, that is, a low level voltage is continuously applied to the cue node. . Therefore, the first transistor and the third transistor are also turned on. Accordingly, the first clock CLK1 at a high level is output to the nth scan signal SCAN(n) through the first transistor, and the second clock CLK2 at a low level is the third transistor. Through is output to the n + 1 scan signal (SCAN (n + 1)).

In the sixth period F, a high level voltage is continuously applied to the QB node QB. Accordingly, the second transistor, the fourth transistor, and the fifth transistor are turned off.

Next, as shown in FIGS. 5 and 12, in the seventh period (G), the gate start signal (GVST) is at a high level, the emission start signal (EVST) is at a low level, and the first voltage (VSS) is a high level, the second voltage (VDD) is a low level, the first clock (CLK1) is a high level, the second clock (CLK2) is a high level, the fourth clock (CLK4) ) Is a low level, and the emission voltage EMVDD is a low level.

In this case, the first voltage VSS having a high level is supplied to the gate of the sixth transistor T6 through the twelfth transistor, the eighth transistor, the first transistor, and the third transistor. Therefore, the first transistor, the third transistor, and the sixth transistor T6 are turned off.

The second voltage VDD having a low level is supplied to the QB node QB. Therefore, the second transistor, the fourth transistor, and the fifth transistor are turned on.

Accordingly, the emission voltage EMVDD having a low level is output to the emission line EL. That is, in the seventh period G, the emission signal EM is an emission turn-on signal.

In addition, since the second transistor and the fourth transistor are turned on, the first voltage VSS at a high level is output to the n-th scan signal SCAN(n) through the second transistor, and the second transistor is turned on. The second voltage VSS at a high level is output to the n+1 scan signal SCAN(n+1) through the 4 transistors.

Finally, from the seventh period (G) to the first period (A), the emission line EL is continuously applied with a low level voltage, and the high level first scan signal SCAN ( n)) is continuously output, and the high-level second scan signal SCAN(n+1) is continuously output.

As described above, since the emission signal EM has a low level from the seventh period G to the first period A, for example, the emission transistors shown in FIG. 2 (TP3, TP4) is turned on, and accordingly, a current is supplied to the organic light emitting diode (OLED). Therefore, the organic light emitting diode may output light having brightness corresponding to the magnitude of the current.

However, in the second period (B) to the sixth period (F), that is, the five horizontal periods, the emission signal has a high level. That is, the emission signal EM of the second period B to the sixth period F is an emission turnoff signal. When the emission turnoff signal is supplied to the emission transistors TP3 and TP4 shown in FIG. 2, the emission transistors TP3 and TP4 are turned off.

While the emission transistors TP3 and TP4 are turned off, a scan turn-on signal of the n-th scan signal SCAN(n) and a scan turn-on of the n+1 scan signal SCAN(n+1). A signal is supplied to the pixel driving circuit PDC, and accordingly, the data voltage Vdata and the threshold voltage of the driving transistor Tdr may be charged to the gate of the driving transistor Tdr.

In the seventh period G, the emission signal EM again has a low level. In this case, as described in the description of FIG. 2, current is supplied to the organic light emitting diode OLED through the driving transistor Tdr, and light having brightness corresponding to the current may be output.

That is, through the processes described above, the organic light emitting diode OLED may output light corresponding to the data voltage Vdata.

13 is another exemplary view showing a configuration of one of the stages shown in FIG. 3, and FIG. 14 is an exemplary view showing waveforms of signals applied to the stage shown in FIG. 13. In the following description, contents identical or similar to those described with reference to FIGS. 1 to 12 are omitted or simply described.

As described above, the organic light emitting display device according to the present invention includes the organic light emitting display panel 100, the data driver 300, the gate driver 200 and the control unit 400. The gate driver 200 includes a plurality of stages (Stage 1 to Stage e).

Each of the stages includes a first scan generator 220, a second scan generator 230, an emission generator 240, and a stage controller 250, as shown in FIG. 13.

Here, the first scan generation unit 220, the second scan generation unit 230 and the construction of the emission generation unit 240, the first scan generation unit 220 shown in Figure 4, the first This is the same as the configuration of the 2 scan generation unit 230 and the emission generation unit 240. Accordingly, reference numerals of the first scan generator 220, the second scan generator 230, and the emission generator 240 shown in FIG. 13 indicate that the first scan shown in FIG. 4 is generated. It is the same as the reference numerals of the unit 220, the second scan generation unit 230, and the emission generation unit 240.

The function of the stage control unit 250 is the same as that of the stage control unit 210 shown in FIG. 4, but the specific structure thereof is different.

That is, in the stage control unit 250 illustrated in FIG. 13, a seventh transistor T7 turned on or off by the gate start signal GVST and a first terminal connected to a second terminal of the seventh transistor An eighth transistor T8 connected to the first scan generator, the second scan generator, and the emission generator, and turned on by a second voltage having a low level supplied to a gate. , A ninth transistor (T9) that is turned on or off by a fourth clock, and a first terminal is connected to a first terminal of the seventh transistor and a gate of the eighth transistor, and a first terminal of the ninth transistor A thirteenth transistor (T13) connected to a second terminal, a second terminal connected to the first scan generator, the second scan generator and the emission generator, and supplied with the emission start signal to a gate. , A first terminal is connected to the second terminal of the thirteenth transistor, the first scan generator, the second scan generator and the emission generator, and a first voltage having a high level is supplied to the second terminal And a gate connected to a second terminal of the eighth transistor T10 and a gate connected to a second terminal of the thirteenth transistor and a first terminal of the tenth transistor, and the first terminal of the It is connected to the second terminal of the seventh transistor, and includes a fourteenth transistor T14 to which the first voltage is supplied to the second terminal.

To explain further, the eleventh transistor T11 and the twelfth transistor T12 shown in FIG. 4 are replaced with the thirteenth transistor T13 and the fourteenth transistor T14 in FIG. 13.

Accordingly, the stage shown in FIG. 13 is a first transistor T1 connected to a scan line through which a first clock is supplied to a first terminal, and a second terminal is connected to a scan line through which an nth scan signal is output among the two scan signals. ), the first terminal is connected to the second terminal of the first transistor, the second terminal is a second transistor (T2) to which a first voltage having a high level is supplied, and a second clock is supplied to the first terminal, , The second terminal is a third transistor T3 connected to a scan line from which the n+1 scan signal is output among the two scan signals, and the first terminal is connected to a second terminal of the third transistor. The second terminal is a fourth transistor T4 to which the first voltage is supplied, and an emission voltage having a low level is supplied to the first terminal, and the second terminal is connected to an emission line from which the emission signal is output. The fifth transistor (T5), the first terminal is connected to the second terminal of the fifth transistor, and the second terminal is a sixth transistor (T6) to which the first voltage is supplied, turned on or turned by a gate start signal A seventh transistor (T7) being turned off, a first terminal is connected to a second terminal of the seventh transistor, and a second terminal is connected to the first scan generator, the second scan generator and the emission generator The eighth transistor T8 is turned on by a second voltage having a low level supplied to the gate, and is turned on or off by a fourth clock, and a first terminal is a first terminal of the seventh transistor and the first The ninth transistor (T9) connected to the gate of the 8 transistor, the first terminal is connected to the second terminal of the ninth transistor, the second terminal is the gate of the first transistor, the gate of the third transistor and the first 6 is connected to the gate of the transistor, the 13th transistor (T13) to which the emission start signal is supplied to the gate, the first terminal is connected to the second terminal of the 13th transistor, and the first voltage is supplied to the second terminal And a tenth transistor T10 having a gate connected to the second terminal of the eighth transistor And a gate connected to the second terminal of the thirteenth transistor and the first terminal of the tenth transistor, the first terminal connected to the second terminal of the seventh transistor, and the first voltage supplied to the second terminal. It includes a fourteenth transistor (T14).

The pulses constituting the first clock CLK1, the second clock CLK2, and the fourth clock CLK4 have a width of two horizontal periods, as shown in FIG. 14, and the first clock ( The phase of CLK1) is one horizontal period faster than the phase of the second clock CLK2, and the phase of the second clock CLK2 is two horizontal periods earlier than the phase of the fourth clock CLK4.

In this case, the emission turnoff signal constituting the emission signal EM, that is, the emission signal EM at a high level has a width of 4 horizontal periods, as shown in FIG. 14. 4 horizontal period means a period in which 1 horizontal period is repeated 4 times.

That is, when the stage shown in FIG. 4 is applied, the width of the emission turn-off signal is 5 horizontal periods, but when the stage shown in FIG. 13 is applied, the width of the emission turn-off signal is 4 It can be a horizontal period.

Therefore, depending on the width of the emission turn-off signal required for driving the organic light emitting display device, the stage shown in FIG. 4 may be used, or the stage shown in FIG. 13 may be used.

In this case, the method in which the stage illustrated in FIG. 13 is driven using the waveforms illustrated in FIG. 14 is similar to the method in which the stage illustrated in FIG. 4 is driven using the waveforms illustrated in FIG. 5, and thus detailed Description is omitted.

According to the present invention as described above, the scan signal and the emission signal can be generated in one stage, and thus, the width of the non-display area of the organic light emitting display panel provided with the gate driver 200 including the stage. This may be narrower than the width of the non-display area of the conventional organic light emitting display panel. Therefore, according to the present invention, an organic light emitting display device having a narrower non-display area than the prior art can be provided.

Those skilled in the art to which the present invention pertains will appreciate that the present invention may be implemented in other specific forms without changing its technical spirit or essential characteristics. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the above detailed description, and it should be interpreted that all changes or modifications derived from the meaning and scope of the claims and equivalent concepts are included in the scope of the present invention. do.

100: panel 200: gate driver
300: data driver 400: control unit
500: emission signal generator 600: scan signal generator

Claims (14)

An organic light emitting diode, a pixel driving circuit for driving the organic light emitting diode, a scan line connected to a switching transistor provided in the pixel driving circuit, an emission transistor provided in the pixel driving circuit to control the emission timing of the organic light emitting diode An organic light emitting display panel including pixels including a connected emission line and a data line connected to the switching transistor;
A data driver supplying a data voltage to the data line provided along a first direction of the organic light emitting display panel;
A gate driver including stages; And
It includes a control unit for driving the data driver and the gate driver,
Each of the stages, an organic light emitting display device that outputs two scan signals and one emission signal. According to claim 1,
Each of the two scan signals is supplied to pixels provided in a line along a second direction different from the first direction,
The emission line is an organic light emitting display device that supplies the emission signal to two pixels adjacent to each other along the data line. According to claim 1,
Each of the stages,
A first scan generator generating an n-th scan signal among the two scan signals;
A second scan generator which generates an n+1 scan signal among the two scan signals;
An emission generator that generates the emission signal; And
And a stage control unit that receives the gate start signal and the emission start signal and controls the first scan generation unit, the second scan generation unit, and the emission generation unit. The method of claim 3,
The first scan generating unit,
A first transistor outputting a first clock as the n-th scan signal under the control of the stage control unit; And
And a second transistor outputting a first voltage having a high level as the n-th scan signal under the control of the stage control unit. The method of claim 3,
The second scan generating unit,
A third transistor outputting a second clock as the n+1 scan signal under the control of the stage controller; And
And a fourth transistor outputting a first voltage having a high level as the n+1 scan signal under the control of the stage control unit. The method of claim 3,
The emission generation unit,
A fifth transistor outputting an emission voltage having a low level as the emission signal under the control of the stage control unit; And
And a sixth transistor outputting a first voltage having a high level as the emission signal under the control of the stage control unit. The method of claim 3,
The stage control unit,
A seventh transistor turned on or off by the gate start signal;
The first terminal is connected to the second terminal of the seventh transistor, and the second terminal is connected to the first scan generation unit, the second scan generation unit and the emission generation unit, and provides a low level supplied to the gate. An eighth transistor turned on by the second voltage having;
A ninth transistor turned on or off by a fourth clock, the first terminal being connected to the first terminal of the seventh transistor and the gate of the eighth transistor;
A first terminal is connected to the second terminal of the ninth transistor, the first scan generator, the second scan generator and the emission generator, and a first voltage having a high level is supplied to the second terminal. , A tenth transistor having a gate connected to a second terminal of the eighth transistor;
An eleventh transistor in which the emission start signal is supplied to a gate, and a second terminal is connected to the first scan generator, the second scan generator, and the emission generator; And
An organic light emitting display including a twelfth transistor having a gate connected to a first terminal of the eleventh transistor, a first terminal connected to a second terminal of the seventh transistor, and the first voltage supplied to a second terminal. Device. According to claim 1,
Each of the stages,
A first transistor is supplied to the first terminal, and the second terminal is a first transistor connected to a scan line from which the nth scan signal is output among the two scan signals;
The first terminal is connected to the second terminal of the first transistor, and the second terminal is a second transistor to which a first voltage having a high level is supplied.
A second transistor is supplied to the first terminal, and the second terminal is a third transistor connected to a scan line through which an n+1 scan signal is output among the two scan signals;
A first transistor connected to a second terminal of the third transistor, and a fourth transistor supplied with the first voltage to the second terminal;
An emission voltage having a low level is supplied to the first terminal, and the second terminal includes a fifth transistor connected to an emission line from which the emission signal is output;
A first terminal connected to a second terminal of the fifth transistor, and a sixth transistor to which the first voltage is supplied to the second terminal;
A seventh transistor turned on or off by a gate start signal;
The first terminal is connected to the second terminal of the seventh transistor, and the second terminal is connected to the first scan generation unit, the second scan generation unit and the emission generation unit, and provides a low level supplied to the gate. An eighth transistor turned on by the second voltage having;
A ninth transistor turned on or off by a fourth clock, the first terminal being connected to the first terminal of the seventh transistor and the gate of the eighth transistor;
A first terminal is connected to the second terminal of the ninth transistor, the gate of the first transistor, the gate of the third transistor and the gate of the sixth transistor, and the first voltage is supplied to the second terminal, and the gate A tenth transistor connected to the second terminal of the eighth transistor;
An eleventh transistor in which an emission start signal is supplied to a gate, and a second terminal is connected to a gate of the second transistor, a gate of the fourth transistor, and a gate of the fifth transistor; And
An organic light emitting display including a twelfth transistor having a gate connected to a first terminal of the eleventh transistor, a first terminal connected to a second terminal of the seventh transistor, and the first voltage supplied to a second terminal. Device. The method of claim 8,
The pulses constituting the first clock, the second clock, and the fourth clock have a width of two horizontal periods, and the phase of the first clock is one horizontal period earlier than the phase of the second clock, and the second clock The phase of the organic light emitting display device is two horizontal periods faster than the phase of the fourth clock. The method of claim 7,
The emission turn-off signal constituting the emission signal has an width of 5 horizontal periods. The method of claim 3,
The gate start signal is one of two scan signals output from another stage,
The emission start signal is an emission signal output from the front end stage. The method of claim 3,
The stage control unit,
A seventh transistor turned on or off by the gate start signal;
The first terminal is connected to the second terminal of the seventh transistor, and the second terminal is connected to the first scan generation unit, the second scan generation unit and the emission generation unit, and provides a low level supplied to the gate. An eighth transistor turned on by the second voltage having;
A ninth transistor turned on or off by a fourth clock, the first terminal being connected to the first terminal of the seventh transistor and the gate of the eighth transistor;
A first terminal is connected to the second terminal of the ninth transistor, and a second terminal is connected to the first scan generator, the second scan generator and the emission generator, and the emission start signal is a gate. A thirteenth transistor to which is supplied;
A first terminal is connected to the second terminal of the thirteenth transistor, the first scan generator, the second scan generator and the emission generator, and a first voltage having a high level is supplied to the second terminal. , A tenth transistor having a gate connected to a second terminal of the eighth transistor; And
A gate is connected to the second terminal of the thirteenth transistor and the first terminal of the tenth transistor, the first terminal is connected to the second terminal of the seventh transistor, and the first voltage is supplied to the second terminal An organic light emitting display device comprising a 14th transistor. The method of claim 12,
The emission turn-off signal constituting the emission signal has an width of 4 horizontal periods. According to claim 1,
Each of the stages,
A first transistor is supplied to the first terminal, and the second terminal is a first transistor connected to a scan line from which the nth scan signal is output among the two scan signals;
The first terminal is connected to the second terminal of the first transistor, and the second terminal is a second transistor to which a first voltage having a high level is supplied.
A second transistor is supplied to the first terminal, and the second terminal is a third transistor connected to a scan line through which an n+1 scan signal is output among the two scan signals;
A first transistor connected to a second terminal of the third transistor, and a fourth transistor supplied with the first voltage to the second terminal;
An emission voltage having a low level is supplied to the first terminal, and the second terminal includes a fifth transistor connected to an emission line from which the emission signal is output;
A first terminal connected to a second terminal of the fifth transistor, and a sixth transistor to which the first voltage is supplied to the second terminal;
A seventh transistor turned on or off by a gate start signal;
The first terminal is connected to the second terminal of the seventh transistor, and the second terminal is connected to the first scan generation unit, the second scan generation unit and the emission generation unit, and provides a low level supplied to the gate. An eighth transistor turned on by the second voltage having;
A ninth transistor turned on or off by a fourth clock, the first terminal being connected to the first terminal of the seventh transistor and the gate of the eighth transistor;
The first terminal is connected to the second terminal of the ninth transistor, the second terminal is connected to the gate of the first transistor, the gate of the third transistor and the gate of the sixth transistor, and an emission start signal as a gate A thirteenth transistor to which is supplied;
A tenth transistor having a first terminal connected to a second terminal of the thirteenth transistor, the first voltage supplied to a second terminal, and a gate connected to a second terminal of the eighth transistor; And
A gate is connected to the second terminal of the thirteenth transistor and the first terminal of the tenth transistor, the first terminal is connected to the second terminal of the seventh transistor, and the first voltage is supplied to the second terminal An organic light emitting display device comprising a fourteenth transistor.

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