KR102548793B1 - Apparatus for testing semiconductor devices - Google Patents

Abstract

A test apparatus for inspecting electrical characteristics of semiconductor devices is disclosed. A semiconductor device test apparatus combines an insert having a pocket for accommodating a semiconductor device and having an open bottom surface of the pocket, a test socket disposed to face the semiconductor device accommodated in the insert and connected to the semiconductor device, and a test socket. and a socket guide facing the insert and having a socket opening for exposing the test socket so that the test socket is connected to the semiconductor device. Here, in order to guide the coupling position of the insert and the socket guide, one of the insert and the socket guide may include at least three guide pins, and the other may include at least three guide holes into which the guide pins are inserted. The guide pins may be arranged in a triangular shape around the opening of the pocket or the opening of the socket. Accordingly, the semiconductor device testing apparatus may prevent the insert and the socket guide from being distorted and improve alignment accuracy and precision.

Description

Semiconductor device testing device {Apparatus for testing semiconductor devices}

Embodiments of the present invention relate to a semiconductor device testing apparatus for inspecting a semiconductor device. More particularly, it relates to a semiconductor device testing apparatus for testing electrical characteristics of semiconductor devices by providing test signals to the semiconductor devices.

In general, semiconductor devices may be formed on a silicon wafer used as a semiconductor substrate by repeatedly performing a series of manufacturing processes, and the semiconductor devices thus formed may be manufactured as finished products through a dicing process, a bonding process, and a packaging process. .

These semiconductor devices may be judged to be good or defective through electrical property tests. A semiconductor device test apparatus including a plurality of transfer modules for transferring semiconductor devices, a test module for inspecting semiconductor devices, and an interface module for connecting the semiconductor devices and the test module to each other may be used for the electrical property test. there is.

The interface module may include an interface board disposed between the test module and the insert accommodating the semiconductor devices, and socket guides mounted on the interface board.

In addition, the semiconductor device testing apparatus may include a support film for guiding positions of solder balls of semiconductor devices and a match plate for connecting the semiconductor devices and test sockets to each other.

The support film may be disposed between the insert and the socket guide to support the semiconductor device, and may include guide holes into which solder balls are inserted.

The match plate may include a plurality of pushers that press the semiconductor devices toward the test sockets to connect solder balls of the semiconductor devices and contact terminals of the test sockets.

A test process for semiconductor devices can be divided into a high-temperature process and a low-temperature process. As an example, the high-temperature process is performed at a test temperature of about 85°C to 130°C, and the low-temperature process is about -55°C to about 130°C. - It can be performed at a test temperature of about 5℃. For the high-temperature process and the low-temperature process as described above, thermoelectric elements for controlling temperatures of the semiconductor elements may be mounted on the match plate through the pushers.

Test sockets for connection with semiconductor devices are mounted on the socket guide, and passive devices such as resistors, condensers, and amplifiers for signal conversion and power supply devices for testing semiconductor devices can be mounted on the lower surface of the interface board. there is. Here, the socket guide has an opening for exposing the test socket so that the semiconductor device and the test socket are connected.

Meanwhile, the alignment of the insert and the test socket may be achieved by alignment between the socket guide and the insert and alignment between the socket guide and the test socket. Here, alignment between the socket guide and the insert may be achieved by guide pins provided in the socket guide and guide holes formed in the insert to insert the guide pins.

Two guide pins and two guide holes are provided, and the two guide pins face each other with an opening exposing the test socket interposed therebetween. In this way, since the insert and the socket guide are aligned by the two guide pins and the two guide holes in the semiconductor device test apparatus, when the distance between the guide pin and the guide hole is about 30 μm or more, the X/Y axes of the guide pin and the guide hole are aligned. Misalignment of the insert and the socket guide may occur due to misalignment of the X/Y axes, and if the distance between the guide pin and the guide hole is less than about 10㎛, the insertion of the guide pin and the wear of the guide hole increase, resulting in a decrease in inspection reliability. . Moreover, it is difficult to improve precision because thermal deformation may occur in the guide hole due to the process of heat-sealing the support film to the insert and the high-temperature test process.

(001) Korea Patent Publication No. 10-2013-0050592 (2013.05.16)

An object of the present invention is to provide a semiconductor device testing apparatus capable of improving alignment accuracy between an insert and a socket guide.

In order to achieve the above object, a semiconductor device testing apparatus according to an aspect of the present invention includes an insert having a pocket for accommodating a semiconductor device and having an open bottom surface of the pocket, and facing the semiconductor device accommodated in the insert. A socket guide having a test socket disposed to be connected to the semiconductor device and a socket opening for exposing the test socket so that the test socket is coupled and coupled to face the insert so that the test socket is connected to the semiconductor device. can include In addition, in order to guide a coupled position between the insert and the socket guide, one of the insert and the socket guide may include at least three guide pins, and the other may include at least three guide holes into which the guide pins are inserted. can Furthermore, the three guide pins may be arranged in a triangular shape around the opening of the pocket or the opening of the socket.

According to embodiments of the present invention, two of the three guide pins are disposed to face each other with the pocket opening or the socket opening interposed therebetween, and the other guide pins are arranged in a diagonal direction with respect to the two guide pins. can be placed as

According to embodiments of the present invention, among the three guide holes, two guide holes disposed facing each other with the pocket opening or the socket opening interposed therebetween are elongated long holes in the direction in which the two guide holes are disposed. It may be made of, and the other one may be made of a regular hole.

According to embodiments of the present invention, any one of the three guide pins may be positioned opposite to the other guide pins with the pocket opening or the socket opening interposed therebetween.

According to embodiments of the present invention, each of the guide pins may have a dome shape.

According to embodiments of the present invention, each of the guide holes may be provided in a tapered shape gradually narrowing away from an inlet into which the guide pin is inserted, and make line contact with the inserted guide pin.

According to embodiments of the present invention, each of the guide pins may include a tapered base portion positioned at an entrance of the guide hole and a pillar portion extending upward from the base portion. Furthermore, a portion of the guide hole in contact with the base portion may be tapered to be the same as that of the base portion so as to come into surface contact with the base portion.

According to the embodiments of the present invention as described above, a test apparatus for inspecting electrical characteristics of semiconductor devices includes three guide pins and three guide holes arranged in a triangular shape to align an insert and a socket guide. Accordingly, distortion of the insert and the socket guide can be prevented and alignment accuracy and precision can be improved. Accordingly, since the semiconductor device and the test socket can be aligned, the test reliability of the semiconductor device test apparatus can be improved.

In addition, the insert is provided with guide holes consisting of two long holes to respond to thermal deformation caused by the thermal splicing process of the support film and one regular hole to increase alignment accuracy between the insert and the socket guide, thereby preventing alignment errors between the insert and the socket guide. can be prevented and the alignment accuracy can be improved.

In addition, the semiconductor device testing apparatus includes a guide pin and a guide hole that are in line contact or partially in surface contact with each other, thereby preventing jamming of the guide pin and minimizing wear of the guide hole.

1 is a schematic exploded cross-sectional view illustrating a semiconductor device testing apparatus according to an exemplary embodiment of the present invention.
FIG. 2 is a schematic partially exploded perspective view for explaining a coupling relationship between an insert and a socket guide shown in FIG. 1 .
Figure 3 is a schematic partial plan view for explaining the insert shown in Figure 2;
FIG. 4 is a schematic partial plan view for explaining the socket guide shown in FIG. 2 .
5 is a schematic partially exploded perspective view for explaining another example of the insert and the socket guide shown in FIG. 2;
6 is a schematic plan view for explaining the socket guide shown in FIG. 5;
Figure 7 is a schematic partial cross-sectional view for explaining the coupling relationship between the guide hole and the guide pin shown in Figure 5;
8 is a schematic partial cross-sectional view for explaining another example of a guide hole and a guide pin shown in FIG. 7 .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention does not have to be configured as limited to the embodiments described below and may be embodied in various other forms. The following examples are not provided to fully complete the present invention, but rather to fully convey the scope of the present invention to those skilled in the art.

In the embodiments of the present invention, when one element is described as being disposed on or connected to another element, the element may be directly disposed on or connected to the other element, and other elements may be interposed therebetween. It could be. Alternatively, when an element is described as being directly disposed on or connected to another element, there cannot be another element between them. The terms first, second, third, etc. may be used to describe various items such as various elements, compositions, regions, layers and/or parts, but the items are not limited by these terms. will not

Technical terms used in the embodiments of the present invention are only used for the purpose of describing specific embodiments, and are not intended to limit the present invention. In addition, unless otherwise limited, all terms including technical and scientific terms have the same meaning as can be understood by those skilled in the art having ordinary knowledge in the technical field of the present invention. The above terms, such as those defined in conventional dictionaries, shall be construed to have a meaning consistent with their meaning in the context of the relevant art and description of the present invention, unless expressly defined, ideally or excessively outwardly intuition. will not be interpreted.

Embodiments of the present invention are described with reference to schematic illustrations of idealized embodiments of the present invention. Accordingly, variations from the shapes of the illustrations, eg, variations in manufacturing methods and/or tolerances, are fully foreseeable. Accordingly, embodiments of the present invention are not to be described as being limited to specific shapes of regions illustrated as diagrams, but to include variations in shapes, and elements described in the drawings are purely schematic and their shapes is not intended to describe the exact shape of the elements, nor is it intended to limit the scope of the present invention.

1 is a schematic exploded cross-sectional view for explaining a semiconductor device testing apparatus according to an embodiment of the present invention, and FIG. 2 is a schematic partially exploded perspective view for explaining a coupling relationship between an insert and a socket guide shown in FIG. 1 .

Referring to FIGS. 1 and 2 , a semiconductor device testing apparatus 100 according to an embodiment of the present invention may be used to test electrical characteristics of a semiconductor device 10 . For example, the semiconductor device testing apparatus 100 provides an electrical test signal to the semiconductor device 10 and analyzes a signal output from the semiconductor device 10 in response to the test signal. ) to inspect the electrical performance.

Specifically, the semiconductor device test apparatus 100 includes an insert 110 in which the semiconductor device 10 is accommodated, a socket guide 120 disposed under the insert 110, and the socket guide 120. and a test socket 130 connected to the semiconductor device 10 and a match plate 140 pressing the semiconductor device 10 toward the test socket 130 .

Although not shown in the drawings, the semiconductor device testing apparatus 100 includes a test tray (not shown) in which a plurality of inserts 110 are installed and a test chamber (not shown) providing a space for performing an electrical characteristic test on semiconductor devices. city) may be included. In addition, the semiconductor device testing apparatus 100 includes a plurality of transfer modules (not shown) for transferring semiconductor devices from a customer tray (not shown) to the test tray and transferring the test tray containing the semiconductor devices into the test chamber. city) may be included. The transfer modules carry out the test tray from the test chamber after the inspection process is completed in the test chamber, and transfer the semiconductor devices stored in the test tray to an empty customer tray. In addition, the semiconductor device test apparatus 100 includes a preheating chamber (not shown) for previously adjusting the temperature of the semiconductor device 10 and a heat removal chamber (not shown) for restoring the temperature of the semiconductor device 10 to room temperature. ) may be included.

FIG. 3 is a schematic partial plan view for explaining the insert shown in FIG. 2 , and FIG. 4 is a schematic partial plan view for explaining the socket guide shown in FIG. 2 .

1 to 3 , the semiconductor device 10 transferred from the customer tray may be accommodated in the insert 110 . The insert 110 has a pocket 112 in which the semiconductor device 10 is accommodated, and the semiconductor device 10 and the test socket 130 are connected to a bottom surface forming the pocket 112. An opening 114 is formed. Although not shown in detail in the drawings, a latch (not shown) for fixing the semiconductor device 10 may be provided in the pocket 112 of the insert 110 . The latch fixes the position of the semiconductor device 10 by pressing an edge portion of the upper surface of the semiconductor device 10 .

A support film 150 for supporting the semiconductor device 10 may be provided below the opening 114 of the insert 110 . A plurality of terminal insertion holes 152 for guiding the position of the semiconductor element 10 by inserting a plurality of solder balls 12, which are external connection terminals of the semiconductor element 10, protrude downward into the support film 150. ) may be provided.

The socket guide 120 for guiding the position of the test socket 130 may be disposed below the insert 110, and the test socket 130 may be disposed below the socket guide 120. there is. The test socket 130 is coupled to the lower surface of the socket guide 120, and the socket guide 120 exposes the test socket 130 so that the test socket 130 and the semiconductor device 10 are connected. It is provided with a socket opening 122 for

2 to 4 , the contact terminals 132 of the test socket 130 are exposed through the socket opening 122 and can be connected to the solder balls 12 of the semiconductor device 10. .

In particular, the insert 110 and the socket guide 120 include at least three guide pins 124A, 124B, and 124C and at least three guides guiding the coupling position of the insert 110 and the socket guide 120. Holes 116A, 116B, and 116C may be provided. That is, the guide pins 124A, 124B, and 124C and the guide holes 116A, 116B, and 116C align the insert 110 and the socket guide 120 with each other, and the insert 110 and the socket guide The semiconductor device 10 and the test socket 130 are aligned by the alignment of 120 .

As an example of the present invention, as shown in FIG. 2 , the guide pins 124A, 124B, and 124C are provided in the socket guide 120, and the guide holes 116A, 116B, and 116C are provided in the insert 110. However, the guide pins 124A, 124B, and 124C may be formed in the insert 110 and the guide holes 116A, 116B, and 116C may be formed in the socket guide 120 .

The guide pins 124A, 124B, and 124C are formed by protruding from the upper surface of the socket guide 120 and positioned around the socket opening 122 . In particular, among the guide pins 124A, 124B, and 124C, at least two guide pins 124A and 124B may be positioned opposite to each other with the socket opening 122 interposed therebetween. Also, the guide pins 124A, 124B, and 124C may be disposed in a triangular shape around the socket opening 122 as shown in FIG. 4 .

As an example of the present invention, as shown in FIG. 4 , among the three guide pins 124A, 124B, and 124C, the first and second guide pins 124A and 124B have the socket opening 122 therebetween. The third guide pin 124C may be disposed to face each other, and the third guide pin 124C may be disposed in a diagonal direction with respect to the first and second guide pins 124A and 124B.

The guide pins 124A, 124B, and 124C are inserted into the guide holes 116A, 116B, and 116C, and the guide holes 116A, 116B, and 116C are in one-to-one correspondence with the guide pins 124A, 124B, and 124C. Located. That is, like the guide pins 124A, 124B, and 124C, the guide holes 116A, 116B, and 116C may be arranged in a triangular shape around the opening 114 of the insert 110.

As an example of the present invention, as shown in FIG. 3 , first and second guide holes 116A corresponding to the first and second guide pins 124A and 124B among the guide holes 116A, 116B, and 116C. , 116B) are disposed facing each other with the opening 114 of the insert 110 therebetween, and the third guide holes 116C corresponding to the third guide pins 124C are the first and second guides. It may be arranged in a diagonal direction with respect to the holes 116A and 1116B.

In addition, as an example of the present invention, each of the first and second guide holes 116A and 116B is a long hole in the direction in which the first and second guide holes 116A and 116B are disposed, as shown in FIG. The third guide hole 116C may be made of a regular hole.

As described above, the semiconductor device testing apparatus 100 includes three guide pins 124A, 124B, and 124C disposed in a triangular shape to align the insert 110 and the socket guide 120, and three guide pins 124A, 124B, and 124C. By providing the guide holes 116A, 116B, and 116C, distortion of the insert 110 and the socket guide 120 may be prevented and alignment accuracy and precision may be improved. Accordingly, since the semiconductor device 10 and the test socket 130 can be positioned properly, the test reliability of the semiconductor device test apparatus 100 can be improved.

In addition, the insert 110 includes two long holes 116A and 116B for coping with thermal deformation caused by the thermal fusion process of the support film 150 (see FIG. 1), the insert 110 and the socket guide 120. ) is provided with guide holes 116A, 116B, and 116C made up of one fixed hole 116C to increase alignment accuracy, thereby preventing alignment errors between the insert 110 and the socket guide 120 and improving alignment accuracy. and wear of the guide holes 116A, 116B and 116C can be minimized.

Although not shown in the drawing, the test signal is provided to the lower side of the socket guide 120, and the electrical power of the semiconductor device 10 is determined based on the output signal output from the semiconductor device 10 in response to the test signal. A test module for checking performance may be provided.

Again, referring to FIG. 1 , the match plate 140 may be disposed above the insert 110 . The match plate 140 may include a plurality of alignment protrusions 142 to align with the insert 110 and the socket guide 120 . The insert 110 has a plurality of first insertion holes 118 corresponding to the alignment protrusions 142, and the socket guide 120 has a plurality of second insertion holes corresponding to the alignment protrusions 142. It may have a hole 126. During assembly, the alignment protrusions 142 of the match plate 140 pass through the first insertion holes 118 of the insert 110 and are inserted into the second insertion holes 126 of the socket guide 120. As a result, the match plate 140 may be aligned with the insert 110 and the socket guide 120 .

The match plate 140 may include a pusher 144 that presses the semiconductor device 10 so that the test socket 130 and the semiconductor device 10 come into contact with each other. The pusher 144 presses the semiconductor device 10 accommodated in the pocket 112 of the insert 110 toward the test socket 130 so that the solder balls 12 of the semiconductor device 10 (see FIG. 3) ) and the contact terminals 132 (see FIG. 4) of the test socket 130 are connected to each other.

As shown in FIG. 1 , the insert 110 and the match plate 140 are arranged in a horizontal direction, but the arrangement direction of the insert 110 and the match plate 140 can be changed in various ways.

FIG. 5 is a schematic partial exploded perspective view illustrating another example of the insert and socket guide illustrated in FIG. 2 , and FIG. 6 is a schematic plan view illustrating the socket guide illustrated in FIG. 5 .

5 and 6, the insert 160 and the socket guide 170 shown in FIG. 5 are shown in FIG. 2 except for guide pins 162A, 162B, and 162C and guide holes 172A, 172B, and 172C. Since it has the same configuration as the insert 10 and the socket guide 120 shown in , reference numerals are used for components other than the guide pins 162A, 162B, and 162C and the guide holes 172A, 172B, and 172C. and overlapping description thereof will be omitted.

The insert 160 includes at least three guide holes 162A, 162B, and 162C, and the socket guide 170 includes at least three guide pins 172A, 172B, 172C) may be provided.

As an example of the present invention, as shown in FIG. 6 , the guide pins 172A, 172B, and 172C may be arranged in a triangular shape around the socket opening 122 . In particular, among the guide pins 172A, 172B, and 172C, the first and second guide pins 172A and 172B are disposed to face each other, and the third guide pin 172C has the socket opening 122 therebetween. It may be located on opposite sides of the first and second guide pins 172A and 172B.

The guide holes 162A, 162B, and 162C may be disposed in a one-to-one correspondence with the guide pins 172A, 172B, and 172C, and each of the guide pins 172A, 172B, and 172C is inserted into a corresponding guide hole.

FIG. 7 is a schematic partial cross-sectional view for explaining a coupling relationship between guide holes and guide pins shown in FIG. One guide pin (172A) and the corresponding guide hole (162A) are shown as an example.

5 and 7 , the first guide pin 172A includes a base portion 72 protruding from the bottom plate 174 of the socket guide 170 and extending upward from the base portion 72. and may include a pillar portion 74 having a circular column shape. As shown in FIG. 7 , the base portion 72 has a tapered shape and is located at the inlet 62 of the guide hole 162A. The guide hole 162A is formed so that the portion of the inlet 62 in contact with the base portion 72 is tapered the same as the base portion 72, and thus, the first guide pin 172A and the guide The hole 162A is in surface contact.

Here, the guide holes 162A, 162B, and 162C and the guide pins 172A, 172B, and 172C each have the same shape.

As such, when the guide pins 172A, 172B, and 172C are inserted into the guide holes 162A, 162B, and 162C, the guide pins and the guide holes are in surface contact with each other, so that the insert 160 and the socket The guide 170 may prevent the guide pins 172A, 172B, and 172C from being jammed and minimize wear of the guide holes 162A, 162B, and 162C.

8 is a schematic cross-sectional view for explaining another example of a guide hole and a guide pin shown in FIG. 7 .

5 and 8, the guide pin 176 may have a dome shape unlike the guide pin 172A shown in FIG. 7, and the guide hole 164 also has a guide hole 162A shown in FIG. Unlike , the longitudinal section has an overall tapered shape. For example, the guide hole 164 may have a conical shape, and thus, the guide pin 176 and the guide hole 164 are in line contact.

As such, when the guide pin 176 is inserted into the guide hole 164, the guide pin 176 and the guide hole 164 are in line contact with each other, so that the insert 160 and the socket guide 170 ) can prevent the guide pin 176 from being jammed and minimize misalignment due to thermal deformation of the guide hole 164 and wear of the guide hole 164 .

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. You will understand that there is

10: semiconductor device 100: semiconductor device test device
110, 160: insert 112: pocket
114: opening 118: first insertion hole
116A, 116B, 116C, 162A, 162B, 162C, 164: guide hole
120, 170: socket guide 122: socket opening
124A, 124B, 124C, 172A, 172B, 172C, 176: guide pin
126: second insertion hole 130: test socket
140: match plate 142: alignment protrusion
144: pusher 150: support film

Claims (7)

an insert having a pocket for accommodating a semiconductor device and having an open bottom surface of the pocket;
a test socket disposed to face the semiconductor device accommodated in the insert and connected to the semiconductor device; and
A socket guide having a socket opening for exposing the test socket so that the test socket is coupled and coupled to face the insert and the test socket is connected to the semiconductor device,
one of the insert and the socket guide is provided with at least three guide pins and the other is provided with at least three guide holes into which the guide pins are inserted, in order to guide a coupled position between the insert and the socket guide;
The three guide pins are arranged in a triangular shape around the pocket opening or the socket opening,
Each of the guide pins has a dome shape, and each of the guide holes has a tapered shape that gradually narrows as it moves away from the entrance into which the guide pin is inserted, and makes line contact with the inserted guide pin. Device. According to claim 1,
Two of the three guide pins are disposed facing each other with the pocket opening or the socket opening interposed therebetween, and the other guide pin is disposed in a diagonal direction with respect to the two guide pins. test device. delete According to claim 1,
wherein one of the three guide pins is positioned opposite to the other guide pins with the pocket opening or the socket opening interposed therebetween. delete delete delete

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