KR102526011B1 - Display panel and display device - Google Patents

Abstract

Embodiments of the present invention relate to a display panel and a display device, in which source/drain electrodes of thin film transistors that control driving of adjacent subpixels are disposed on different layers, thereby reducing an area in which wiring is arranged, thereby increasing the number of subpixels. The aperture ratio can be improved. In addition, by disposing color filters representing the same color in subpixels disposed on both sides of an area where data lines are not disposed, a color mixing phenomenon can be prevented and a part of the black matrix can be removed in a display panel displaying a high-resolution image. The effect of improving the aperture ratio can be maximized.

Description

Display panel and display device {DISPLAY PANEL AND DISPLAY DEVICE}

Embodiments of the present invention relate to display panels and display devices.

As the information society develops, the demand for display devices that display images is increasing, and liquid crystal display devices, plasma display devices, and organic light emitting display devices are increasing. Various types of display devices such as and the like are being utilized.

Such a display device includes a display panel on which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels defined by intersections of the gate lines and data lines are arranged. And, various driving circuits such as gate driving circuits and data driving circuits for driving such gate lines and data lines are included.

The gate driving circuit drives the gate lines by outputting scan signals to the plurality of gate lines. In addition, the data driving circuit supplies data voltages to a plurality of data lines according to the timing at which the scan signal is applied so that each subpixel can display a brightness corresponding to the data voltage and display an image.

Meanwhile, in such a display device, the number of subpixels disposed per unit area in a display panel is increasing in order to display a high-resolution image. That is, according to the demand for high resolution, the size of subpixels is getting smaller.

However, it is difficult to make signal wires such as gate lines or data lines disposed in these sub-pixels thinner due to resistance. Accordingly, although the size of the subpixel is getting smaller, there is a problem that the aperture ratio of the subpixel is lowered and the efficiency of the display panel is lowered due to the limitation of the signal line disposed in the subpixel.

An object of embodiments of the present invention is to provide a subpixel structure capable of improving an aperture ratio of a subpixel in a display panel exhibiting high resolution, and a display panel and display device including the subpixel.

An object of embodiments of the present invention is to provide a display panel and a display device capable of maintaining screen quality while maximizing the aperture ratio of subpixels through a color filter arrangement structure in a subpixel structure that improves the aperture ratio of the subpixels. .

An object of the embodiments of the present invention is to minimize the structural change of the non-active area of the display panel according to the subpixel structure in which the aperture ratio of the subpixel is improved, so that the subpixel with the improved aperture ratio can be easily implemented. and a display device.

In one aspect, embodiments of the present invention provide a display panel in which a plurality of subpixels defined by a plurality of gate lines, a plurality of data lines, and intersections of the gate lines and the data lines are arranged.

The display panel includes a first data line, a first electrode electrically connected to the first data line, a first insulating layer disposed on the first data line and the first electrode, and a first insulating layer disposed on the first insulating layer. A gate electrode, a second insulating layer disposed on the gate electrode, a second data line disposed on the second insulating layer, and a second electrode disposed on the second insulating layer and electrically connected to the second data line; , a planarization layer disposed on the second data line and the second electrode, a first pixel electrode disposed in a first subpixel on the planarization layer and electrically connected to the first electrode through a first contact hole, and a first pixel electrode disposed on the planarization layer. It may include a second pixel electrode disposed in 2 subpixels and electrically connected to the second electrode through a second contact hole.

On the other hand, embodiments of the present invention provide a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are disposed and include an active area and a non-active area; and a gate driving the plurality of gate lines. A display device including a driving circuit and a data driving circuit driving a plurality of data lines.

In such a display device, the active area of the display panel includes a first data line, a first electrode electrically connected to the first data line, a first insulating layer disposed on the first data line and the first electrode, and a first electrode. A gate electrode disposed on the first insulating layer, a second insulating layer disposed on the gate electrode, a second data line disposed on the second insulating layer, and a second data line disposed on the second insulating layer and A second electrode electrically connected, a planarization layer disposed on the second data line and the second electrode, and a first pixel disposed in a first subpixel on the planarization layer and electrically connected to the first electrode through a first contact hole. An electrode and a second pixel electrode disposed in the second subpixel on the planarization layer and electrically connected to the second electrode through the second contact hole.

According to embodiments of the present invention, transistors for driving subpixels disposed on both sides of a region where data lines are disposed are disposed on different layers and the transistors are controlled through a shared gate electrode, thereby providing data to the subpixels. By reducing the area where the line is arranged, the aperture ratio of the sub-pixel can be improved.

According to embodiments of the present invention, a color filter representing the same color is disposed in two subpixels located between regions where data lines are disposed, so that a black matrix disposed between subpixels can be removed, thereby reducing the number of subpixels. to maximize the aperture ratio of

According to embodiments of the present invention, a display panel having a subpixel structure in which an aperture ratio is improved while minimizing a structural change in a non-active region of a display panel by minimizing a change in a transistor arrangement process for improving an aperture ratio of a subpixel. make it easy to implement.

1 is a diagram showing a schematic configuration of a display device according to embodiments of the present invention.
2 is a diagram illustrating an example of a circuit structure of a subpixel in a display device according to embodiments of the present invention.
3 is a diagram showing a first example of a planar structure of subpixels in a display device according to embodiments of the present invention.
FIG. 4 is a diagram illustrating an example of a cross-sectional structure of an AA′ portion and a BB′ portion in a planar structure of a subpixel shown in FIG. 3 .
5 is a diagram showing a second example of a planar structure of subpixels in a display device according to embodiments of the present invention.
FIG. 6 is a diagram showing an example of a cross-sectional structure of CC' portion in the planar structure of the subpixel shown in FIG. 5 .
7 is a diagram illustrating a third example of a planar structure of subpixels in a display device according to embodiments of the present invention.
FIG. 8 is a diagram illustrating an example of a cross-sectional structure of a DD′ part in a planar structure of a subpixel shown in FIG. 7 .
9 is a diagram showing a fourth example of a planar structure of subpixels in a display device according to embodiments of the present invention.
FIG. 10 is a diagram illustrating an example of a cross-sectional structure of an EE' portion in a planar structure of a subpixel shown in FIG. 9 .
11 is a diagram illustrating an example of a cross-sectional structure of a non-active area in a display device according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention are described in detail below with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

1 shows a schematic configuration of a display device 100 according to embodiments of the present invention.

Referring to FIG. 1 , a display device 100 according to embodiments of the present invention includes a display panel 110 on which a plurality of subpixels (SP) are arranged, and a gate driving circuit for driving the display panel 110. 120, a data driving circuit 130, a controller 140, and the like.

In the display panel 110, a plurality of gate lines GL and a plurality of data lines DL are disposed, and a subpixel SP is disposed in an area where the gate lines GL and data lines DL intersect. .

The gate driving circuit 120 is controlled by the controller 140 and sequentially outputs scan signals to the plurality of gate lines GL disposed on the display panel 110 to drive timing of the plurality of subpixels SP. to control

The gate driving circuit 120 may include one or more gate driver integrated circuits (GDICs), and may be located on only one side of the display panel 110 or on both sides depending on the driving method. may be

The data driving circuit 130 receives video data from the controller 140 and converts the video data into analog data voltages. Data voltages are output to each data line DL at the timing when the scan signal is applied through the gate line GL so that each subpixel SP expresses brightness according to the image data.

The data driving circuit 130 may include one or more Source Driver Integrated Circuits (SDICs).

The controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130 and controls operations of the gate driving circuit 120 and the data driving circuit 130 .

The controller 140 causes the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and converts image data received from the outside to suit the data signal format used by the data driving circuit 130. and outputs the converted image data to the data driving circuit 130 .

The controller 140 transmits various timing signals including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable signal (DE, Data Enable), and a clock signal (CLK) together with the video data to the outside. (e.g. host system).

The controller 140 may generate various control signals using various timing signals received from the outside and output them to the gate driving circuit 120 and the data driving circuit 130 .

For example, in order to control the gate driving circuit 120, the controller 140 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). It outputs various gate control signals including Gate Output Enable).

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 120 . The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal. The gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits.

In addition, the controller 140, in order to control the data driving circuit 130, a source start pulse (SSP, source start pulse), a source sampling clock (SSC, source sampling clock), a source output enable signal (SOE, source It outputs various data control signals including Output Enable).

Here, the source start pulse SSP controls data sampling start timing of one or more source driver integrated circuits constituting the data driving circuit 130 . The source sampling clock (SSC) is a clock signal that controls sampling timing of data in each source driver integrated circuit. The source output enable signal SOE controls output timing of the data driving circuit 130 .

The display device 100 includes a power management integrated circuit that supplies various voltages or currents to a display panel 110, a gate driving circuit 120, a data driving circuit 130, or controls various voltages or currents to be supplied. can include more.

Each subpixel SP is defined by the intersection of the gate line GL and the data line DL, and liquid crystals or light emitting elements may be disposed according to the type of the display device 100 .

For example, when the display device 100 is a liquid crystal display device, a light source device such as a backlight unit for radiating light to the display panel 110 is included, and liquid crystal is disposed in the subpixel SP of the display panel 110. do. In addition, by adjusting the arrangement of liquid crystals by an electric field formed as data voltage is applied to each sub-pixel (SP), it is possible to display an image with brightness according to image data.

Alternatively, the display device 100 may display an image by using a self-luminous device to indicate brightness according to image data. The display device 100 includes a light emitting device such as a light emitting diode (LED) or an organic light emitting diode (OLED) in each subpixel (SP), and controls a current flowing through the light emitting device according to a data voltage to display an image. can be displayed

FIG. 2 shows an example of a circuit structure of a subpixel SP in a display device 100 according to embodiments of the present invention, in the case of a liquid crystal display device as an example.

Referring to FIG. 2 , one gate line GL and one data line DL may be intersected in the subpixel SP. Alternatively, in some cases, two or more gate lines GL may be disposed between subpixels SP, or one data line DL may be disposed in each of two or more subpixels SP.

A thin film transistor TFT controlled by a scan signal applied to the gate line GL and transferring a data voltage supplied through the data line DL to the pixel electrode PXL may be disposed in the subpixel SP. there is. Also, a common electrode COM to which a common voltage is applied may be disposed, and a capacitance C may be formed between the common electrode COM and the pixel electrode PXL.

The thin film transistor TFT may include a first node N1 , a second node N2 , and a third node N3 .

The first node N1 may be a gate node of the thin film transistor TFT and is electrically connected to the gate line GL. Also, the second node N2 may be a source node or a drain node, and is electrically connected to the data line DL. The third node N3 may be a drain node or a source node, and is electrically connected to the pixel electrode PXL.

The thin film transistor TFT is turned on when a turn-on level scan signal is applied through the gate line GL, so that the data voltage supplied through the data line DL is applied to the pixel electrode PXL. .

In addition, when the arrangement of liquid crystals is adjusted according to the electric field formed by the data voltage applied to the pixel electrode PXL and the common voltage applied to the common electrode COM, the subpixel SP displays brightness according to the image data and displays an image. display

The subpixel SP may be divided into an area where the pixel electrode PXL and the common electrode COM form an electric field and an area where the gate line GL, data line DL, and thin film transistor TFT are disposed. can Here, since an image is displayed through an area where the pixel electrode PXL and the common electrode COM form an electric field, the ratio occupied by this area in the subpixel SP may be very important for screen quality.

3 illustrates a first example of a planar structure of a subpixel SP in a display device 100 according to embodiments of the present invention.

Referring to FIG. 3 , each subpixel (SP) disposed on the display panel 110 may be defined by an intersection of a gate line (GL) and a data line (DL). Also, a thin film transistor (TFT), a pixel electrode (PXL), a common electrode (COM), and the like may be disposed in each subpixel (SP).

For example, the first subpixel SP1 is defined by the intersection of the first gate line GL1 and the first data line DL1, and the intersection of the first gate line GL1 and the second data line DL2 The second subpixel SP2 may be defined by

A first pixel electrode PXL1 may be disposed in the first subpixel SP, and a thin film transistor TFT may be disposed to control data voltages to be applied to the first pixel electrode PXL1.

Such a thin film transistor (TFT) may include a gate electrode, a source electrode, a drain electrode, an active layer, and the like.

The first gate electrode G1 of the thin film transistor TFT disposed in the first subpixel SP is electrically connected to the first gate line GL1 and, as shown in FIG. 3 , the first gate line It may be a structure integrally formed with (GL1).

Also, the source electrode or the drain electrode of the thin film transistor TFT is electrically connected to the first data line DL1, and as in the example shown in FIG. 3, it is part of the first data line DL1 or the first data line. It may be a structure integrally formed with (DL1).

The drain electrode or the source electrode of the thin film transistor TFT is electrically connected to the first pixel electrode PXL1 and is indicated as the first electrode 310 in the example of FIG. 3 . The first electrode 310 may be electrically connected to the first pixel electrode PXL1 through the first contact hole CH1.

Here, the first electrode 310 is a part of the second gate electrode G2, as shown in the X portion, to compensate for the capacitance formed between the gate electrode and the source/drain electrode. It may overlap with some parts.

Also, although not shown in FIG. 3 , an active layer made of a semiconductor material may be disposed on the first gate electrode G1 .

That is, when a voltage is applied to the first gate electrode G1 by a scan signal applied to the first gate line GL1, the data voltage supplied through the first data line DL1 passes through the first electrode 310. through to the first pixel electrode PXL1. In addition, the arrangement of liquid crystals is adjusted by an electric field formed between the first pixel electrode PXL1 and the common electrode COM, so that the brightness according to the data voltage can be displayed.

FIG. 4 illustrates an example of a cross-sectional structure of parts A-A' and parts BB' in the planar structure of the subpixel SP shown in FIG. 3 .

Referring to FIG. 4 , a first gate electrode G1 and a second gate electrode G2 are disposed on a first substrate 400 . A gate insulating layer 410 is disposed on the first gate electrode G1 and the second gate electrode G2.

An active layer and source/drain electrodes constituting a thin film transistor (TFT) are disposed on the gate insulating layer 410 .

For example, the first active layer ACT1, the first data line DL1, and the first electrode 310 may be positioned on the first gate electrode G1. Here, the first data line DL1 may be a source electrode or a drain electrode, and the first electrode 310 may be a drain electrode or a source electrode.

A protective layer 420 is disposed on the source/drain electrodes, and a planarization layer 430 is disposed on the protective layer 420 .

A common electrode COM is disposed on the planarization layer 430 , and a pixel insulating layer 440 is disposed on the common electrode COM. And, the pixel electrode PXL is disposed on the pixel insulating layer 440 . Alternatively, in some cases, the pixel electrode PXL may be disposed on the planarization layer 430 and the common electrode COM may be disposed on a layer higher than the pixel electrode PXL.

A compensation pattern 450 for reducing resistance of the common electrode COM may be disposed on the common electrode COM. Also, the compensation pattern 450 may be disposed in an area overlapping the data line DL.

The pixel electrode PXL may be electrically connected to the thin film transistor TFT through a contact hole CH formed in the planarization layer 430 .

For example, the first pixel electrode PXL1 is electrically connected to the first electrode 310 through the first contact hole CH1, and the second pixel electrode PXL2 is electrically connected to the first electrode 310 through the second contact hole CH2. It may be electrically connected to the second electrode 320 .

As described above, the pixel electrode PXL to which the data voltage according to the image data is applied, the thin film transistor TFT for controlling the application of the data voltage to the pixel electrode PXL, and signal wires are disposed in the sub-pixel SP. It can be.

At this time, in order for the display panel 110 to display a high-resolution image, the number of subpixels (SP) disposed per unit area must be increased, so the size of the subpixels (SP) is reduced. However, since it is difficult to arrange a thin signal line in the subpixel SP due to resistance or the like, a ratio of an area where the pixel electrode PXL forms an electric field in the subpixel SP may be reduced. That is, in the display panel 110 displaying a high-resolution image, the aperture ratio of the sub-pixels SP may decrease.

In the display device 100 according to embodiments of the present invention, the thin film transistor (TFT) controlling the application of the data voltage to the pixel electrode (PXL) disposed in the subpixel (SP) is different according to the subpixel (SP). Through the structure that can be arranged on the layer, the aperture ratio of the sub-pixel (SP) is improved and a high-resolution image can be displayed.

5 illustrates a second example of a planar structure of a subpixel SP in a display device 100 according to embodiments of the present invention.

Referring to FIG. 5 , a subpixel (SP) disposed on the display panel 110 may be defined by an intersection of a gate line (GL) and a data line (DL).

For example, the first subpixel SP1 is defined by the first gate line GL1 and the first data line DL1. Also, the second subpixel SP2 is defined by the second gate line GL2 and the second data line DL2.

Here, the first data line DL1 and the second data line DL2 may be disposed at a boundary between the first subpixel SP1 and the second subpixel SP2. Also, the first data line DL1 and the second data line DL2 may be disposed on different layers. In this case, the first data line DL1 and the second data line DL2 may not overlap each other or at least partially overlap each other.

The first data line DL1 may be electrically connected to the first electrode 510 disposed on the same layer. That is, a structure may be electrically connected through an active layer disposed to overlap a portion of the first data line DL1 and a portion of the first electrode 510 .

Also, the second data line DL2 may be electrically connected to the second electrode 520 disposed on the same layer.

The first electrode 510 is electrically connected to the first pixel electrode PXL1 disposed in the first subpixel SP1 through the first contact hole CH1, and the second electrode 520 is connected to the second contact hole. It may be electrically connected to the second pixel electrode PXL2 disposed in the second subpixel SP2 through (CH2).

Here, a common gate electrode SG may be disposed between a layer on which the first data line DL1 is disposed and a layer on which the second data line DL2 is disposed. The common gate electrode SG is electrically connected to the first gate line GL1 and may be integrally formed with the first gate line GL1.

That is, the common gate electrode SG may be a gate electrode G shared by the thin film transistor TFT driving the first subpixel SP1 and the thin film transistor TFT driving the second subpixel SP2. there is.

For example, the data voltage supplied through the first data line DL1 by the scan signal applied to the common gate electrode SG is applied to the first pixel electrode PXL1 and passed through the second data line DL2. The supplied data voltage may be applied to the second pixel electrode PXL2.

Accordingly, driving of the first subpixel SP1 and the second subpixel SP2 may be controlled through the common gate electrode SG.

In addition, by using this structure to reduce the area where the data line DL is disposed in the subpixel SP, the area where the signal line is disposed in the subpixel SP is reduced, thereby improving the aperture ratio of the subpixel SP. make it possible

FIG. 6 shows an example of a cross-sectional structure of a portion C-C' in the planar structure of the subpixel SP shown in FIG. 5 .

Referring to FIG. 6 , a first data line DL1 and a first electrode 510 are disposed on a first substrate 400, and the first data line DL1 and the first electrode 510 are electrically connected. A first active layer ACT1 is disposed.

A first gate insulating layer 411 is disposed on the first data line DL1 and the first electrode 510 .

A common gate electrode SG is disposed on the first gate insulating layer 411 , and a second gate insulating layer 412 is disposed on the common gate electrode SG.

The second data line DL2 on the second gate insulating layer 412, the second electrode 520, and the second active layer electrically connecting the second data line DL2 and the second electrode 520 ( ACT2) is placed.

A passivation layer 420 and a planarization layer 430 are disposed on the second data line DL2 and the second electrode 520, and a common electrode COM and a pixel insulating layer 440 are formed on the planarization layer 430. and a pixel electrode PXL may be disposed.

Also, the first pixel electrode PXL1 disposed in the first subpixel SP1 is electrically connected to the first electrode 510 disposed under the first gate insulating layer 411 through the first contact hole CH1. connected to

In addition, the second pixel electrode PXL2 disposed on the second subpixel SP2 is electrically connected to the second electrode 520 disposed on the second gate insulating layer 412 through the second contact hole CH2. connected to Here, since the layers on which the first electrode 510 and the second electrode 520 are disposed are different from each other, the depth of the first contact hole CH1 and the depth of the second contact hole CH2 may be different.

That is, the thin film transistor TFT controlling driving of the first subpixel SP1 and the thin film transistor TFT controlling driving of the second subpixel SP2 are disposed on different layers.

In addition, the data voltage supplied to the first data line DL1 is applied to the first pixel electrode PXL1 and the data voltage supplied to the second data line DL2 according to the signal applied to the common gate electrode SG. This may be applied to the second pixel electrode PXL2.

Accordingly, driving of the first subpixel SP1 and the second subpixel SP2 may be controlled through the common gate electrode SG.

In addition, since the thin film transistor TFT controlling driving of the first subpixel SP1 and the thin film transistor TFT controlling driving of the second subpixel SP2 are disposed on different layers, the subpixel SP The area where the data line DL is disposed in can be reduced.

That is, both the first data line DL1 supplying the data voltage to the first subpixel SP1 and the second data line DL2 supplying the data voltage to the second subpixel SP2 are connected to the first subpixel (SP2). By being disposed in the area corresponding to the boundary between SP1 and the second subpixel SP2, reduction in the aperture ratio of the subpixel SP due to the data line DL disposed in the subpixel SP can be prevented.

In this way, by improving the aperture ratio of the sub-pixels (SP) through a structure in which the thin film transistors (TFTs) that control the driving of the adjacent sub-pixels (SP) are disposed on different layers, even in the display panel 110 displaying a high-resolution image. It is possible to improve screen quality by improving the aperture ratio of the subpixel (SP).

And, in the example shown in FIG. 6, the display panel 110 having such a sub-pixel (SP) structure includes a process of depositing source/drain electrodes such as the first data line DL1 and the first electrode 510; , It can be easily implemented by adding only a process of depositing the first gate insulating layer 411 .

7 shows a third example of a subpixel (SP) structure in the display device 100 according to embodiments of the present invention, and an example of a structure in which color filters and black matrices are disposed in each subpixel (SP). is shown.

Referring to FIG. 7 , a first data line DL1 and a second data line DL2 are disposed in an area corresponding to a boundary between the first subpixel SP1 and the second subpixel SP2. Also, the first data line DL1 and the second data line DL2 are disposed on different layers, and between the layer where the first data line DL1 is disposed and the layer where the second data line DL2 is disposed. Driving of the first subpixel SP1 and the second subpixel SP2 is controlled by the disposed common gate electrode SG.

Also, color filters may be disposed on the first subpixel SP1 and the second subpixel SP2. For example, a green color filter may be disposed on the first subpixel SP1 and the second subpixel SP2 ), a blue color filter may be disposed.

In the example of FIG. 7 , the color filter is shown as being disposed on the entire subpixel SP, but the color filter is disposed only in the area where the pixel electrode PXL is disposed, and the color filter is disposed in the area where the thin film transistor TFT is disposed. A filter may not be disposed and only a black matrix may be disposed.

A first black matrix BM1 may be disposed at a boundary between the first subpixel SP1 and the second subpixel SP2.

The first black matrix BM1 may overlap a part of the green color filter disposed in the first subpixel SP1 and a part of the blue color filter disposed in the second subpixel SP2.

In addition, the first black matrix BM1 is formed in an area overlapping the first data line DL1 and the second data line DL2 disposed at the boundary between the first subpixel SP1 and the second subpixel SP2. can be placed.

Also, the first black matrix BM1 may be disposed with a constant width W1 to prevent color mixing between adjacent subpixels SP and to protect the data line DL.

A third subpixel SP3 may be disposed on one side of the first subpixel SP1, and a fourth subpixel SP4 may be disposed on one side of the second subpixel SP2.

Here, since the third subpixel SP3 and the fourth subpixel SP4 also share the gate electrode G of the thin film transistor TFT with the adjacent subpixel SP, the first subpixel ( The data line DL is not disposed at the boundary between SP1 and the third subpixel SP3. Similarly, the data line DL may not be disposed at the boundary between the second subpixel SP2 and the fourth subpixel SP4.

Accordingly, a second black matrix BM2 for preventing color mixing is disposed at the boundary between the first subpixel SP1 and the third subpixel SP3, and the second black matrix BM2 forms a lower portion of the data line DL. Since the black matrix BM1 is not disposed, the width W2 may be narrower than that of the first black matrix BM1.

As described above, the second black matrix BM2 disposed at the boundary between the first subpixel SP1 and the third subpixel SP3 and the boundary between the second subpixel SP2 and the fourth subpixel SP4 As the width decreases, the aperture ratio of the subpixel SP may increase.

FIG. 8 illustrates an example of a cross-sectional structure of a portion D-D' in the planar structure of the subpixel SP shown in FIG. 7 .

Referring to FIG. 8 , a first data line DL1, a first active layer ACT1, and a first electrode 510 are disposed on a first substrate 400, and the first data line DL1 and the first electrode 510 are disposed. A first gate insulating layer 411 is disposed on the electrode 510 .

A common gate electrode SG is disposed on the first gate insulating layer 411 , and a second gate insulating layer 412 is disposed on the common gate electrode SG.

A second data line DL2 , a second active layer ACT2 , and a second electrode 520 are disposed on the second gate insulating layer 412 .

Also, the first electrode 510 is electrically connected to the first pixel electrode PXL1 disposed in the first subpixel SP1 through the first contact hole CH1, and the second electrode 520 is electrically connected to the second pixel electrode PXL1. It is electrically connected to the second pixel electrode PXL2 disposed in the second subpixel SP2 through the contact hole CH2.

Here, a color filter may be disposed on each subpixel SP. For example, a green color filter is disposed on the first pixel electrode PXL1 and a blue color filter is disposed on the second pixel electrode PXL2. can be placed. A second substrate 460 may be disposed on the color filter.

A first black matrix BM1 is disposed at the boundary between the first subpixel SP1 and the second subpixel SP2 to overlap a portion of the color filter, and the first black matrix BM1 is disposed on the first data line DL1. ) and the area where the second data line DL2 is disposed.

Also, a second black matrix BM2 may be disposed at a boundary between a blue color filter and a red color filter disposed in an adjacent subpixel SP. Since the data line DL is not disposed at the lower portion of the second black matrix BM2, the second black matrix BM2 may be disposed with a narrower width than the width of the first black matrix BM1.

That is, in the display device 100 according to embodiments of the present invention, the thin film transistors (TFTs) driving the adjacent subpixels (SP) are disposed on different layers, and the area where the data line (DL) is disposed. , and widths of some black matrices are reduced to improve the aperture ratio of the subpixels SP.

In addition, in the display device 100 displaying a high-resolution image, the effect of improving the aperture ratio of the subpixels SP can be maximized by removing some black matrices through the arrangement structure of the color filters disposed in the subpixels SP.

FIG. 9 shows a fourth example of a planar structure of a subpixel SP in a display device 100 according to embodiments of the present invention, and shows another example of a structure in which color filters and black matrices are disposed.

Referring to FIG. 9 , a first data line DL1 and a second data line DL2 are disposed at the boundary between the first subpixel SP1 and the second subpixel SP2. The first data line DL1 and the second data line DL2 are disposed on different layers. In addition, the first subpixel SP1 and the second subpixel ( The driving of SP2) can be controlled.

Color filters may be disposed in each of the first subpixel SP1 and the second subpixel SP2. For example, a red color filter is disposed in the first subpixel SP1 and the second subpixel SP2. A green color filter may be disposed in

A first black matrix BM1 may be disposed at a boundary between the first subpixel SP1 and the second subpixel SP2.

The first black matrix BM1 may overlap a part of the red color filter disposed in the first subpixel SP1 and a part of the green color filter disposed in the second subpixel SP2, and adjacent subpixels ( SP) to prevent color mixing between them.

Also, the first black matrix BM1 may be disposed to overlap an area where the first data line DL1 and the second data line DL2 are disposed.

A third subpixel SP3 may be disposed adjacent to the first subpixel SP1, and a fourth subpixel SP4 may be disposed adjacent to the second subpixel SP2.

Here, the data line DL supplying the data voltage to the third subpixel SP3 may be disposed on a different layer from the first data line DL1 or may be disposed on the same layer. Also, the data line DL supplying the data voltage to the fourth subpixel SP4 may be disposed on a different layer from the second data line DL2 or may be disposed on the same layer.

That is, the thin film transistors TFTs driving the subpixels SP disposed on both sides of the area where the data line DL is disposed are disposed on different layers, but the amount of the area where the data line DL is not disposed. The thin film transistors TFTs driving the sub-pixels SP disposed on the side may be disposed on different layers or on the same layer.

Color filters may be disposed in each of the third subpixel SP3 and the fourth subpixel SP4. For example, a red color filter may be disposed in the third subpixel SP3, and the fourth subpixel SP4 A green color filter may be disposed in

That is, a color filter representing the same color (red) as the color filter disposed in the first subpixel SP1 may be disposed in the third subpixel SP3, and a color filter representing the same color (red) as the color filter disposed in the first subpixel SP1 may be disposed in the fourth subpixel SP4. A color filter exhibiting the same color (green) as the color filter disposed in (SP2) may be disposed.

Also, the red color filter disposed on the first subpixel SP1 and the red color filter disposed on the third subpixel SP3 may be integrally disposed.

In this way, the black matrix may not be disposed at the boundary of the subpixel SP by disposing the color filters representing the same color in the subpixel SP disposed on both sides of the region where the data line DL is not disposed. there is.

Therefore, the aperture ratio of the subpixel SP can be further improved by partially removing the black matrix, and as color filters representing the same color are disposed in adjacent subpixels SP, color mixture that can be recognized according to the viewing angle occurs. you can avoid doing that.

That is, embodiments of the present invention enable the improvement of the aperture ratio by reducing the wiring area through a structure in which the thin film transistor (TFT) and the data line (DL) driving the adjacent subpixel (SP) are disposed on different layers, Through a structure in which the black matrix is disposed only in the region overlapping with the region where the data line DL is disposed, it is possible to maximize the aperture ratio by removing a part of the black matrix.

FIG. 10 illustrates an example of a cross-sectional structure of a portion E-E' in the planar structure of the subpixel SP shown in FIG. 9 .

Referring to FIG. 10 , a first data line DL1, a first electrode 510, and a first active layer ACT1 are disposed on a first substrate 400, and the first data line DL1 and the first active layer ACT1 are disposed. A first gate insulating layer 411 is disposed on the electrode 510 .

A common gate electrode SG is disposed on the first gate insulating layer 411 , and a second gate insulating layer 412 is disposed on the common gate electrode SG.

A second data line DL2 , a second electrode 520 , and a second active layer ACT2 are disposed on the second gate insulating layer 412 .

Also, the first pixel electrode PXL1 of the first subpixel SP1 is electrically connected to the first electrode 510 through the first contact hole CH1 and the second pixel of the second subpixel SP2. The electrode PXL2 is electrically connected to the second electrode 520 through the second contact hole CH2.

Here, a red color filter may be disposed on the first subpixel SP1 and a green color filter may be disposed on the second subpixel SP2.

Such a color filter may be disposed in a structure extending to adjacent subpixels SP.

That is, a structure in which a red color filter is extended to a subpixel SP adjacent to the first subpixel SP1 and a structure in which a green color filter is extended to a subpixel SP adjacent to the second subpixel SP2 can be placed as

Accordingly, the first black color is applied only to an area corresponding to the boundary between the first subpixel SP1 and the second subpixel SP2 and overlapping the area where the first data line DL1 and the second data line DL2 are disposed. A matrix BM1 may be disposed.

Also, a black matrix may not be disposed at a boundary between adjacent subpixels SPs on which color filters representing the same color are disposed.

For example, as shown in part I shown in FIG. 10 , since the green color filter is disposed on the second sub-pixel SP2 and the sub-pixel SP adjacent to the second sub-pixel SP2 in an extended structure, A black matrix may not be disposed at a boundary between pixels SP.

In this way, the aperture ratio of the subpixels SP can be further improved by removing a part of the black matrix disposed on the boundary between the subpixels SP.

In addition, by disposing a color filter representing the same color between adjacent subpixels (SP), a phenomenon in which color mixture between adjacent subpixels (SP) is prevented and displayed in the display panel 110 showing a high-resolution image of the subpixel (SP) to maximize the aperture ratio.

Meanwhile, according to the stacked structure of the subpixels SP, the stacked structure of an area not displaying an image of the display panel 110 may also be changed.

FIG. 11 illustrates an example of a cross-sectional structure of a non-active area N/A changed according to a stacked structure of subpixels SP in the display device 100 according to embodiments of the present invention.

Referring to FIG. 11 , the display panel 110 according to embodiments of the present invention includes an active area A/A in which subpixels SP are disposed and displaying an image, and an active area A/A. It corresponds to an external area and may include a non-active area (N/A) in which a signal wire or a driving circuit is disposed.

Here, referring to the example of the cross-sectional structure of the J-J′ portion in the non-active area N/A of the display panel 110 , the first gate insulating layer 411 is disposed on the first substrate 400 . Then, the gate metal 1100 is disposed on the first gate insulating layer 411 , and the second gate insulating layer 412 is disposed on the gate metal 1100 .

A semiconductor material 1110 and a source/drain metal 1120 are disposed on the second gate insulating layer 412, and a protective layer 420, a planarization layer 430, and the like are disposed on the source/drain metal 1120. It can be.

A pixel insulating layer 440 and a pixel metal 1130 may be disposed on the planarization layer 430 .

Here, the gate metal 1100 may be the same material disposed on the same layer as the common gate electrode SG in the subpixel SP. In addition, the semiconductor material 1110 may be the same as the active layer in the subpixel SP, and the source/drain metal 1120 may be the same material as the source electrode and the drain electrode in the subpixel SP. The pixel metal 1130 may be made of the same material as the pixel electrode PXL.

In addition, the gate metal 1100 , the source/drain metal 1120 , the pixel metal 1130 , and the like may constitute signal wires disposed in the non-active area N/A of the display panel 110 . For example, it may be a wire to which a control signal such as a gate high voltage, a gate low voltage, or a clock signal applied to a gate driving circuit disposed in the non-active region N/A is applied.

That is, the signal wiring may be formed in the non-active area N/A by using the same material as the material constituting the signal wiring or electrode in the subpixel SP.

In addition, since only the first gate insulating layer 411 is additionally disposed below the gate metal 1100 according to the stack structure of the subpixel SP, even if the stack structure of the subpixel SP is changed, the non-active region N /A) to minimize structural changes and implement signal wiring.

In the embodiments of the present invention, the materials constituting the source electrode and the drain electrode of the thin film transistor (TFT) for driving the adjacent subpixel (SP) are disposed on different layers, so that the subpixel ( SP) to improve the aperture ratio.

In addition, in the display panel 110 displaying a high-resolution image, color filters representing the same color are disposed in the subpixels SP positioned on both sides of an area where the data line DL is not disposed, thereby increasing the number of subpixels SP. It is possible to prevent a phenomenon in which color mixture is recognized according to the viewing angle at the boundary.

In addition, the effect of improving the aperture ratio of the subpixels SP can be maximized by partially removing the black matrix disposed on the boundary between the subpixels SP.

The above description is merely an example of the technical idea of the present invention, and various modifications and variations can be made to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, so the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device 110: display panel
120: gate driving circuit 130: data driving circuit
140: controller 310, 510: first electrode
320, 520: second electrode 400: first substrate
410: gate insulating layer 411: first gate insulating layer
412: second gate insulating layer 420: protective layer
430: planarization layer 440: pixel insulating layer
450: compensation pattern 460: second substrate
1100: gate metal 1110: semiconductor material
1120: source/drain metal 1130: pixel metal

Claims (16)

In a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are disposed,
a first data line;
a first electrode electrically connected to the first data line;
a first active layer electrically connecting the first data line and the first electrode;
a first insulating layer disposed on the first data line and the first electrode;
a gate electrode disposed on the first insulating layer;
a second insulating layer disposed on the gate electrode;
a second data line disposed on the second insulating layer;
a second electrode disposed on the second insulating layer and electrically connected to the second data line;
a second active layer electrically connecting the second data line and the second electrode;
a planarization layer disposed on the second data line and the second electrode;
a first pixel electrode disposed in a first subpixel on the planarization layer and electrically connected to the first electrode through a first contact hole;
a second pixel electrode disposed in a second subpixel on the planarization layer and electrically connected to the second electrode through a second contact hole;
a first color filter disposed in the first subpixel and positioned on the first pixel electrode;
a second color filter disposed in the second subpixel, positioned on the second pixel electrode, and displaying a color different from that of the first color filter; and
A first black matrix disposed at a boundary between the first subpixel and the second subpixel and positioned to overlap an area where the first data line and the second data line are disposed.
A display panel comprising a.
delete delete According to claim 1,
a third pixel electrode disposed in a third subpixel located on one side of the first subpixel; and
The display panel further comprises a third color filter disposed in the third sub-pixel and positioned on the third pixel electrode.
According to claim 4,
The third color filter displays the same color as the first color filter.
According to claim 5,
The first color filter and the third color filter are integrally disposed on the display panel.
According to claim 4,
The third pixel electrode,
A display panel electrically connected to a third electrode disposed on the same layer as the first electrode or the same layer as the second electrode through a third contact hole.
According to claim 4,
and a second black matrix disposed at a boundary between the first subpixel and the third subpixel and having a width narrower than that of the first black matrix.
According to claim 4,
a fourth pixel electrode disposed in a fourth subpixel positioned on one side of the second subpixel; and
The display panel further comprises a fourth color filter disposed in the fourth sub-pixel and positioned on the fourth pixel electrode.
According to claim 9,
The fourth color filter exhibits the same color as the second color filter, and the second color filter and the fourth color filter are integrally disposed.
According to claim 1,
The display panel of claim 1 , wherein a depth of the first contact hole and a depth of the second contact hole are different.
a display panel on which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are disposed, and includes an active area and a non-active area;
a gate driving circuit for driving the plurality of gate lines; and
A data driving circuit for driving the plurality of data lines;
The active area of the display panel,
a first data line;
a first electrode electrically connected to the first data line;
a first active layer electrically connecting the first data line and the first electrode;
a first insulating layer disposed on the first data line and the first electrode;
a gate electrode disposed on the first insulating layer;
a second insulating layer disposed on the gate electrode;
a second data line disposed on the second insulating layer;
a second electrode disposed on the second insulating layer and electrically connected to the second data line;
a second active layer electrically connecting the second data line and the second electrode;
a planarization layer disposed on the second data line and the second electrode;
a first pixel electrode disposed in a first subpixel on the planarization layer and electrically connected to the first electrode through a first contact hole; and
a second pixel electrode disposed in a second subpixel on the planarization layer and electrically connected to the second electrode through a second contact hole;
The non-active area of the display panel,
Including the first insulating layer and the second insulating layer,
A display device comprising one or more signal wires positioned between the first insulating layer and the second insulating layer and made of the same material as the gate electrode.
delete According to claim 12,
The active area of the display panel,
a plurality of black matrices arranged for each subpixel among the plurality of subpixels and positioned at a boundary between subpixels;
and a color filter disposed in two subpixels between two black matrices among the plurality of black matrices, exhibiting the same color, and integrally formed.
According to claim 12,
The active area of the display panel,
a plurality of black matrices arranged for each subpixel among the plurality of subpixels and positioned at a boundary between subpixels;
Two adjacent black matrices among the plurality of black matrices have different widths.
delete

Images