KR20190028057A - Organic Light Emitting Display Device And Method Of Driving The Same - Google Patents

Abstract

According to the present invention, gate electrodes of sensing transistors of first to fourth sub-pixels included in each pixel are connected to one sensing line and a drain electrode is connected to the same reference line. Accordingly, since current of driving transistors of the first to fourth sub-pixels included in each pixel may be sensed through the same reference voltage line and the number of sensing lines may be reduced, an aperture ratio of each pixel may be increased.

Description

[0001] The present invention relates to an organic light emitting display device and a method of driving the same,

The present invention relates to an organic light emitting diode (OLED) display device, and more particularly, to an OLED display device capable of reducing the number of source drive ICs and reducing the number of sensing lines and a driving method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, in recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

Of these, the organic light emitting display device can be driven at a low voltage, is thin, has excellent viewing angle, and has a high response speed.

The organic light emitting display includes a display panel having a plurality of data lines, a plurality of gate lines, a plurality of data lines and a plurality of pixels formed at intersections of the plurality of gate lines, a gate for supplying gate signals to the plurality of gate lines, And a data driver for supplying a data voltage to the plurality of data lines.

 Each of the plurality of pixels includes an organic light emitting diode, a driving transistor for controlling the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, And supplies the data voltage of the data signal to the gate electrode of the driving transistor.

The threshold voltage of the driving transistor may be different for each pixel due to a process variation at the time of manufacturing the OLED display device or a shift of the threshold voltage of the driving transistor due to long-term driving.

Therefore, when the same data voltage is applied to each pixel, the current Ids of the driving transistor supplied to the organic light emitting diode should be the same. However, even if the same data voltage is applied to each pixel, Due to the difference in electron mobility, the current Ids of the driving transistor supplied to the organic light emitting diode is different for each pixel.

As a result, even if the same data voltage is applied to each pixel, there arises a problem that the luminance at which the organic light emitting diode emits varies from pixel to pixel.

To solve this problem, a compensation method for compensating the threshold voltage of the driving transistor has been proposed.

The compensation method is divided into an internal compensation method and an external compensation method.

The internal compensation method is a method of sensing and compensating the threshold voltage of the driving transistor inside the pixel.

The external compensation method supplies a predetermined data voltage to the pixel, senses the current Ids of the driving transistor of the pixel through a sensing line according to a preset data voltage, converts the current into a digital data, And compensates digital video data to be supplied to the pixels.

The external compensation method requires a sensing data output unit that senses the current Ids of the driving transistor of the pixel through the sensing line and converts it into digital data sensing data.

The sensing data output unit is embedded in the source driver IC of the data driver, so that in the external compensation method, the source driver ICs are connected to the sensing lines as well as the data lines.

As a result, the number of source driver ICs increases, resulting in an increase in the manufacturing cost of the organic light emitting display device and a problem of lowering the aperture ratio by the sensing line.

The present invention has an object to provide an organic light emitting display device capable of reducing the manufacturing cost and increasing the aperture ratio of a sub-pixel.

According to an aspect of the present invention, there is provided a liquid crystal display device including first and second data lines, first and second gate lines crossing the first and second data lines, A first gate line, a first gate line, and a second gate line, the first gate line, the first gate line, and the first and second gate lines, Pixel, the switching transistor of the first sub-pixel is connected to the first gate line, the first data line, and the sensing transistor of the first sub-pixel is connected to the first sensing line, Pixel, the switching transistor of the second sub-pixel is connected to the second gate line, the first data line, and the sensing transistor of the second sub-pixel is connected to the first sensing line, Pixel, the switching transistor of the third sub-pixel is connected to the first gate line, the second data line, and the sensing transistor of the third sub-pixel is connected to the first sensing line, Pixel, the switching transistor of the fourth sub-pixel is connected to the second gate line, the second data line, and the sensing transistor of the fourth sub-pixel is connected to the first sensing line, And an organic electroluminescent display device.

Each of the first to fourth sub-pixels is turned on by an organic light emitting diode and a gate signal of either the first gate line or the second gate line, The switching transistor supplying a data voltage of either one of the data line and the second data line; and a switching transistor having a gate electrode connected to the drain electrode of the switching thin film transistor, a drain electrode connected to the driving voltage wiring, A driving transistor connected to the organic light emitting diode and configured to adjust an amount of current flowing to the organic light emitting diode according to a voltage difference between a gate voltage and a source voltage; a gate electrode connected to the first sensing line; A source electrode connected to a source electrode of the driving transistor, And the sensing transistor may be turned on by a sensing signal of the first sensing line to connect the source electrode of the driving transistor to the first reference line.

Each of the first to fourth sub-pixels may further include a storage capacitor connected to a gate electrode and a source electrode of the driving transistor.

The first through fourth sub-pixels may be red, white, blue, and green sub-pixels.

In addition, the one frame period includes an active period and a blank period, the blank period includes first and second periods, sequentially supplies gate signals to the first and second gate lines during the active period, Simultaneously supplying gate signals to each of the first and second gate lines during a first period (T1) of the blank period and supplying one of the first and second gate lines during the second period (T2) of the blank period And a gate signal output unit for supplying a gate signal to the gate electrode.

And a sensing signal output unit for supplying a sensing signal to each of the first to fourth sub-pixels connected to the first sensing line during the first and second periods of the blank period.

Here, during the active period, the corresponding data signal is output to each of the first and second data lines, and in either of the first and second data lines during the first and second periods of the blank period, And a data driver for alternately outputting the black data signal and the sensing data signal to the other one of the first and second data lines.

According to another aspect of the present invention, there is provided a liquid crystal display device including first and second data lines, first and second gate lines crossing the first and second data lines, and first and second gate lines arranged in parallel with the first and second gate lines. Pixels, a first reference line intersecting the first and second gate lines, and first through fourth sub-pixels corresponding to the first and second gate lines and the first and second data lines, A method of driving an organic light emitting display, the method comprising: sequentially supplying gate signals to the first and second gate lines during an active period of one frame; supplying data signals to the first and second data lines; Simultaneously supplying gate signals to each of said first and second gate lines during a first period (T1) of a blank period of one frame, and supplying said gate signals to said first and second gate lines simultaneously during a second period (T2) 2 gate line And supplying a sensing signal to each of the first to fourth sub-pixels connected to the first sensing line during the first and second periods to sense the first to fourth sub-pixels simultaneously And a driving method of the organic light emitting display device.

Here, the step of simultaneously sensing the first to fourth sub-pixels by supplying a sensing signal to each of the first to fourth sub-pixels connected to the first sensing line during the first and second periods may include: And outputting a black data signal predefined as a data voltage for sensing in one of the first and second data lines during a second period, and outputting the black data signal and the sensing data to the other of the first and second data lines, And alternately outputting the data signal.

The switching transistor of the first sub-pixel is connected to the first gate line, the first data line, the sensing transistor of the first sub-pixel is connected to the first sensing line, the first reference line, Pixel, the switching transistor of the second sub-pixel is connected to the second gate line, the first data line, the sensing transistor of the second sub-pixel is connected to the first sensing line, the first reference line, Pixels are connected to the first gate line, the second data line, the sensing transistor of the third sub-pixel is connected to the first sensing line, the first reference line, and the fourth sub- Pixel is connected to the second gate line, the second data line, and the sensing transistor of the fourth sub- Line, the first may be connected to the first reference line.

Each of the first to fourth sub-pixels is turned on by an organic light emitting diode and a gate signal of either the first gate line or the second gate line, The switching transistor supplying a data voltage of either one of the data line and the second data line; and a switching transistor having a gate electrode connected to the drain electrode of the switching thin film transistor, a drain electrode connected to the driving voltage wiring, A driving transistor connected to the organic light emitting diode and configured to adjust an amount of current flowing to the organic light emitting diode according to a voltage difference between a gate voltage and a source voltage; a gate electrode connected to the first sensing line; A source electrode connected to a source electrode of the driving transistor, And the sensing transistor may be turned on by a sensing signal of the first sensing line to connect the source electrode of the driving transistor to the first reference line.

Each of the first to fourth sub-pixels may further include a storage capacitor connected to a gate electrode and a source electrode of the driving transistor.

In the present invention, it is possible to reduce the number of data lines by half to reduce the manufacturing cost, and to sense the current of the driving transistor of the sub-pixels through one sensing line, thereby improving the aperture ratio of the sub-pixels.

1 is a block diagram schematically showing an organic light emitting display according to an embodiment of the present invention.
2 is a block diagram schematically showing a source drive IC included in the data driver.
3 is a schematic view illustrating a pixel of an OLED display according to an embodiment of the present invention.
Fig. 4 is a schematic diagram showing the circuit diagram of Fig. 3. Fig.
5 is a timing chart schematically showing sensing driving of an organic light emitting device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram schematically showing an organic light emitting display according to an embodiment of the present invention, and FIG. 2 is a block diagram schematically showing a source drive IC included in a data driver.

 1, an OLED display 100 according to an exemplary embodiment of the present invention includes a display panel 10, a data driver 20, a gate driver 40, a timing controller 60, A reference voltage supply unit 70, and a reference voltage supply unit 30.

The display panel 10 includes a display area AA and a non-display area NA provided in the periphery of the display area AA.

The display area AA is an area where a plurality of pixels are formed to display an image, and the non-display area NA means an area other than the display area.

 The display panel 10 may include a plurality of data lines DL1 to DLm, a plurality of reference lines RL1 to RLp, a plurality of gate lines GL1 to GLn, and a plurality of sensing lines SL1 to SLq have.

 Here, the plurality of data lines DL1 to DLm and the plurality of reference lines RL1 to RLp may intersect the plurality of gate lines GL1 to GLn and the sensing lines SL1 to SLq.

 The plurality of data lines DL1 to DLm and the reference lines RL1 to RLp may be parallel to each other and the plurality of gate lines GL1 to GLn and the sensing lines SL1 to SLq may be parallel to each other.

Each pixel of the OLED display 100 according to the embodiment of the present invention includes two data lines among the data lines DL1 to DLm, one of the plurality of reference voltage lines RL1 to RLp, Two gate lines among the plurality of gate lines GL1 to GLn, and one sensing line among the plurality of sensing lines SL1 to SLp.

Here, each pixel of the display panel 10 may include a plurality of sub pixels.

Each of the plurality of sub-pixels may include an organic light emitting diode (OLED) and a plurality of transistors for supplying current to the organic light emitting diode (OLED).

The pixels in the display area and the sub-pixels constituting the pixel will be described in more detail later.

On the other hand, the data driver 20 may include a plurality of source drive ICs 21.

2, the source drive IC 21 may include a data voltage supply unit 21A, a sensing data output unit 21B, a first switching unit 21C, and a second switching unit 21D.

The data voltage supply unit 21A may be connected to a plurality of data lines DL1 to DLm to supply data voltages (or data signals).

The data voltage supplier 21A can receive the compensation data CDATA or the sensing data SDATA and the data timing control signal DCS from the timing controller 60.

The data voltage supplier 21A supplies the data voltage (or data signal) for emitting the compensation data CDATA to the organic light emitting diode OLED of the pixel at a predetermined luminance in accordance with the data timing control signal DCS in the display mode, And supplies the data to the plurality of data lines DL1 to DLm.

For example, when the compensation data CDATA supplied to the data driver 20 is 8 bits, the data voltage may be supplied in any one of 256 voltages.

The data voltage supplier 21A converts the sensing data SDATA to sensing data voltages (or sensing data signals) in accordance with the data timing control signal DCS in the sensing mode and supplies them to the data lines DL1 to DLm Can supply.

Here, the sensing data voltage is a voltage for sensing the current of the driving transistor of the pixel.

The first switching unit 21C is disposed between the plurality of reference lines RL1 to RLp and the reference voltage supply unit 30 and is connected between the reference lines RL1 to RLp and the reference voltage supply unit 30. [ Lt; / RTI >

The first switching unit 21C may include a plurality of first switches SW1 that are turned on and off by a first switch control signal input from the timing controller 60. [

 Here, when the first switch SW1 of the first switching unit 21C is turned on by the first switch control signal, the plurality of reference lines RL1 to RLp are connected to the reference voltage supply unit 30, The reference voltage of the reference voltage supply unit 30 may be supplied to the plurality of reference lines RL1 to RLp.

The second switching unit 21D is connected between the plurality of reference lines RL1 to RLp and the sensing data output unit 21B and is connected between the plurality of reference lines RL1 to RLp and the sensing data output unit 21B Can be switched.

The second switching unit 21D may include a plurality of second switches SW2 that are turned on and off by a second switch control signal input from the timing controller 60. [

When the second switch SW2 of the second switching unit 21D is turned on by the second switch control signal, the plurality of reference lines RL1 to RLp are connected to the sensing data output unit 21B, The current flowing in each of the reference lines RL1 to RLp of the sensing circuit 21 can be sensed by the sensing data output section 21B.

That is, the sensing data output section 21B can convert a current flowing in each of the plurality of reference lines RL1 to RLp into a voltage, and convert the converted voltage into digital data sensing data SD.

To this end, the sensing data output section 21B includes a current-to-voltage conversion section for converting the current flowing in each of the plurality of reference lines RL1 to RLp into a voltage and an output voltage of the current- To an analog digital converter (ADC).

The sensing data output section 21B can output the sensing data SD to the data compensating section 70. [

The gate driver 40 may include a gate signal output unit 41 and a sensing signal output unit 42.

Here, the gate signal output unit 41 may be connected to a plurality of gate lines GL1 to GLn to supply a gate signal.

That is, the gate signal output unit 41 can supply the gate signals to the plurality of gate lines GL1 to GLn, respectively, in accordance with the gate timing control signal SCS input from the timing control unit 60. [

The supply of the gate signal of the gate signal output unit 41 will be described later in more detail.

The sensing signal output unit 42 may be connected to a plurality of sensing lines SL1 to SLq to supply a sensing signal.

That is, the sensing signal output unit 42 can supply the sensing signals to the plurality of sensing lines SL1 to SLq according to the sensing timing control signal SENCS input from the timing controller 60. [

The supply of the sensing signal of the sensing signal output unit 42 will be described later in more detail.

Each of the gate signal output unit 41 and the sensing signal output unit 42 may include a plurality of transistors and may be formed directly in the non-display area NDA of the display panel 10 using a GIP (Gate Driver InPanel) method.

Each of the gate signal output unit 41 and the sensing signal output unit 42 may be mounted on a flexible film (not shown) formed in the form of a driving chip and connected to the display panel 10.

The timing controller 60 can receive the compensation data CDATA or the sensing data SDATA and the timing signal from the data compensator 70.

Here, the timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing control unit 60 can generate a timing control signal for controlling the operation timings of the date drive unit 20, the gate signal output unit 41, and the sensing signal output unit 42. [

For example, the timing control signals include a data timing control signal DCS for controlling the operation timing of the data driver 20, a gate timing control signal SCS for controlling the operation timing of the gate signal output section 41, And a sensing timing control signal (SENCS) for controlling the operation timing of the sensing signal output section (42).

The timing controller 60 may output the compensation data CDATA or the sensing data SDATA and the data timing control signal DCS to the data driver 20.

The timing control unit 60 may output the gate timing control signal SCS to the gate signal output unit 41. [

The timing control unit 60 can output the sensing timing control signal SENCS to the sensing signal output unit 42. [

The timing controller 60 includes first and second switching controls SW1 and SW2 for controlling the first and second switches SW1 and SW2 of the first and second switching units 21C and 21D of the data driver 20, Signals.

Here, the timing controller 60 divides one frame period into an active period and a blank period, displays an image on the pixels of the display panel 10 during the active period, and controls the current of the driving transistor of the pixel during the blank period can do.

The operation of the pixels P during the active period and the blank period of one frame period will be described in more detail later.

Meanwhile, the data compensator 70 can receive the sensing data SD from the data driver 20.

The data compensator 70 may generate the compensation data CDATA to compensate the digital video data DATA by calculating the sensing data SD.

Here, the data compensator 70 may include a memory in the form of a look-up table storing the compensation data CDATA.

That is, the data compensator 70 may apply compensation data to the digital video data DATA from outside to generate compensation data CDATA, and output the compensation data CDATA to the timing controller 60.

Here, the data compensating unit 70 may be embedded in the timing control unit 60.

More specifically, the sensing data SD is data obtained by sensing the current flowing through the driving transistor when the sensing data voltage is supplied to the gate electrodes of the driving transistors of the plurality of pixels.

That is, the sensing data SD may be digital data of the source voltage of the driving transistor in which the threshold voltage of the driving transistor is reflected.

The compensation data CDATA generated by applying the correction data to the digital video data DATA may be data in which the threshold voltage of the driving transistor DT is compensated.

 Therefore, in the embodiment of the present invention, the correction data is generated by calculating the sensing data SD, and the compensation data CDATA is generated by applying the correction data to the digital video data DATA, Thereby allowing external compensation of the threshold voltage.

The reference voltage supply unit 30 may generate a reference voltage and supply the generated reference voltage to the source drive ICs 21 of the data driver 20.

Here, the timing control unit 60, the data compensation unit 70, and the reference voltage supply unit 30 may be mounted on the control circuit board.

 Here, the control circuit board may be connected to the source circuit board by a flexible cable, and the control circuit board may be a printed circuit board.

3 is a schematic view illustrating a pixel of an OLED display according to an embodiment of the present invention.

A first pixel P1 including first through fourth sub-pixels SP1, SP2, SP3, and SP4 arranged in a gate line (X-axis direction) The second pixel P2 including the fifth through eighth sub-pixels SP5, SP6, SP7, and SP8 arranged in the vertical direction (the vertical direction) is arranged in the data line (Y-axis direction) But is not limited thereto.

The first and fifth sub-pixels SP1 and SP5 are sub-pixels R for emitting red light and the second and sixth sub-pixels SP2 and SP6 are sub-pixels W for emitting white light. The third and seventh sub-pixels SP3 and SP7 are sub-pixels B for emitting blue light and the fourth and eighth sub-pixels SP4 and SP8 are sub-pixels G for emitting green light. But this is merely an example, and the present invention is not limited thereto.

The first to eight sub-pixels SP1, SP2, SP3, SP4, SP5, SP6, SP7 and SP8 constituting the first and second pixels P1 and P2 include a plurality of gate lines GL1 to GL4, May be disposed in regions formed by the intersection of the lines SL1 and SL2 and the plurality of data lines DL1 and DL2.

That is, one data line may be disposed between adjacent sub-pixels in the gate line direction (X-axis direction).

Because of this, the four sub-pixels are connected by the two data lines DL1 and DL2, so that each of the pixels P1 and P2 can be connected by two data lines DL1 and DL2.

Specifically, two sub-pixels adjacent to each other may be connected to one data line, and the other two sub-pixels adjacent to each other may be connected to another data line.

The first pixel P1 and the second pixel P2 have the same structure and will be described with reference to the first pixel P1.

For example, the first and second sub-pixels SP1 and SP2 of the first pixel P1 are connected to the first data line DL1, and the third and fourth sub-pixels SP3 and SP4 are connected to the second And may be connected to the data line DL2.

In addition, a plurality of gate lines GL1 and GL2 may be disposed in the first pixel P1.

That is, the first pixel P1 may be connected to the two gate lines GL1 and GL2. Specifically, two sub-pixels of the first pixel P1 may be connected to one gate line, and the other two sub-pixels may be connected to the other gate line.

At this time, two adjacent sub-pixels may be connected to different gate lines, and two adjacent sub-pixels may be connected to different gate lines.

For example, the first and third sub-pixels SP1 and SP3 may be coupled to the first gate line GL1 and the second and fourth sub-pixels SP2 and SP4 may be coupled to the second gate line GL2. Can be connected.

That is, the first pixel P1 is connected to the two data lines DL1 and DL2 and the two gate lines GL1 and GL2 so that when the gate signal is supplied to the first gate line GL1, The data voltage of the first data line DL1 is supplied to the pixel SP1 and the data voltage of the second data line DL2 is supplied to the third sub pixel SP3.

When the gate signal is supplied to the second gate line GL2, the data voltage of the first data line DL1 is supplied to the second sub-pixel SP2 and the data voltage of the second data line DL1 is supplied to the fourth sub- It is possible to supply the data voltage of the line DL2.

That is, in the embodiment of the present invention, the organic light emitting display (100 of FIG. 1) includes first through fourth sub-pixels SP1 and DL2 using two gate lines GL1 and GL2 and two data lines DL1 and DL2. , SP2, SP3, and SP4).

Accordingly, the number of data lines can be reduced to half compared with the case where data voltages are supplied to the first to fourth sub-pixels using one gate line and four data lines in the related art, thereby reducing the number of source drive ICs The manufacturing cost can be reduced.

One sensing line SL1 is disposed in each of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 and the first to fourth sub-pixels SP1, SP2, SP3 and SP4 are connected to one sensing line SL1 SL1.

In addition, a reference line RL1 may be disposed between the second sub-pixel SP2 and the third sub-pixel SP3.

Accordingly, the first to fourth sub-pixels SP1, SP2, SP3 and SP4 of the first pixel P1 can be connected to one reference line RL1.

That is, the first to fourth sub-pixels SP1, SP2, SP3 and SP4 are connected to one sensing line SL1 and connected to one reference line RL1.

Therefore, when the sensing signal is supplied to one sensing line SL1, the first to fourth sub-pixels SP1, SP2, SP3, SP4 can be sensed through one reference voltage line RL1.

Therefore, since the number of sensing lines can be reduced, the aperture ratio of each pixel can be increased.

Fig. 4 is a schematic diagram showing the circuit diagram of Fig. 3. Fig. 3 will be described together.

The first through eighth sub-pixels SP1, SP2, SP3, SP4, SP5, SP6, SP7, and SP8 included in the first and second pixels P1 and P2 may emit organic light And may include a diode OLED, a driving transistor Tdr, a switching transistor Tsw, a sensing transistor Tse, and a storage capacitor Cst.

The first pixel P1 and the second pixel P2 have the same structure and will be described with reference to the first pixel P1.

Here, the organic light emitting diode OLED can emit light according to the current supplied through the driving transistor Tdr.

The anode electrode of the organic light emitting diode OLED is connected to the first electrode of the driving transistor Tdr and the cathode electrode of the organic light emitting diode OLED is connected to the second power source VSS, Line. ≪ / RTI >

The organic light emitting diode OLED includes an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. can do.

Here, when a voltage is applied to the anode electrode and the cathode electrode, the organic light emitting diode OLED moves the holes and electrons to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively.

The first sub-pixel SP1 may include a red organic light emitting diode OLED that emits red light and the second sub-pixel SP2 may include a white organic light emitting diode OLED that emits white light. And the third sub pixel SP3 may include a blue organic light emitting diode OLED for emitting blue light and the fourth sub pixel GP may include a green organic light emitting diode OLED for emitting green light But is not limited thereto.

In addition, each of the first to fourth sub-pixels SP1, SP2, SP3, and SP4 may include a white organic light emitting diode. In this case, the first sub-pixel SP1 includes a red color filter, the third sub-pixel SP3 includes a blue color filter, and the fourth sub-pixel SP4 includes a green color filter.

The driving transistor Tdr is disposed between the first power supply line (not shown) and the organic light emitting diode OLED.

The driving transistor Tdr adjusts the current flowing from the first power supply line to the organic light emitting diode OLED in accordance with the voltage difference between the gate electrode and the source electrode.

The gate electrode of the driving transistor Tdr is connected to the drain electrode of the switching transistor Tsw and the source electrode of the driving transistor Tdr is connected to the anode electrode of the organic light emitting diode OLED. May be connected to the first power supply line to which the first power supply voltage VDD is supplied.

On the other hand, the switching transistor Tsw is turned on by the gate signals of the gate lines GL1 and GL2 to supply the voltage of the data lines DL1 and DL2 to the gate electrode of the driving transistor Tdr.

Here, the gate electrode of the switching transistor Tsw is connected to the gate lines GL1 and GL2, the drain electrode of the switching transistor Tsw is connected to the gate electrode of the driving transistor Tdr, and the source of the switching transistor Tsw The electrodes may be connected to the data lines DL1 and DL2.

 On the other hand, the sensing transistor Tse is turned on by the sensing signal of the sensing line SL1 to connect the reference line RL1 to the first electrode of the driving transistor Tdr.

Here, the gate electrode of the sensing transistor Tse is connected to the sensing line SL1, the drain electrode of the sensing transistor Tse is connected to the reference line RL1, and the source electrode of the sensing transistor Tse is connected to the driving transistor Tdr, respectively.

On the other hand, the storage capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor Tdr.

Here, the storage capacitor Cst stores the difference voltage between the gate voltage of the driving transistor Tdr and the source voltage.

The driving transistor Tdr, the switching transistor Tsw, and the sensing transistor Tse are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but the present invention is not limited thereto.

That is, the driving transistor Tdr, the switching transistor Tsw, and the sensing transistor Tse may be formed of a P-type MOSFET.

Hereinafter, the operation in the display period and the sensing period of the first to fourth sub-pixels SP1, SP2, SP3, and SP4 of the first pixel P1 will be described.

The data voltage (or data signal) of the data lines DL1 and DL2 is supplied to the gate electrode of the driving transistor Tdr when the gate signal is supplied to the gate lines GL1 and GL2 in the display period, ), A reference voltage of the reference line RL1 is supplied to the source electrode of the driving transistor Tdr.

The current of the driving transistor Tdr flowing in accordance with the voltage difference between the voltage of the gate electrode of the driving transistor Tdr and the voltage of the source electrode in the display period is supplied to the organic light emitting diode OLED, ) Emit light.

 At this time, since the data voltage is the voltage compensated for the threshold voltage of the driving transistor Tdr, the current of the driving transistor Tdr does not depend on the threshold voltage of the driving transistor Tdr.

When a gate signal is supplied to the gate lines GL1 and GL2 in the sensing period, the sensing data voltage (or sensing data signal) of the data lines DL1 and DL2 is supplied to the gate electrode of the driving transistor Tdr, The reference voltage of the reference line RL1 is supplied to the source electrode of the driving transistor Tdr when the sensing signal is supplied to the line SL1.

 In the sensing period, the sensing transistor SL1 is turned on by the sensing signal on the sensing line SL1 to turn on the driving transistor Tdr flowing in accordance with the voltage difference between the voltage of the gate electrode of the driving transistor Tdr and the voltage of the source electrode. ) Flows to the reference line RL1.

 As a result, the sensing data output unit 21B of FIG. 2 can sense the current flowing in the reference line RL1 according to the switching of the second switching unit 21D of FIG. 2 to output the sensing data SD, The data compensating unit 70 in FIG. 1 can externally compensate the threshold voltage of the driving transistor Tdr using the sensing data SD.

Here, the gate electrode of the switching transistor Tsw of the two sub-pixels among the first to fourth sub-pixels SP1, SP2, SP3, and SP4 included in the first pixel P1 is connected to one of the gate lines , And the gate electrode of the switching transistor Tsw of the other two sub-pixels may be connected to the other gate line.

For example, when the gate electrode of the switching transistor Tsw of the first and third sub-pixels SP1 and SP3 is connected to the first gate line GL1, the second and fourth sub-pixels SP2 and SP4, The gate electrode of the switching transistor Tsw may be connected to the second gate line GL2.

Alternatively, when the gate electrode of the switching transistor Tsw of the first and third sub-pixels SP1 and SP3 is connected to the second gate line GL2, the switching of the second and fourth sub-pixels SP2 and SP4 A gate electrode of the transistor Tsw may be connected to the first gate line GL1.

The drain electrode of the switching transistor Tsw of the two sub-pixels among the first to fourth sub-pixels SP1, SP2, SP3 and SP4 included in the first pixel P1 is connected to one of the data lines , And the drain electrode of the switching transistor Tsw of the other two sub-pixels may be connected to the other data line.

 For example, when the drain electrode of the switching transistor Tsw of the first and second sub-pixels SP1 and SP2 is connected to the first data line DL1, the third and fourth sub-pixels SP3 and SP4, The drain electrodes of the switching transistor Tsw may be connected to the second data line DL2.

That is, each of the pixels P of the OLED display 100 according to the embodiment of the present invention supplies data voltages to the first through fourth sub-pixels using two gate lines and two data lines .

Accordingly, the number of data lines can be reduced to half compared with the case where data voltages are supplied to the first to fourth sub-pixels by using one gate line and four data lines in the related art, Therefore, the manufacturing cost can be reduced.

The gate electrode of the sensing transistor Tse of the sub-pixel included in each pixel is connected to the same sensing line, and the drain electrode of the sensing transistor Tse of the sub- Lt; / RTI >

Accordingly, it is possible to sense the currents of the driving transistors of the first to fourth sub-pixels included in each pixel on the same sensing line through the same reference voltage line, so that the number of sensing lines can be reduced, .

5 is a timing chart schematically showing sensing driving of an organic light emitting device according to an embodiment of the present invention. 4 will be described together.

In FIG. 5, only Nth (N is a positive integer) to (N + 3) frame periods are illustrated for convenience of explanation.

Here, when driven at a frequency of 60 Hz, 60 frame periods may be included in 1 second. In this case, each of the frame periods may be approximately 16.67 ms.

 As shown in FIG. 5, each of the frame periods may include an active period (AP) and a blank period (BP).

The active period AP is a data addressing period in which data voltages are supplied to the sub-pixels of the pixels of the display panel (10 in Fig. 1).

In the OLED display 100 according to the exemplary embodiment of the present invention, the first to fourth sub-pixels SP1, SP2, and SP3 may be connected to one sensing line SL1, SP2, SP3, SP4) of the driving transistors Tdr.

The first and second gate signals Scan1 and Scan2 of the gate high voltage VGH may be sequentially applied to the first and second gate lines GL1 and GL2 during the active period AP.

At this time, the first and second data voltages D1 and D2 are applied to the first and second data lines DL1 and DL2 in synchronization with the gate signals Scan1 and Scan2 of the gate high voltage VGH, Respectively.

Therefore, the sub-pixels SP1, SP2, SP3, and SP4 connected to the gate lines GL1 and GL2 to which the gate signals Scan1 and Scan2 of the gate high voltage VGH are supplied during the active period AP are supplied to the data lines The data voltages D1 and D2 may be supplied through the data lines DL1 and DL2.

The first sensing signal Sense1 of the gate high voltage VGH may be sequentially applied to the first sensing line SL1 during the active period AP.

At this time, the reference voltage is supplied to the first reference line RL1. Accordingly, the sub-pixels SP1, SP2, SP3, and SP4 connected to the first sensing line SL1 to which the first sensing signal Sense1 is supplied during the active period AP are connected to the reference line RL1 via the first reference line RL1, Voltage can be applied.

The gate high voltage VGH corresponds to a voltage capable of turning on the switching transistor Tsw and the sensing transistor Tse of the sub-pixels SP1, SP2, SP3, and SP4.

On the other hand, the gate-low voltage VGL corresponds to a voltage capable of turning off the switching transistor Tsw and the sensing transistor Tse of the sub-pixel.

Here, the gate low voltage VGL may be a voltage lower than the gate high voltage VGH.

Meanwhile, four sub-pixels SP1, SP2, SP3 and SP4 connected to the first sensing line SL1 are connected to the first and second gate lines GL1 and GL2.

As a result, the first sensing signal Sense1 can be applied to each of the two gate signals.

That is, the width of the first sensing signal Sense1 is wider than the width of each of the gate signals Scan1 and Scan2, and four sub-pixels SP1, SP2, SP3, and SP4 connected to the first sensing line SL1 When connected to two gate lines GL1 and GL2, the width of the first sensing signal Sense1 may be approximately twice as wide as the width of each of the gate signals Scan1 and Scan2.

The operation of each of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 of the first pixel SP during the active period AP of the n-th frame to the (n + 3) -th frame is as follows.

First, during the active period AP, the first and second gate signals Scan1 and Scan2 of the gate high voltage VGH are sequentially applied to the first and second gate lines GL1 and GL2, respectively.

The switching transistor Tsw of each of the sub-pixels SP1, SP2, SP3 and SP4 is turned on when the gate signals Scan1 and Scan2 of the gate high voltage VGH are supplied to the gate lines GL1 and GL2.

Thus, the data voltages (or data signals) D1 and D2 of the data lines DL1 and DL2 are supplied to the gate electrode of the driving transistor Tdr.

Secondly, during the active period AP, the sensing transistor Tse is turned on by the first sensing signal Sense1 of the gate high voltage VGH supplied to the first sensing line SL1.

For this reason, the reference voltage of the first reference line RL1 is supplied to the source electrode of the driving transistor Tdr.

The difference between the gate voltage of the driving transistor Tdr and the source voltage during the active period AP is stored in the storage capacitor Cst.

When both the switching transistor Tsw and the sensing transistor Tse are turned off, the current Ids corresponding to the difference between the gate voltage and the source voltage of the driving transistor Tdr flows to the organic light emitting diode OLED.

Since the data voltages D1 and D2 are voltages at which the threshold voltage of the driving transistor Tdr is compensated, the current flowing to the organic light emitting diode OLED through the driving transistor Tdr does not depend on the threshold voltage of the driving transistor Tdr Do not.

The operation of each of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 of the first pixel SP during the blank period BP of the n-th frame is as follows.

The blank period BP is divided into first to second periods T1 and T2. The first period T1 is a period during which the first and second gate signals Scan1 and Scan2 are simultaneously supplied to the first and second gate lines GL1 and GL2 and the second period T2 is a period during which the sub- And the gate signals Scan1 and Scan2 are supplied to one gate line GL1 and GL2 connected to the pixels SP1, SP2, SP3 and SP4.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 are connected to the first and second gate lines GL1 and GL2 in the first and second periods T1 and T2 of the blank period BP, And the first sensing signal Sense1 of the gate high voltage VGH at the same time.

For example, during the first period T1 of the blank period BP of the n-th frame period, the gate signals Scan1 and Scan2 of the gate high voltage VGH are applied to the first and second gate lines GL1 and GL2 Can be supplied at the same time.

At this time, the first and second data voltages D1 and D2 of the black data voltage may be supplied to the first and second data lines DL1 and DL2 during the first period T1.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 connected to the first and second gate lines GL1 and GL2 during the first period T1 are connected to the first and second data lines DL1 and DL2 To receive the black data voltage.

During the second period T2, the gate signals Scan1 and Scan2 of the gate high voltage VGH are supplied to the gate lines GL1 and GL2 connected to the pixels to be sensed.

For example, the first gate signal Scan1 of the gate high voltage VGH is supplied only to the first gate line GL1 during the second period T2 of the blank period BP of the n-th frame period.

The first gate signal Scan1 of the gate high voltage VGH is applied only to the first and third sub-pixels SP1 and SP3 connected to the first gate line GL1 during the second period T2 have

Then, the first data voltage D1 of the sensing data signal is supplied to the first data line DL1 during the second period T2.

Accordingly, the first sub-pixel SP1 connected to the first gate line GL1 during the second period T2 is supplied with the first data voltage D1, which is the first sensing data signal, through the first data line DL1, ).

At this time, the second data voltage D2 of the black data voltage is supplied to the second data line DL2 during the second period T2.

Accordingly, the third sub-pixel SP3 connected to the first gate line GL1 during the second period T2 can receive the black data voltage through the second data line DL2.

Therefore, the current of the driving transistor Tdr of the first sub-pixel SP1 can be sensed through the first reference line RL1 during the second period T2 of the blank period BP of the n-th frame period .

That is, the second through fourth sub-pixels SP2 and SP3 except for the first sub-pixel SP1 in the first through fourth sub-pixels SP1, SP2, SP3 and SP4 during the blank period BP of the n- SP4 are applied with the black data voltage so that the currents of the driving transistors Tdr of the first sub-pixel SP1 are accurately sensed without being affected by the second to third sub-pixels SP2, SP3, SP4 .

The operation of each of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 of the first pixel SP during the blank period BP of the (n + 1) th frame is as follows.

The blank period BP is divided into first to second periods T1 and T2. The first period T1 is a period during which the first and second gate signals Scan1 and Scan2 are simultaneously supplied to the first and second gate lines GL1 and GL2 and the second period T2 is a period during which the sub- And the gate signals Scan1 and Scan2 are supplied to one gate line GL1 and GL2 connected to the pixels SP1, SP2, SP3 and SP4.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 are connected to the first and second gate lines GL1 and GL2 in the first and second periods T1 and T2 of the blank period BP, And the first sensing signal Sense1 of the gate high voltage VGH at the same time.

For example, during the first period T1 of the blank period BP of the (n + 1) -th frame period, the gate signals Scan1 and Scan2 of the gate high voltage VGH are applied to the first and second gate lines GL1 and GL2, Can be supplied at the same time.

At this time, the first and second data voltages D1 and D2 of the black data voltage may be supplied to the first and second data lines DL1 and DL2 during the first period T1.

Accordingly, the first to fourth sub-pixels SP1, SP2, SP3 and SP4 connected to the first and second gate lines GL1 and GL2 during the first period T1 are connected to the first and second data lines D1 and D2, D2, respectively.

During the second period T2, the gate signals Scan1 and Scan2 of the gate high voltage VGH are supplied to the gate lines GL1 and GL2 connected to the pixels to be sensed.

For example, the second gate signal Scan2 of the gate high voltage VGH is supplied only to the second gate line GL2 during the second period T2 of the blank period BP of the (n + 1) -th frame period.

The second gate signal Scan2 of the gate high voltage VGH is applied only to the second and fourth sub-pixels SP2 and SP4 connected to the second gate line GL2 during the second period T2 have

Then, the first data voltage D1 of the sensing data signal is supplied to the first data line DL1 during the second period T2.

Accordingly, the second sub-pixel SP2 connected to the second gate line GL2 during the second period T2 can receive the sensing data signal through the first data line DL1.

At this time, the second data voltage D2 of the black data voltage is supplied to the second data line DL2 during the second period T2.

Accordingly, the fourth sub-pixel SP4 connected to the second gate line GL2 during the second period T2 can receive the black data voltage through the second data lines DL2.

Therefore, during the second period T2 of the blank period BP of the (n + 1) -th frame period, the current of the driving transistor Tdr of the second subpixel SP2 can be sensed through the first reference line RL1 .

That is, during the second period of the blank period BP of the (n + 1) -th frame period, the first, second, and third sub-pixels SP1, SP2, SP3, The black data voltage is applied to the fourth sub-pixels SP1, SP3 and SP4 so that the second sub-pixel SP2 is not affected by the first, third and fourth sub-pixels SP1, SP3 and SP4, The currents of the driving transistors Tdr can be accurately sensed.

The operation of each of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 of the first pixel SP during the blank period BP of the (n + 2) -th frame is as follows.

The blank period BP is divided into first to second periods T1 and T2. The first period T1 is a period during which the first and second gate signals Scan1 and Scan2 are simultaneously supplied to the first and second gate lines GL1 and GL2 and the second period T2 is a period during which the sub- And the gate signals Scan1 and Scan2 are supplied to one gate line GL1 and GL2 connected to the pixels SP1, SP2, SP3 and SP4.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 are connected to the first and second gate lines GL1 and GL2 in the first and second periods T1 and T2 of the blank period BP, And the first sensing signal Sense1 of the gate high voltage VGH at the same time.

For example, during the first period T1 of the blank period BP of the (n + 2) -th frame period, the gate signals Scan1 and Scan2 of the gate high voltage VGH are applied to the first and second gate lines GL1 and GL2, Can be supplied at the same time.

At this time, the first and second data voltages D1 and D2 of the black data voltage may be supplied to the first and second data lines DL1 and DL2 during the first period T1.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 connected to the first and second gate lines GL1 and GL2 during the first period T1 are connected to the first and second data lines DL1, And the black data voltage may be applied through the data lines DL2.

During the second period T2, the gate signals Scan1 and Scan2 of the gate high voltage VGH are supplied to the gate lines GL1 and GL2 connected to the pixels to be sensed.

For example, the first gate signal Scan1 of the gate high voltage VGH is supplied only to the first gate line GL1 during the second period T2 of the blank period BP of the (n + 2) -th frame period.

The first gate signal Scan1 of the gate high voltage VGH is applied only to the first and third sub-pixels SP1 and SP3 connected to the first gate line GL1 during the second period T2 have.

The second data voltage D2 of the sensing data signal is supplied to the second data line DL2 during the second period T2.

Accordingly, the third sub-pixel SP3 connected to the first gate line GL1 during the second period T2 can receive the sensing data signal through the second data line DL1.

At this time, the first data voltage D1 of the black data voltage is supplied to the first data line DL1 during the second period T2.

Accordingly, the first sub-pixel SP1 connected to the first gate line GL1 during the second period T2 can receive the black data voltage through the first data line DL1.

Therefore, during the second period T2 of the blank period BP of the (n + 2) -th frame period, the current of the driving transistor Tdr of the third sub-pixel SP3 can be sensed through the first reference line RL1 .

In other words, the first, second, and fourth sub-pixels excluding the third sub-pixel SP3 in the first through fourth sub-pixels SP1, SP2, SP3, and SP4 during the blank period (BP) The black data voltage is applied to the pixels SP1, SP2 and SP4 so that the driving transistors of the third sub-pixel SP3 (the second sub-pixel SP3) are not affected by the first, Tdr) can be accurately sensed.

The operation of each of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 of the first pixel SP during the blank period BP of the n + +3 frame is as follows.

The blank period BP is divided into first to second periods T1 and T2. The first period T1 is a period during which the first and second gate signals Scan1 and Scan2 are simultaneously supplied to the first and second gate lines GL1 and GL2 and the second period T2 is a period during which the sub- And the gate signals Scan1 and Scan2 are supplied to one gate line GL1 and GL2 connected to the pixels SP1, SP2, SP3 and SP4.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 are connected to the first and second gate lines GL1 and GL2 in the first and second periods T1 and T2 of the blank period BP, And the first sensing signal Sense1 of the gate high voltage VGH at the same time.

For example, during the first period T1 of the blank period BP of the (n + 3) -th frame period, the gate signals Scan1 and Scan2 of the gate high voltage VGH are applied to the first and second gate lines GL1 and GL2, Can be supplied at the same time.

At this time, the first and second data voltages D1 and D2 of the black data voltage may be supplied to the first and second data lines DL1 and DL2 during the first period T1.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 connected to the first and second gate lines GL1 and GL2 during the first period T1 are connected to the first and second data lines DL1, And the black data voltage may be applied through the data lines DL1 and DL2.

During the second period T2, the gate signals Scan1 and Scan2 of the gate high voltage VGH are supplied to the gate lines GL1 and GL2 connected to the pixels to be sensed.

For example, the second gate signal Scan2 of the gate high voltage VGH is supplied only to the second gate line GL2 during the second period T2 of the blank period BP of the (n + 3) -th frame period.

The second gate signal Scan2 of the gate high voltage VGH is applied only to the second and fourth sub-pixels SP2 and SP4 connected to the second gate line GL2 during the second period T2 Can

The second data voltage D2 of the sensing data signal is supplied to the second data line DL2 during the second period T2.

Accordingly, the fourth sub-pixel SP4 connected to the second gate line GL2 during the second period T2 can receive the sensing data signal through the second data line DL2.

At this time, the first data voltage D1 of the black data voltage is supplied to the first data line DL1 during the second period T2.

Accordingly, the second sub-pixel SP2 connected to the second gate line GL2 during the second period T2 can receive the black data voltage through the second data lines DL2.

Therefore, during the second period T2 of the blank period BP of the (n + 3) -th frame period, the current of the driving transistor Tdr of the fourth sub-pixel SP4 can be sensed through the first reference line RL1 .

That is, during the first period of the blank period BP of the (n + 3) -th frame period, the first, second, and third sub-pixels SP1, SP2, SP3, The black data voltage is applied to the third sub-pixels SP1, SP2 and SP3 so that the fourth sub-pixel SP4 is not affected by the first, second and third sub-pixels SP1, SP2 and SP3, The currents of the driving transistors Tdr can be accurately sensed.

As described above, each of the pixels P1 and P2 of the OLED display 100 according to the embodiment of the present invention uses two gate lines GL1 and GL2 and two data lines DL1 and DL2 To supply the data voltages to the first to fourth sub-pixels SP1, SP2, SP3 and SP4.

Accordingly, the number of data lines can be reduced to half compared with the case where data voltages are supplied to the first to fourth sub-pixels by using one gate line and four data lines in the related art, Therefore, the manufacturing cost can be reduced.

1) of the sensing transistor Tse of the first to fourth sub-pixels SP1, SP2, SP3, and SP4 included in each pixel, May be connected to the same sensing line, and the drain electrode may be connected to the same reference line.

Accordingly, it is possible to sense the currents of the driving transistors Tdr of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 included in each pixel on the same sensing line through the same reference voltage line RL1 Thus, the number of sensing lines can be reduced, so that the aperture ratio of each pixel can be increased.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

GL1: first gate line GL2: second gate line
GL3: third gate line GL4: fourth gate line
DL1: first data line DL2: second data line
RL1: first reference line P1: first pixel
P2: second pixel SP1: first sub-pixel
SP2: second sub-pixel SP3: third sub-pixel
SP4: fourth sub-pixel SP5: fifth sub-pixel
SP6: sixth sub pixel SP7: seventh sub pixel
SP8: eighth sub-pixel Tsw: switching transistor
Tdr: driving transistor Tse: sensing transistor
OLED: Organic Light Emitting Diode Cst: Storage Capacitor
VDD: first power supply voltage VSS: second power supply voltage

Claims (12)

First and second data lines;
First and second gate lines crossing the first and second data lines;
A first sensing line disposed in parallel with the first and second gate lines;
A first reference line intersecting the first and second gate lines; And
And first to fourth sub-pixels corresponding to the first and second gate lines and the first and second data lines,
A switching transistor of the first sub-pixel is connected to the first gate line, the first data line, a sensing transistor of the first sub-pixel is connected to the first sensing line, the first reference line,
Pixel, a switching transistor of the second sub-pixel is connected to the second gate line, the first data line, and a sensing transistor of the second sub-pixel is connected to the first sensing line and the first reference line,
Pixel is connected to the first gate line, the second data line, and the sensing transistor of the third sub-pixel is connected to the first sensing line and the first reference line,
The switching transistor of the fourth sub-pixel is connected to the second gate line and the second data line, and the sensing transistor of the fourth sub-pixel is connected to the first sensing line and the first reference line. Device.
The method according to claim 1,
Each of the first through fourth sub-
Organic light emitting diodes;
The gate electrode of the driving transistor is turned on by the gate signal of either the first gate line or the second gate line to supply the data voltage of either the first data line or the second data line to the gate electrode of the driving transistor The switching transistor;
A gate electrode is connected to the drain electrode of the switching thin film transistor, a drain electrode is connected to the driving voltage wiring, a source electrode is connected to the organic light emitting diode, and a voltage difference between the gate voltage and the source voltage is applied to the organic light emitting diode A driving transistor for adjusting the amount of current flowing;
A gate electrode is connected to the first sensing line, a drain electrode is connected to the first reference line, a source electrode is connected to a source electrode of the driving transistor, and a sensing signal of the first sensing line is turned on And the source electrode of the driving transistor is connected to the first reference line,
And an organic light emitting diode (OLED).
3. The method of claim 2,
And each of the first to fourth sub-pixels further includes a storage capacitor connected to a gate electrode and a source electrode of the driving transistor.
The method according to claim 1,
Wherein the first to fourth sub-pixels are red, white, blue, and green sub-pixels.
The method according to claim 1,
One frame period includes an active period and a blank period, and the blank period includes first and second periods,
Sequentially supplying gate signals to the first and second gate lines during the active period,
Simultaneously supplying gate signals to each of the first and second gate lines during a first period (T1) of the blank period,
And a gate signal output part for supplying a gate signal to one of the first and second gate lines during the second period (T2) of the blank period.
6. The method of claim 5,
And a sensing signal output unit for supplying a sensing signal to each of the first to fourth sub-pixels connected to the first sensing line during the first and second periods of the blank period.
The method according to claim 6,
Outputting corresponding data signals to the first and second data lines during the active period,
And outputs a black data signal predefined as a data voltage for non-sensing in any one of the first and second data lines during the first and second periods of the blank period, And a data driver for alternately outputting the black data signal and the sensing data signal.
First and second data lines, first and second gate lines crossing the first and second data lines, a first sensing line arranged in parallel with the first and second gate lines, 1 and a second gate line, and first to fourth sub-pixels corresponding to the first and second gate lines and the first and second data lines, In the driving method,
Sequentially supplying gate signals to the first and second gate lines during an active period of one frame, and supplying a data signal to the first and second data lines;
Simultaneously supplying gate signals to each of the first and second gate lines during a first period (T1) of a blank period of one frame;
Supplying a gate signal to one of the first and second gate lines during a second period (T2) of a blank period of one frame;
Sensing the first to fourth sub-pixels simultaneously by supplying a sensing signal to each of the first to fourth sub-pixels connected to the first sensing line during the first and second periods,
And a driving method of the organic light emitting display device.
9. The method of claim 8,
And simultaneously sensing the first through fourth sub-pixels by supplying a sensing signal to each of the first through fourth sub-pixels connected to the first sensing line during the first and second periods,
The data driver outputs a black data signal predefined as a data voltage for sensing in one of the first and second data lines during the first and second periods, and the other of the first and second data lines And alternately outputting the black data signal and the sensing data signal.
9. The method of claim 8,
A switching transistor of the first sub-pixel is connected to the first gate line, the first data line, a sensing transistor of the first sub-pixel is connected to the first sensing line, the first reference line,
Pixel, a switching transistor of the second sub-pixel is connected to the second gate line, the first data line, and a sensing transistor of the second sub-pixel is connected to the first sensing line and the first reference line,
Pixel is connected to the first gate line, the second data line, and the sensing transistor of the third sub-pixel is connected to the first sensing line and the first reference line,
The switching transistor of the fourth sub-pixel is connected to the second gate line and the second data line, and the sensing transistor of the fourth sub-pixel is connected to the first sensing line and the first reference line. A method of driving a device.
11. The method of claim 10,
Each of the first through fourth sub-
Organic light emitting diodes;
The gate electrode of the driving transistor is turned on by the gate signal of either the first gate line or the second gate line to supply the data voltage of either the first data line or the second data line to the gate electrode of the driving transistor The switching transistor;
A gate electrode is connected to the drain electrode of the switching thin film transistor, a drain electrode is connected to the driving voltage wiring, a source electrode is connected to the organic light emitting diode, and a voltage difference between the gate voltage and the source voltage is applied to the organic light emitting diode A driving transistor for adjusting the amount of current flowing;
A gate electrode is connected to the first sensing line, a drain electrode is connected to the first reference line, a source electrode is connected to a source electrode of the driving transistor, and a sensing signal of the first sensing line is turned on And the source electrode of the driving transistor is connected to the first reference line,
And a driving method of the organic light emitting display device.
12. The method of claim 11,
Wherein each of the first to fourth sub-pixels further includes a storage capacitor connected to a gate electrode and a source electrode of the driving transistor.

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