KR20190124036A - Display panel and display device - Google Patents

Abstract

Embodiments of the present invention relate to a display panel and a display device, in which source/drain electrodes of a thin film transistor for controlling the driving of adjacent subpixels are disposed on different layers, so the area where wirings are arranged is reduced to improve an aperture ratio of the subpixels. In addition, by arranging a color filter representing the same color in subpixels disposed on both sides of an area where data lines are not disposed, it is possible to prevent color mixing in a display panel representing a high resolution image and to remove a part of the black matrix to maximize the effect of improving the aperture ratio.

Description

Display Panels and Display Devices {DISPLAY PANEL AND DISPLAY DEVICE}

Embodiments of the present invention relate to a display panel and a display device.

As the information society develops, the demand for a display device for displaying an image is increasing, and a liquid crystal display device, a plasma display device, and an organic light emitting display device are increasing. Various types of display devices such as the above are utilized.

Such a display apparatus includes a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels defined by intersections of the gate lines and the data lines are disposed. And various driving circuits such as a gate driving circuit and a data driving circuit for driving such a gate line, a data line, and the like.

The gate driving circuit outputs a scan signal to the plurality of gate lines to drive the gate lines. The data driving circuit supplies the data voltages to the plurality of data lines in accordance with the timing at which the scan signal is applied so that each subpixel can display an image with brightness according to the data voltage.

Meanwhile, in order to display high resolution images, such display devices are increasing in number of subpixels disposed per unit area in a display panel. That is, the size of the subpixel is getting smaller due to the demand for high resolution.

However, it is difficult for signal wirings such as gate lines and data lines disposed in such subpixels to become thinner due to resistance. Therefore, although the size of the subpixel is getting smaller, there is a problem that the aperture ratio of the subpixel is lowered and the efficiency of the display panel is lowered due to the limitation of the signal wiring arranged in the subpixel.

It is an object of embodiments of the present invention to provide a subpixel structure capable of improving the aperture ratio of a subpixel in a display panel showing a high resolution, a display panel including the subpixel, and a display device.

It is an object of embodiments of the present invention to provide a display panel and a display device capable of maintaining screen quality while maximizing the aperture ratio of a subpixel through a color filter arrangement in a subpixel structure that improves an aperture ratio of a subpixel. .

An object of the embodiments of the present invention is to minimize the change in the structure of the non-active area of the display panel according to the subpixel structure with improved sub-pixel aperture ratio, thereby making it possible to easily implement a sub-pixel with improved aperture ratio And to provide a display device.

In one aspect, embodiments of the present invention provide a display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels defined by intersections of gate lines and data lines are disposed.

The display panel includes a first data line, a first electrode electrically connected to the first data line, a first insulating layer disposed on the first data line and the first electrode, and a first insulating layer. A gate electrode, a second insulating layer disposed on the gate electrode, a second data line disposed on the second insulating layer, a second electrode disposed on the second insulating layer and electrically connected to the second data line; A planarization layer disposed on the second data line and the second electrode, a first pixel electrode disposed on the first subpixel on the planarization layer and electrically connected to the first electrode through the first contact hole, and on the planarization layer. It may include a second pixel electrode disposed in two subpixels and electrically connected to the second electrode through the second contact hole.

In another aspect, embodiments of the present invention provide a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of subpixels and including an active region and a non-active region, and a gate driving the plurality of gate lines. A display device including a driving circuit and a data driving circuit for driving a plurality of data lines is provided.

In such a display device, the active area of the display panel includes a first data line, a first electrode electrically connected to the first data line, a first insulating layer disposed on the first data line and the first electrode, A gate electrode disposed on the first insulating layer, a second insulating layer disposed on the gate electrode, a second data line disposed on the second insulating layer, a second data line disposed on the second insulating layer, A second electrically connected electrode, a planarization layer disposed on the second data line and the second electrode, and a first pixel disposed in the first subpixel on the planarization layer and electrically connected to the first electrode through the first contact hole. The electrode may include a second pixel electrode disposed in the second subpixel on the planarization layer and electrically connected to the second electrode through the second contact hole.

According to embodiments of the present invention, transistors for driving subpixels disposed on both sides of a region where data lines are disposed are disposed on different layers, and the transistors are controlled through a shared gate electrode, thereby providing data to the subpixels. By reducing the area where the lines are placed, the subpixels can improve the aperture ratio.

According to embodiments of the present invention, by placing a color filter representing the same color in two subpixels positioned between regions where data lines are disposed, it is possible to remove a black matrix disposed between subpixels. To maximize the aperture ratio.

According to embodiments of the present invention, a display panel having a subpixel structure with an improved aperture ratio is minimized by minimizing a change in a transistor arrangement process for improving an aperture ratio of a subpixel, thereby minimizing a structure change of a non-active region of the display panel. Make it easy to implement.

1 is a view showing a schematic configuration of a display device according to embodiments of the present invention.
2 is a diagram illustrating an example of a circuit structure of a subpixel in a display device according to example embodiments.
3 is a diagram illustrating a first example of a planar structure of a subpixel in a display device according to embodiments of the present invention.
4 is a diagram illustrating an example of a cross-sectional structure of an AA ′ portion and a BB ′ portion in the planar structure of the subpixel illustrated in FIG. 3.
FIG. 5 is a diagram illustrating a second example of a planar structure of a subpixel in a display device according to example embodiments. FIG.
6 is a diagram illustrating an example of a cross-sectional structure of a CC ′ portion in the planar structure of the subpixel illustrated in FIG.
FIG. 7 is a diagram illustrating a third example of a planar structure of a subpixel in a display device according to example embodiments. FIG.
FIG. 8 is a diagram illustrating an example of a cross-sectional structure of a portion DD ′ in the planar structure of the subpixel illustrated in FIG. 7.
FIG. 9 is a diagram illustrating a fourth example of a planar structure of a subpixel in a display device according to example embodiments. FIG.
FIG. 10 is a diagram illustrating an example of a cross-sectional structure of an EE ′ portion in the planar structure of the subpixel illustrated in FIG. 9.
11 illustrates an example of a cross-sectional structure of a non-active area in a display device according to embodiments of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are shown in different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only to distinguish the components from other components, and the terms are not limited in nature, order, order or number of the components. When a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected to or connected to that other component, but between components It will be understood that the elements may be "interposed" or each component may be "connected", "coupled" or "connected" through other components.

1 illustrates a schematic configuration of a display apparatus 100 according to embodiments of the present invention.

Referring to FIG. 1, the display apparatus 100 according to the exemplary embodiments may include a display panel 110 in which a plurality of subpixels SP are arranged, and a gate driving circuit for driving the display panel 110. 120, a data driving circuit 130, a controller 140, and the like.

In the display panel 110, a plurality of gate lines GL and a plurality of data lines DL are disposed, and a subpixel SP is disposed in an area where the gate lines GL and the data lines DL intersect. .

The gate driving circuit 120 is controlled by the controller 140 and sequentially outputs a scan signal to the plurality of gate lines GL disposed on the display panel 110 to drive the plurality of subpixels SP. To control.

The gate driving circuit 120 may include one or more gate driver integrated circuits (GDICs), and may be located on only one side or both sides of the display panel 110 according to a driving scheme. It may be.

The data driving circuit 130 receives image data from the controller 140 and converts the image data into an analog data voltage. The data voltage is output to each data line DL in accordance with the timing at which the scan signal is applied through the gate line GL so that each subpixel SP expresses brightness according to image data.

The data driver circuit 130 may include one or more source driver integrated circuits (SDICs).

The controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130.

The controller 140 causes the gate driving circuit 120 to output the scan signal in accordance with the timing implemented in each frame, and converts the externally received image data according to the data signal format used by the data driving circuit 130. The converted image data is output to the data driver circuit 130.

The controller 140 may externally output various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, a data enable signal, and a clock signal CLK together with image data. (Eg, from a host system).

The controller 140 may generate various control signals using various timing signals received from the outside and output the various control signals to the gate driving circuit 120 and the data driving circuit 130.

For example, in order to control the gate driving circuit 120, the controller 140 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). Various gate control signals including Gate Output Enable).

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driving circuit 120. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits, and controls a timing of shifting a scan signal. The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

In addition, the controller 140 may control a data driving circuit 130 to control the data driving circuit 130, a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE, Source). Output data), and the like.

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driving circuit 130. The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver circuit 130.

The display apparatus 100 may provide a power management integrated circuit that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, or controls various voltages or currents to be supplied. It may further include.

Each subpixel SP is defined by the intersection of the gate line GL and the data line DL, and a liquid crystal or a light emitting device may be disposed according to the type of the display apparatus 100.

For example, when the display device 100 is a liquid crystal display device, the display device 100 includes a light source device such as a backlight unit that irradiates light onto the display panel 110, and the liquid crystal is disposed in the subpixel SP of the display panel 110. do. In addition, by adjusting the arrangement of the liquid crystals by the electric field formed as the data voltage is applied to each subpixel SP, an image may be displayed while displaying brightness according to the image data.

Alternatively, the display apparatus 100 may display an image by displaying brightness according to image data by using the self-light emitting device. The display apparatus 100 includes a light emitting device such as a light emitting diode (LED) or an organic light emitting diode (OLED) in each subpixel SP, and controls an electric current flowing through the light emitting device according to a data voltage to display an image. I can display it.

2 illustrates an example of a circuit structure of a subpixel SP in the display apparatus 100 according to the exemplary embodiments of the present invention, and illustrates a case of a liquid crystal display apparatus.

Referring to FIG. 2, one gate line GL and one data line DL may cross each other in the subpixel SP. In some cases, two or more gate lines GL may be disposed between the subpixels SP, or one data line DL may be disposed for each of the two or more subpixels SP.

A thin film transistor TFT controlled by a scan signal applied to the gate line GL and transferring a data voltage supplied through the data line DL to the pixel electrode PXL may be disposed in the subpixel SP. have. The common electrode COM to which the common voltage is applied may be disposed, and the capacitance C may be formed between the common electrode COM and the pixel electrode PXL.

The thin film transistor TFT may include a first node N1, a second node N2, and a third node N3.

The first node N1 may be a gate node of the thin film transistor TFT and is electrically connected to the gate line GL. The second node N2 may be a source node or a drain node, and is electrically connected to the data line DL. The third node N3 may be a drain node or a source node and is electrically connected to the pixel electrode PXL.

The thin film transistor TFT is turned on when a scan signal having a turn-on level is applied through the gate line GL, so that the data voltage supplied through the data line DL is applied to the pixel electrode PXL. .

The subpixel SP displays brightness according to image data when the arrangement of liquid crystals is adjusted according to an electric field formed by a data voltage applied to the pixel electrode PXL and a common voltage applied to the common electrode COM. Display.

The subpixel SP is divided into a region in which the pixel electrode PXL and the common electrode COM form an electric field, and a region in which the gate line GL, the data line DL, and the thin film transistor TFT are disposed. Can be. Here, since the image is displayed through an area where the pixel electrode PXL and the common electrode COM form an electric field, the ratio of the area in the subpixel SP may be very important for the screen quality.

3 illustrates a first example of a planar structure of a subpixel SP in the display apparatus 100 according to the exemplary embodiments of the present invention.

Referring to FIG. 3, each subpixel SP disposed on the display panel 110 may be defined by the intersection of the gate line GL and the data line DL. The thin film transistor TFT, the pixel electrode PXL, the common electrode COM, and the like may be disposed in each subpixel SP.

For example, the first subpixel SP1 is defined by the intersection of the first gate line GL1 and the first data line DL1, and the intersection of the first gate line GL1 and the second data line DL2. The second subpixel SP2 may be defined by.

The first pixel electrode PXL1 may be disposed in the first subpixel SP, and the thin film transistor TFT that controls the data voltage to be applied to the first pixel electrode PXL1 may be disposed.

The thin film transistor TFT may include a gate electrode, a source electrode, a drain electrode, an active layer, and the like.

The first gate electrode G1 of the thin film transistor TFT disposed in the first subpixel SP is electrically connected to the first gate line GL1, and as shown in FIG. 3, the first gate line It may be a structure formed integrally with the GL1.

In addition, the source electrode or the drain electrode of the thin film transistor TFT is electrically connected to the first data line DL1. As shown in FIG. 3, the source electrode or the drain electrode of the thin film transistor TFT may be part of the first data line DL1 or may be a first data line. It may have a structure formed integrally with the DL1.

The drain electrode or the source electrode of the thin film transistor TFT is electrically connected to the first pixel electrode PXL1, and is represented by the first electrode 310 in the example of FIG. 3. The first electrode 310 may be electrically connected to the first pixel electrode PXL1 through the first contact hole CH1.

Here, as shown in part X, a portion of the first electrode 310 is formed of the second gate electrode G2 to compensate for capacitance formed between the gate electrode and the source / drain electrode. May overlap with a portion.

Although not shown in FIG. 3, an active layer made of a semiconductor material may be disposed on the first gate electrode G1.

That is, when a voltage is applied to the first gate electrode G1 by the scan signal applied to the first gate line GL1, the data voltage supplied through the first data line DL1 may cause the first electrode 310 to be applied. The first pixel electrode PXL1 is transferred to the first pixel electrode PXL1. In addition, the alignment of the liquid crystals may be adjusted by an electric field formed between the first pixel electrode PXL1 and the common electrode COM, thereby displaying brightness according to the data voltage.

4 illustrates an example of a cross-sectional structure of an A-A 'portion and a B-B' portion in the planar structure of the subpixel SP shown in FIG. 3.

Referring to FIG. 4, a first gate electrode G1 and a second gate electrode G2 are disposed on the first substrate 400. The gate insulating layer 410 is disposed on the first gate electrode G1 and the second gate electrode G2.

An active layer constituting the thin film transistor TFT and a source / drain electrode are disposed on the gate insulating layer 410.

For example, the first active layer ACT1, the first data line DL1, and the first electrode 310 may be positioned on the first gate electrode G1. Here, the first data line DL1 may be a source electrode or a drain electrode, and the first electrode 310 may be a drain electrode or a source electrode.

The passivation layer 420 is disposed on the source / drain electrodes, and the planarization layer 430 is disposed on the passivation layer 420.

The common electrode COM is disposed on the planarization layer 430, and the pixel insulating layer 440 is disposed on the common electrode COM. The pixel electrode PXL is disposed on the pixel insulating layer 440. Alternatively, in some cases, the pixel electrode PXL may be disposed on the planarization layer 430, and the common electrode COM may be disposed on a layer higher than the pixel electrode PXL.

The compensation pattern 450 may be disposed on the common electrode COM to reduce the resistance of the common electrode COM. The compensation pattern 450 may be disposed in an area overlapping the data line DL.

The pixel electrode PXL may be electrically connected to the thin film transistor TFT through the contact hole CH formed in the planarization layer 430.

For example, the first pixel electrode PXL1 is electrically connected to the first electrode 310 through the first contact hole CH1, and the second pixel electrode PXL2 is formed through the second contact hole CH2. The second electrode 320 may be electrically connected to the second electrode 320.

As such, the pixel electrode PXL to which the data voltage according to the image data is applied and the thin film transistor TFT and the signal wires for controlling the application of the data voltage to the pixel electrode PXL are arranged in the subpixel SP. Can be.

In this case, in order for the display panel 110 to display a high resolution image, the number of subpixels SP disposed per unit area must be increased, thereby reducing the size of the subpixels SP. However, since the signal wires arranged in the subpixel SP are difficult to be disposed thinly due to resistance, the ratio of the area where the pixel electrode PXL forms an electric field in the subpixel SP may be low. That is, the aperture ratio of the subpixel SP in the display panel 110 representing the high resolution image may decrease.

In the display apparatus 100 according to the exemplary embodiments, the thin film transistor TFT that controls the application of the data voltage to the pixel electrode PXL disposed in the subpixel SP may have different values depending on the subpixel SP. The structure that can be arranged in the layer improves the aperture ratio of the subpixel SP and enables the display of high resolution images.

5 illustrates a second example of a planar structure of a subpixel SP in the display apparatus 100 according to the exemplary embodiments of the present invention.

Referring to FIG. 5, the subpixel SP disposed on the display panel 110 may be defined by the intersection of the gate line GL and the data line DL.

For example, the first subpixel SP1 is defined by the first gate line GL1 and the first data line DL1. The second subpixel SP2 is defined by the second gate line GL2 and the second data line DL2.

Here, the first data line DL1 and the second data line DL2 may be disposed at the boundary between the first subpixel SP1 and the second subpixel SP2. The first data line DL1 and the second data line DL2 may be disposed on different layers. In this case, the first data line DL1 and the second data line DL2 may not overlap each other, or at least some of them overlap each other.

The first data line DL1 may be electrically connected to the first electrode 510 disposed on the same layer. That is, the structure may be electrically connected through an active layer disposed to overlap a portion of the first data line DL1 and a portion of the first electrode 510.

In addition, the second data line DL2 may be electrically connected to the second electrode 520 disposed on the same layer.

The first electrode 510 is electrically connected to the first pixel electrode PXL1 disposed in the first subpixel SP1 through the first contact hole CH1, and the second electrode 520 is connected to the second contact hole. It may be electrically connected to the second pixel electrode PXL2 disposed in the second subpixel SP2 through CH2.

Here, the shared gate electrode SG may be disposed between the layer on which the first data line DL1 is disposed and the layer on which the second data line DL2 is disposed. The shared gate electrode SG may be electrically connected to the first gate line GL1 and may be integrally formed with the first gate line GL1.

That is, the shared gate electrode SG may be the gate electrode G shared by the thin film transistor TFT driving the first subpixel SP1 and the thin film transistor TFT driving the second subpixel SP2. have.

For example, a data voltage supplied through the first data line DL1 is applied to the first pixel electrode PXL1 by a scan signal applied to the shared gate electrode SG, and is applied through the second data line DL2. The supplied data voltage may be applied to the second pixel electrode PXL2.

Therefore, driving of the first subpixel SP1 and the second subpixel SP2 may be controlled through the shared gate electrode SG.

In addition, by reducing the structure in which the data line DL is disposed in the subpixel SP, the area in which the signal wiring is disposed in the subpixel SP may be reduced to increase the aperture ratio of the subpixel SP. To help.

FIG. 6 illustrates an example of a cross-sectional structure of the portion CC ′ in the planar structure of the subpixel SP shown in FIG. 5.

Referring to FIG. 6, the first data line DL1 and the first electrode 510 are disposed on the first substrate 400, and the first data line DL1 and the first electrode 510 are electrically connected to each other. The first active layer ACT1 is disposed.

The first gate insulating layer 411 is disposed on the first data line DL1 and the first electrode 510.

The shared gate electrode SG is disposed on the first gate insulating layer 411, and the second gate insulating layer 412 is disposed on the shared gate electrode SG.

The second data layer DL2, the second electrode 520, and the second active layer electrically connecting the second data line DL2 and the second electrode 520 on the second gate insulating layer 412 ( ACT2) is arranged.

The protective layer 420 and the planarization layer 430 are disposed on the second data line DL2 and the second electrode 520, and the common electrode COM and the pixel insulating layer 440 are disposed on the planarization layer 430. And the pixel electrode PXL may be disposed.

The first pixel electrode PXL1 disposed in the first subpixel SP1 is electrically connected to the first electrode 510 disposed below the first gate insulating layer 411 through the first contact hole CH1. Is connected.

In addition, the second pixel electrode PXL2 disposed in the second subpixel SP2 is electrically connected to the second electrode 520 disposed on the second gate insulating layer 412 through the second contact hole CH2. Is connected. Here, since the layers in which the first electrode 510 and the second electrode 520 are disposed are different from each other, the depth of the first contact hole CH1 and the depth of the second contact hole CH2 may be different.

That is, the thin film transistor TFT that controls the driving of the first subpixel SP1 and the thin film transistor TFT that controls the driving of the second subpixel SP2 are disposed on different layers.

The data voltage supplied to the first data line DL1 is applied to the first pixel electrode PXL1 by the signal applied to the shared gate electrode SG, and the data voltage supplied to the second data line DL2. The second pixel electrode PXL2 may be applied.

Accordingly, driving of the first subpixel SP1 and the second subpixel SP2 may be controlled through the shared gate electrode SG.

In addition, the thin film transistor TFT that controls the driving of the first subpixel SP1 and the thin film transistor TFT that controls the driving of the second subpixel SP2 are disposed on different layers, thereby providing the subpixel SP. In this case, the area in which the data line DL is disposed may be reduced.

That is, both the first data line DL1 for supplying the data voltage to the first subpixel SP1 and the second data line DL2 for supplying the data voltage to the second subpixel SP2 are the first subpixels. By being disposed in an area corresponding to the boundary between SP1 and the second subpixel SP2, it is possible to prevent a reduction in the aperture ratio of the subpixel SP due to the data line DL disposed on the subpixel SP.

As described above, even when the thin film transistor TFT controlling the driving of the adjacent subpixels SP is disposed on different layers, the aperture ratio of the subpixels SP may be improved, thereby allowing the display panel 110 to display a high resolution image. It is possible to improve the screen quality by improving the aperture ratio of the subpixel SP.

In the example illustrated in FIG. 6, the display panel 110 having the subpixel SP structure includes a process of depositing a source / drain electrode such as a first data line DL1 and a first electrode 510. In addition, only the process of depositing the first gate insulating layer 411 may be easily implemented.

FIG. 7 illustrates a third example of a structure of a subpixel SP in the display apparatus 100 according to example embodiments, and illustrates a structure in which a color filter and a black matrix are disposed in each subpixel SP. It is shown.

Referring to FIG. 7, the first data line DL1 and the second data line DL2 are disposed in an area corresponding to a boundary between the first subpixel SP1 and the second subpixel SP2. The first data line DL1 and the second data line DL2 are disposed on different layers, and between the layer on which the first data line DL1 is disposed and the layer on which the second data line DL2 is disposed. The driving of the first subpixel SP1 and the second subpixel SP2 is controlled by the shared gate electrode SG.

The color filter may be disposed in the first subpixel SP1 and the second subpixel SP2. For example, a green color filter is disposed in the first subpixel SP1 and the second subpixel SP2. The blue color filter may be disposed at

In the example of FIG. 7, the color filter is illustrated as being disposed throughout the subpixel SP, but the color filter is disposed only in the region where the pixel electrode PXL is disposed, and in the region where the thin film transistor TFT is disposed. The black matrix may be disposed without the filter.

The first black matrix BM1 may be disposed at a boundary between the first subpixel SP1 and the second subpixel SP2.

The first black matrix BM1 may overlap a portion of the green color filter disposed in the first subpixel SP1 and a portion of the blue color filter disposed in the second subpixel SP2.

In addition, the first black matrix BM1 may be disposed in an area overlapping the first data line DL1 and the second data line DL2 disposed at the boundary between the first subpixel SP1 and the second subpixel SP2. Can be arranged.

In addition, the first black matrix BM1 may be disposed to have a predetermined width W1 to prevent color mixing between adjacent subpixels SP and to protect the data line DL.

The third subpixel SP3 may be disposed on one side of the first subpixel SP1, and the fourth subpixel SP4 may be disposed on one side of the second subpixel SP2.

The third subpixel SP3 and the fourth subpixel SP4 also have a structure in which the adjacent subpixel SP and the gate electrode G of the thin film transistor TFT share the same structure, respectively. The data line DL is not disposed at the boundary between SP1 and the third subpixel SP3. Similarly, the data line DL may not be disposed at a boundary between the second subpixel SP2 and the fourth subpixel SP4.

Accordingly, a second black matrix BM2 is disposed at the boundary between the first subpixel SP1 and the third subpixel SP3 to prevent color mixing, and the second black matrix BM2 is disposed below the data line DL. Since it is not disposed, the width W2 may be narrower than that of the first black matrix BM1.

As such, the second black matrix BM2 is disposed at the boundary between the first subpixel SP1 and the third subpixel SP3 and the boundary between the second subpixel SP2 and the fourth subpixel SP4. As the width becomes narrower, the aperture ratio of the subpixel SP may increase.

FIG. 8 illustrates an example of a cross-sectional structure of the portion D-D ′ in the planar structure of the subpixel SP shown in FIG. 7.

Referring to FIG. 8, a first data line DL1, a first active layer ACT1, and a first electrode 510 are disposed on a first substrate 400, and the first data line DL1 and the first data line are disposed on the first substrate 400. The first gate insulating layer 411 is disposed on the electrode 510.

The shared gate electrode SG is disposed on the first gate insulating layer 411, and the second gate insulating layer 412 is disposed on the shared gate electrode SG.

The second data line DL2, the second active layer ACT2, and the second electrode 520 are disposed on the second gate insulating layer 412.

The first electrode 510 is electrically connected to the first pixel electrode PXL1 disposed in the first subpixel SP1 through the first contact hole CH1, and the second electrode 520 is connected to the second electrode 520. The second pixel electrode PXL2 is electrically connected to the second subpixel SP2 through the contact hole CH2.

Here, a color filter may be disposed in each subpixel SP. For example, a green color filter may be disposed on the first pixel electrode PXL1, and a blue color filter may be disposed on the second pixel electrode PXL2. Can be arranged. The second substrate 460 may be disposed on the color filter.

The first black matrix BM1 is disposed on the boundary between the first subpixel SP1 and the second subpixel SP2 so as to overlap a portion of the color filter, and the first black matrix BM1 is disposed on the first data line DL1. ) And the second data line DL2 overlap each other.

The second black matrix BM2 may be disposed at a boundary between the blue color filter and the red color filter disposed in the adjacent subpixel SP. Since the data line DL is not disposed below the second black matrix BM2, the second black matrix BM2 may be disposed to have a width narrower than that of the first black matrix BM1.

That is, in the display apparatus 100 according to the exemplary embodiments of the present invention, a region in which the data line DL is disposed through a structure in which thin film transistors TFTs driving adjacent subpixels SP are disposed on different layers. It is possible to improve the aperture ratio of the subpixel SP by reducing the width of some black matrices.

In addition, by removing some black matrices through the arrangement structure of the color filters disposed in the subpixel SP in the display apparatus 100 representing the high resolution image, the effect of improving the aperture ratio of the subpixel SP may be maximized.

FIG. 9 illustrates a fourth example of the planar structure of the subpixel SP in the display apparatus 100 according to the exemplary embodiments, and illustrates another example of a structure in which a color filter and a black matrix are disposed.

Referring to FIG. 9, a first data line DL1 and a second data line DL2 are disposed at a boundary between the first subpixel SP1 and the second subpixel SP2. The first data line DL1 and the second data line DL2 are disposed on different layers. The first subpixel SP1 and the second subpixel are formed by the shared gate electrode SG disposed between the layer on which the first data line DL1 is disposed and the layer on which the second data line DL2 is disposed. The drive of SP2) can be controlled.

A color filter may be disposed in each of the first subpixel SP1 and the second subpixel SP2. For example, a red color filter is disposed in the first subpixel SP1 and the second subpixel SP2. A green color filter may be disposed in the.

The first black matrix BM1 may be disposed at a boundary between the first subpixel SP1 and the second subpixel SP2.

The first black matrix BM1 may overlap a portion of the red color filter disposed in the first subpixel SP1 and a portion of the green color filter disposed in the second subpixel SP2, and the adjacent subpixel ( Prevents mixing between SP).

In addition, the first black matrix BM1 may be disposed to overlap with an area where the first data line DL1 and the second data line DL2 are disposed.

The third subpixel SP3 may be disposed adjacent to the first subpixel SP1, and the fourth subpixel SP4 may be disposed adjacent to the second subpixel SP2.

The data line DL for supplying the data voltage to the third subpixel SP3 may be disposed on a different layer from the first data line DL1 or on the same layer. In addition, the data line DL for supplying the data voltage to the fourth subpixel SP4 may be disposed on a different layer from the second data line DL2 or on the same layer.

That is, the thin film transistor TFTs driving the subpixels SP disposed on both sides of the region where the data line DL is disposed are disposed on different layers, but the amount of the region where the data line DL is not disposed. The thin film transistors TFT driving the subpixels SP disposed on the side may be disposed in different layers, or may be disposed in the same layer.

A color filter may be disposed in each of the third subpixel SP3 and the fourth subpixel SP4. For example, a red color filter is disposed in the third subpixel SP3 and the fourth subpixel SP4. A green color filter may be disposed in the.

That is, a color filter representing the same color (red) as the color filter disposed in the first subpixel SP1 may be disposed in the third subpixel SP3, and the second subpixel is disposed in the fourth subpixel SP4. A color filter showing the same color (green) as the color filter disposed in SP2 may be disposed.

The red color filter disposed in the first subpixel SP1 and the red color filter disposed in the third subpixel SP3 may be integrally disposed.

As such, by disposing a color filter representing the same color in the subpixels SP disposed on both sides of the region where the data line DL is not disposed, the black matrix may not be disposed at the boundary of the subpixels SP. have.

Therefore, the partial aperture of the subpixel SP can be further improved by removing part of the black matrix, and as the color filter representing the same color is disposed in the adjacent subpixel SP, mixed color that can be recognized according to the viewing angle occurs. You can do it.

That is, embodiments of the present invention allow the aperture ratio to be improved by reducing the wiring area through a structure in which the data line DL and the thin film transistor TFT driving adjacent subpixels SP are disposed on different layers. The black matrix is disposed only in an area overlapping the area where the data line DL is disposed, thereby maximizing the aperture ratio due to the partial removal of the black matrix.

FIG. 10 illustrates an example of a cross-sectional structure of an E-E 'portion in the planar structure of the subpixel SP shown in FIG. 9.

Referring to FIG. 10, a first data line DL1, a first electrode 510, and a first active layer ACT1 are disposed on a first substrate 400, and the first data line DL1 and the first data line are disposed on the first substrate 400. The first gate insulating layer 411 is disposed on the electrode 510.

The shared gate electrode SG is disposed on the first gate insulating layer 411, and the second gate insulating layer 412 is disposed on the shared gate electrode SG.

The second data line DL2, the second electrode 520, and the second active layer ACT2 are disposed on the second gate insulating layer 412.

The first pixel electrode PXL1 of the first subpixel SP1 is electrically connected to the first electrode 510 through the first contact hole CH1 and the second pixel of the second subpixel SP2. The electrode PXL2 is electrically connected to the second electrode 520 through the second contact hole CH2.

Here, a red color filter may be disposed on the first subpixel SP1 and a green color filter may be disposed on the second subpixel SP2.

Such color filters may be arranged in an extended structure to adjacent subpixels SP.

That is, the red color filter is extended to the subpixel SP adjacent to the first subpixel SP1, and the green color filter is extended to the subpixel SP adjacent to the second subpixel SP2. It can be arranged as.

Therefore, the first black only corresponds to an area corresponding to a boundary between the first subpixel SP1 and the second subpixel SP2 and overlaps with an area where the first data line DL1 and the second data line DL2 are disposed. Matrix BM1 may be disposed.

The black matrix may not be disposed at a boundary between adjacent subpixels SP in which color filters representing the same color are disposed.

For example, as shown in part I of FIG. 10, since the green color filter is disposed on the second subpixel SP2 and the subpixel SP adjacent to the second subpixel SP2, the green color filter is extended. The black matrix may not be disposed at the boundary between the pixels SP.

In this way, the opening ratio of the subpixel SP can be further improved by allowing a part of the black matrix disposed at the boundary between the subpixels SP to be removed.

In addition, by arranging a color filter representing the same color between adjacent subpixels SP, it is possible to prevent a phenomenon in which mixed colors between adjacent subpixels SP are perceived and to display the high resolution image of the subpixels SP in the display panel 110. Maximize the aperture ratio.

Meanwhile, according to the stacking structure of the subpixels SP, the stacking structure of the region in which the image is not displayed on the display panel 110 may also be changed.

FIG. 11 illustrates an example of a cross-sectional structure of the non-active region N / A changed according to the stacked structure of the subpixels SP in the display apparatus 100 according to the exemplary embodiments.

Referring to FIG. 11, the display panel 110 according to the exemplary embodiments of the present invention may include an active area A / A for displaying an image and a subpixel SP disposed thereon, and the active area A / A. It may include a non-active area (N / A) that corresponds to an external area and in which signal wires or driving circuits are disposed.

Here, referring to an example of the cross-sectional structure of the portion J-J ′ in the non-active area N / A of the display panel 110, the first gate insulating layer 411 is disposed on the first substrate 400. The gate metal 1100 is disposed on the first gate insulating layer 411, and the second gate insulating layer 412 is disposed on the gate metal 1100.

The semiconductor material 1110 and the source / drain metal 1120 are disposed on the second gate insulating layer 412, and the protective layer 420, the planarization layer 430, and the like are disposed on the source / drain metal 1120. Can be.

The pixel insulating layer 440 and the pixel metal 1130 may be disposed on the planarization layer 430.

The gate metal 1100 may be the same material disposed on the same layer as the shared gate electrode SG in the subpixel SP. The semiconductor material 1110 may be the same as the active layer in the subpixel SP, and the source / drain metal 1120 may be the same material as the source electrode and the drain electrode in the subpixel SP. The pixel metal 1130 may be made of the same material as the pixel electrode PXL.

The gate metal 1100, the source / drain metal 1120, the pixel metal 1130, and the like may form signal wires disposed in the non-active region N / A of the display panel 110. For example, it may be a wiring to which a control signal such as a gate high voltage, a gate low voltage or a clock signal is applied to the gate driving circuit disposed in the non-active region N / A.

That is, the signal line may be configured in the non-active region N / A by using the same material as the material of the signal line or the electrode in the subpixel SP.

In addition, since only the first gate insulating layer 411 is additionally disposed under the gate metal 1100 according to the stacking structure of the subpixel SP, the non-active area N may be changed even if the stacking structure of the subpixel SP is changed. / A) minimizes structural changes and enables signal wiring.

In an embodiment of the present invention, the materials forming the source electrode and the drain electrode of the thin film transistor TFT for driving adjacent subpixels SP are disposed on different layers, thereby reducing the area of the wiring. It is possible to improve the aperture ratio of SP).

In addition, in the display panel 110 representing the high resolution image, color filters representing the same color are disposed on the subpixels SP located on both sides of the region where the data line DL is not disposed, thereby providing the subpixel SP. It is possible to prevent the phenomenon of mixed color depending on the viewing angle at the boundary.

In addition, by removing a part of the black matrix disposed at the boundary between the subpixels SP, the effect of improving the aperture ratio of the subpixels SP may be maximized.

The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and changes without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention but to describe the scope of the technical spirit of the present invention by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device 110: display panel
120: gate driving circuit 130: data driving circuit
140: controller 310, 510: first electrode
320, 520: second electrode 400: first substrate
410: gate insulating layer 411: first gate insulating layer
412: second gate insulating layer 420: protective layer
430: planarization layer 440: pixel insulating layer
450: compensation pattern 460: second substrate
1100: gate metal 1110: semiconductor material
1120: source / drain metal 1130: pixel metal

Claims (16)

A display panel in which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are disposed,
A first data line;
A first electrode electrically connected to the first data line;
A first insulating layer disposed on the first data line and the first electrode;
A gate electrode on the first insulating layer;
A second insulating layer disposed on the gate electrode;
A second data line disposed on the second insulating layer;
A second electrode disposed on the second insulating layer and electrically connected to the second data line;
A planarization layer disposed on the second data line and the second electrode;
A first pixel electrode disposed in a first subpixel on the planarization layer, and electrically connected to the first electrode through a first contact hole; And
A second pixel electrode disposed on a second subpixel on the planarization layer, and electrically connected to the second electrode through a second contact hole;
Display panel comprising a.
The method of claim 1,
A first color filter disposed on the first subpixel and positioned on the first pixel electrode; And
And a second color filter disposed on the second subpixel and positioned on the second pixel electrode, the second color filter representing a color different from the first color filter.
The method of claim 2,
And a first black matrix disposed at a boundary between the first subpixel and the second subpixel and positioned to overlap an area in which the first data line and the second data line are disposed.
The method of claim 3,
A third pixel electrode disposed on a third subpixel positioned at one side of the first subpixel; And
And a third color filter disposed on the third subpixel and positioned on the third pixel electrode.
The method of claim 4, wherein
And the third color filter exhibits the same color as the first color filter.
The method of claim 5,
And the first color filter and the third color filter are integrally disposed.
The method of claim 4, wherein
The third pixel electrode,
And a third electrode disposed on the same layer as the first electrode or on the same layer as the second electrode and electrically connected to each other through a third contact hole.
The method of claim 4, wherein
And a second black matrix disposed at a boundary between the first subpixel and the third subpixel and having a width narrower than that of the first black matrix.
The method of claim 4, wherein
A fourth pixel electrode disposed on a fourth subpixel positioned at one side of the second subpixel; And
And a fourth color filter disposed on the fourth subpixel and positioned on the fourth pixel electrode.
The method of claim 9,
And the fourth color filter represents the same color as the second color filter, and the second color filter and the fourth color filter are integrally disposed.
The method of claim 1,
And a depth of the first contact hole and a depth of the second contact hole are different.
A display panel including a plurality of gate lines, a plurality of data lines, and a plurality of subpixels, the display panel including an active region and a non-active region;
A gate driving circuit driving the plurality of gate lines; And
A data driving circuit for driving the plurality of data lines,
The active area of the display panel is
A first data line;
A first electrode electrically connected to the first data line;
A first insulating layer disposed on the first data line and the first electrode;
A gate electrode on the first insulating layer;
A second insulating layer disposed on the gate electrode;
A second data line disposed on the second insulating layer;
A second electrode disposed on the second insulating layer and electrically connected to the second data line;
A planarization layer disposed on the second data line and the second electrode;
A first pixel electrode disposed in a first subpixel on the planarization layer, and electrically connected to the first electrode through a first contact hole; And
And a second pixel electrode disposed on a second subpixel on the planarization layer and electrically connected to the second electrode through a second contact hole.
The method of claim 12,
The active area of the display panel is
And a plurality of black matrices disposed at every two subpixels of the plurality of subpixels and positioned at boundaries between the subpixels.
The method of claim 13,
The active area of the display panel is
And a color filter disposed in two subpixels between two black matrices of the plurality of black matrices, the same color and integrally formed.
The method of claim 12,
The active area of the display panel is
A plurality of black matrices disposed at every one of the plurality of subpixels and positioned at boundaries between the subpixels,
And two adjacent black matrices of the plurality of black matrices have different widths.
The method of claim 12,
The non-active area of the display panel is
The first insulating layer and the second insulating layer;
And at least one signal line disposed between the first insulating layer and the second insulating layer and made of the same material as the gate electrode.

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