KR102475572B1 - Display device and driving method thereof - Google Patents

Abstract

The present invention provides a display device capable of preventing image defects by delaying a data voltage according to a delay of a gate driving voltage and a method for driving the same. A display device according to the present invention includes a display panel including a gate line, a data line, and an RC line, and a data driver delaying a data voltage in response to a delay switch signal provided through the RC line and outputting the delayed data voltage to the data line.

Description

Display device and its driving method {DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a display device, and more particularly, to a display device capable of compensating for a delay of a gate driving voltage and a method for driving the same.

Flat Panel Display (FPD) replaces the conventional Cathode Ray Tube (CRT) display device to reduce the size and weight of not only desktop computer monitors, but also portable computers such as notebook computers and PDAs and mobile phone terminals. It is an essential display device to implement the system. Currently commercialized flat panel display devices include liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), and the like. The liquid crystal display device has advantages such as excellent visibility, easy thinning, and low power consumption, and the organic light emitting device has advantages such as a wide viewing angle, excellent contrast ratio, fast response speed, and low power consumption.

1 is a diagram schematically illustrating a conventional display device.

As shown in FIG. 1 , the display device 10 includes a display panel 12 , a timing controller 14 , a data driver 18 , and gate drivers 16a and 16b.

In the display panel 12, a plurality of gate lines GL and a plurality of data lines DL are intersected in a matrix form on a substrate, and a plurality of pixels PX are defined at the intersections.

The timing controller 14 receives a timing signal TS transmitted from an external system (not shown) and generates gate control signals GCS1 and GCS2 and a data control signal DCS. The gate control signals GCS1 and GCS2 are output to the gate drivers 16a and 16b, and the data control signal DCS is output to the data driver 18. In addition, the timing controller 14 generates image data RGB from the image signal VS transmitted from an external system and outputs it to the data driver 18 .

The gate drivers 16a and 16b include a first gate driver 16a and a second gate driver 16b on both sides of the display panel 12 . The first and second gate drivers 16a and 16b generate gate driving voltages in response to the first and second gate control signals GCS1 and GCS2 input from the timing controller 14 . Gate driving voltages are sequentially output from both sides of the plurality of gate lines GL of the display panel 12 .

The data driver 18 generates analog waveform data voltages in response to the data control signal DSC input from the timing controller 14 and digital image data RGB. The data voltage is output to each pixel PX through a plurality of data lines DL of the display panel 12 .

Meanwhile, in the conventional display device 12, the edge area EG of the display panel 12 adjacent to the first and second gate drivers 16a and 16b and the first and second gate drivers 16a and 16b A difference in panel load occurs in the center area CT of the spaced display panel 12 . That is, since the edge area EG of the display panel 12 has a relatively smaller panel load than the center area CT, the gate driving voltage output from the first and second gate driving units 16a and 16b is delayed. phenomenon does not occur. In contrast, since the center region CT of the display panel 12 has a relatively larger panel load than the edge region EG, the gate driving voltage output from the first and second gate driving units 16a and 16b is delayed. phenomenon occurs.

2A and 2B are diagrams showing voltage-time graphs of an edge area and a center area of a display panel in a conventional display device.

That is, as shown in FIG. 2A , delay of the gate driving voltage hardly occurs at the edge portion EG of the display panel 12 . Accordingly, the data driver 18 outputs a data voltage that is accurately synchronized with the gate driving voltage.

On the other hand, as shown in FIG. 2B , a gate driving voltage delay occurs in the center portion CT of the display panel 12 . Therefore, as can be seen in area A (A), the data voltage to be applied at the turn-on time (ton) of the next gate line is applied to the turn-on time (ton) of the corresponding gate line, causing problems of color mixing and image defects. .

An object of the present invention is to provide a display device and a method for driving the display device capable of preventing image defects due to delay in gate driving voltage.

A display device of the present invention for achieving the above object includes a display panel, a timing controller, and a data driver.

The display panel includes gate lines, data lines, and RC lines.

The timing controller generates a switch signal and outputs it to the RC line.

The data driver delays the data voltage in response to the delay switch signal provided through the RC line and outputs the delayed data voltage to the data line.

To achieve the above object, a display device driving method of the present invention includes a switch signal transmission step, a delay switch signal transmission step, a data voltage switching step, and a data voltage application step.

The step of transmitting the switch signal is a step of transmitting the switch signal from the timing controller to the RC line.

The step of transmitting the delay switch signal is a step of transmitting the delay switch signal to the data driver of the display panel through the RC line.

The data voltage switching step is a step of switching the data voltage according to the delay switch signal in the data driver.

The step of applying the data voltage is a step of applying the data voltage to a plurality of data lines.

The display device according to the present invention applies the delayed data voltage to the data line according to the delay time of the gate driving voltage, thereby preventing color mixing and image defects due to delay in the gate driving voltage.

1 is a diagram schematically illustrating a conventional display device.
2A and 2B are diagrams showing voltage-time graphs of an edge area and a center area of a display panel in a conventional display device.
3 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.
4 is an enlarged view of a portion of the display device shown in FIG. 3;
5 is a diagram illustrating a data driver according to an embodiment of the present invention.
6A to 6C are diagrams showing waveforms of gate driving voltages applied to each pixel connected to the second data line, and FIG. 7 describes a delay of the data voltage applied to each pixel connected to the second data line. It is a drawing for
8A to 8C are diagrams showing waveforms of gate driving voltages applied to each pixel connected to the first gate line, and FIG. 9 is a description of the delay of the data voltage applied to each pixel connected to the first gate line. It is a drawing for
10A and 10B are diagrams illustrating voltage-time graphs of an edge area and a center area of a display panel according to an exemplary embodiment of the present invention.
11 is a diagram illustrating a display device driving method according to an exemplary embodiment of the present invention.

Hereinafter, a display device and a driving method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a display device according to an exemplary embodiment of the present invention.

The display device 100 of the present invention may include LCD, OLED, and the like, but hereinafter, for convenience of description, an LCD will be described as an example.

As shown in FIG. 3 , the display device 100 according to the present exemplary embodiment includes a display panel 120 , a timing controller 140 , gate drivers 161 and 162 , and a data driver 180 .

In the display panel 120 , a plurality of gate lines GL and a plurality of data lines DL are crossed in a matrix form on a substrate (not shown) using glass or plastic. Also, a plurality of pixels PX are defined at intersections of the gate line GL and the data line DL. In addition, an RC line (RCL) is additionally disposed on the substrate.

Each pixel PX of the display panel 120 includes at least one thin film transistor (not shown) and a liquid crystal capacitor (not shown). The gate electrode of the thin film transistor is connected to the gate line GL, and the source electrode is connected to the data line DL. Also, the drain electrode is connected to a pixel electrode (not shown) facing the common electrode (not shown) to control the voltage applied to the liquid crystal capacitor. Accordingly, the movement of the liquid crystal is controlled to implement the gradation of the liquid crystal display device.

The RC line RCL may be formed in a non-display area (not shown) located on one side of the display panel in parallel with the gate line GL. Here, the non-display area is formed outside the outermost gate lines GL1 and GLn. By forming the RC line RCL in this way, it is possible to minimize the decrease in the aperture ratio due to the RC line RCL.

Also, the RC line RCL may be formed of the same material as the gate line GL. Also, for convenience in the manufacturing process of the display device, the formation of the RC line (RCL) may be formed on the same layer through the same process as the formation of the gate line (GL).

The timing controller 140 receives a timing signal TS transmitted from an external system (not shown) and generates gate control signals GCS1 and GCS2 and a data control signal DCS. The gate control signals GCS1 and GCS2 are output to the gate driving units 161 and 162 , and the data control signal DCS is output to the data driving unit 180 . Also, the timing controller 140 generates image data RGB from the image signal VS transmitted from an external system and outputs the image data RGB to the data driver 180 . In addition, the timing controller 140 includes an SE generator 142 . The switch signals SE1 and SE2 are generated by the SE generation unit 142 of the timing controller 140 and transmitted to both sides of the RC line RCL.

Here, the gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE. The gate start pulse GSP is applied to shift registers (not shown) of the gate drivers 161 and 162 as a signal that determines when to output the gate driving voltage Vg to the first gate line GL1. The gate shift clock GSC is commonly applied to each shift register and is a clock signal enabling the next shift register (not shown). The gate output enable signal GOE controls the output of the shift register.

Also, the data control signal DCS includes a source start pulse SSP, a source shift clock SSC, and a source output enable signal SOE. The source start pulse SSP determines sampling start timing of the image data RGB of the data driver 180 . The source shift clock SSC is a clock signal that controls a data sampling operation in the data driver 180 . The source output enable signal SOE controls the output of the data driver 180 .

The switch signals SE1 and SE2 are delayed through the RC line RCL and then transmitted to the data driver 180 to delay the output of the data voltage Vdata. In this way, by matching the output timing of the data voltage Vdata with the delay time of the gate driving voltage Vg using the switch signals SE1 and SE2, color mixing of each pixel PX can be prevented.

In addition, the switch signals SE1 and SE2 must be synchronized with the output timing of the data voltage Vdata. Accordingly, the switch signals SE1 and SE2 may be output in synchronization with the data control signal DCS. More specifically, the data control signal DCS may be synchronized with the source output enable signal SOE for controlling the output of the data driver 180 .

The gate drivers 161 and 162 include a first gate driver 161 and a second gate driver 162 on both sides of the display panel 120 . That is, in response to the first gate control signal GCS1, the first gate driver 161 sequentially operates the gate driving voltage Vg by one horizontal period through the left end of the gate line GL formed on the display panel 120. ) can be output. In addition, the second gate driver 162 sequentially operates the gate driving voltage Vg by one horizontal period through the right end of the gate line GL formed on the display panel 120 in response to the second gate control signal GCS2. ) can be output. Accordingly, the thin film transistors connected to each gate line GL are turned on by one horizontal period.

In addition, the gate driving units 161 and 162 may be integrated into one gate driving unit, or may be configured in a gate in panel (GIP) type mounted inside the display panel 120 .

4 is an enlarged view of a portion of the display device shown in FIG. 3;

5 is a diagram illustrating a data driver according to an embodiment of the present invention.

As shown in FIG. 4 , the data driver 180 is composed of a plurality of data driving integrated circuits (ICs) 180-1 to 180-n. The plurality of data driving ICs 180-1 to 180-n are electrically connected through an RC line RCL and a plurality of selection lines SL1 to SLn. Here, the contact points P1 to Pn of the RC line RCL and the plurality of selection lines SL1 to SLn may maintain the same spacing as that of the plurality of data lines DL. This is to delay the switch signals SE1 and SE2 the same as the delay time of the gate driving voltage Vg.

As shown in FIG. 5, the individual data driving IC 180-1 includes a data controller 180-1a, a digital/analog converter (hereinafter referred to as a DAC), an output buffer ( 180-1c) and a switch 180-1d.

The data control unit 180-1a converts the digital image data (RGB) in serial form input from the timing control unit 140 into a parallel form. Subsequently, image data (RGB) in parallel form is sampled and transmitted to the DAC 180-1b.

The DAC 180-1b uses the gamma voltage (GMA) input from the gamma voltage generator (not shown) to provide an analog data voltage (corresponding to the digital image data RGB) transmitted from the data control unit 180-1a. Vdata).

The output buffer 180-1c outputs the data voltage Vdata received from the DAC 180-1d to the switch 180-1d. The output buffer 180-1c serves to prevent signal delay of the data voltage Vdata from an internal resistance component.

The switch 180-1d switches the data voltage Vdata input from the output buffer 180-1c in response to the delay switch signal DSE input through the selection line SL. Here, the switch 180-1d may be composed of a transistor, and due to the characteristics of a general transistor, the switch 180-1d is turned on when the delay switch signal DSE has a turn-on voltage or higher. Therefore, in proportion to the delay time of the delay switch signal DSE, the data voltage Vdata is delayed and output.

Next, a signal transmission process and a data voltage delay process of the display device operating with the above configuration will be described in detail.

6A to 6C are diagrams showing waveforms of gate driving voltages applied to each pixel connected to the second data line, and FIG. 7 describes a delay of the data voltage applied to each pixel connected to the second data line. It is a drawing for

As shown in FIGS. 6A to 6C , the gate driving voltage Vg1 applied to the uppermost pixel connected to the second data line DL2 and the gate driving voltage Vg1 applied to the second pixel connected to the second data line DL2 It can be seen that the voltage Vg2 and the gate driving voltage Vg3 applied to the third pixel connected to the second data line DL2 all have the same waveform. That is, the gate driving voltages applied to the pixels connected to the same data line DL are all equally delayed. This is because the panel load applied to each gate driving voltage (Vg) is the same.

Referring to FIG. 7 , the SE generator 142 of the timing controller generates a switch signal SE in synchronization with the data control signal DCS and outputs it to the RC line RCL. Thereafter, the switch signal SE is delayed according to the delay time of the gate driving voltage Vg in the RC line RCL. Next, the delay switch signal DSE is transmitted to the switch 180-1d of the data driver. The switch 180-1d outputs the data voltage Vdata only when the delay switch signal DSE equal to or higher than the turn-on voltage Von is applied. As a result, the data voltage Vdata is delayed by the delay time td according to the delay time of the gate driving voltage Vg and outputted.

8A to 8C are diagrams showing waveforms of gate driving voltages applied to each pixel connected to the first gate line, and FIG. 9 is a description of the delay of the data voltage applied to each pixel connected to the first gate line. It is a drawing for

8A to 8C , the gate driving voltage Vg1-2 applied to the second pixel connected to the first gate line GL1 is applied to the first pixel connected to the first gate line GL1. It is delayed from the gate driving voltage (Vg1-1). Also, the gate driving voltage Vg1-3 applied to the third pixel connected to the first gate line GL1 is higher than the gate driving voltage Vg1-2 applied to the second pixel connected to the first gate line GL1. Delayed. That is, the longer the transmission distance of the signal applied from the gate drivers 161 and 162 to each pixel PX, the longer the response speed. This is because the panel load increases as the signal transmission distance increases.

Referring to FIG. 9, the delay time of the delay switch signal DSE is delayed according to the delay time of the gate driving voltage Vg. That is, the delay switch signal DSE1-2 at the second contact point P2 is more delayed than the delay switch signal DSE1-1 at the first contact point P1. And, the delay switch signal DSE1-1 at the third contact point P3 is more delayed than the delay switch signal DSE1-2 at the second contact point P2. This is because the panel load increases as the distance between the gate drivers 161 and 162 and the contact points P1 to Pn located at the ends of the selection line SL increases.

Accordingly, the data voltage Vdata applied to each pixel connected to the first gate line is also delayed according to the delay level of the delay switch signal DSE. That is, the delay time of the data voltage Vdata1-2 applied to the second pixel connected to the first gate line is greater than the delay time td1 of the data voltage Vdata1-1 applied to the first pixel connected to the first gate line. (td2) is long. Further, the delay time of the data voltage Vdata1-3 applied to the third pixel connected to the first gate line is greater than the delay time td2 of the data voltage Vdata1-2 applied to the second pixel connected to the first gate line. (td3) is long.

10A and 10B are diagrams illustrating voltage-time graphs of an edge area and a center area of a display panel according to an exemplary embodiment of the present invention.

Here, the edge portion of the display panel refers to a portion of the display panel 120 adjacent to the first and second gate driving units 161 and 162, and the center portion of the display panel refers to the first and second gate driving units 161 and 162. It refers to the central portion of the display panel 120 spaced apart from

Referring to FIG. 10A , it can be seen that the gate driving voltage Vg is hardly delayed and the data voltage Vdata is hardly delayed at the edge portion of the display panel. Therefore, during the turn-on time (ton) of the thin film transistor of each pixel PX, the data voltage Vdata is sufficiently applied to each pixel PX, so that image defects do not occur.

In comparison, referring to FIG. 10B , the gate driving voltage (Vg) is delayed due to the panel load in the center portion of the display panel. Accordingly, it can be seen that the data voltage Vdata is also delayed. In particular, as can be seen in area B (B), during the turn-on time (ton) of the thin film transistor of each pixel (PX), the data voltage (Vdata) is sufficiently applied to each pixel (PX), thereby solving the problem of color mixing. can do.

A method of driving a display device according to an embodiment of the present invention will be described in detail.

11 is a diagram illustrating a display device driving method according to an exemplary embodiment of the present invention.

Referring to FIG. 11 , the display device driving method according to an embodiment of the present invention includes a switch signal transmission step (S100), a delay switch signal transmission step (S200), a data voltage switching step (S300), and a data voltage application step (S400). includes

The switch signal transmission step (S100) is a step in which the switch signals SE1 and SE2 are generated by the SE generator 142 of the timing controller 140 and transmitted to both sides of the RC line RCL.

At this time, the switch signals SE1 and SE2 are delayed through the RC line RCL and supplied to the data driver 180 to delay the data voltage Vdata. At this time, the switch signals SE1 and SE2 must be synchronized with the output timing of the data voltage Vdata. Accordingly, the switch signals SE1 and SE2 may be output in synchronization with the data control signal DCS. More specifically, the data control signal DCS may be synchronized with the source output enable signal SOE for controlling the output of the data driver 180 .

Subsequently, in the delay switch signal transmission step (S200), the switch signals SE1 and SE2 are delayed through the RC line RCL. And, it is a step of transmitting the delay switch signal DSE to the data driver 180 through the selection line SL.

When the switch signals SE1 and SE2 are delayed, the delay time should be equal to the delay time of the gate driving voltage Vg. As can be seen in region B of FIG. 10B, this is to ensure that the data voltage is sufficiently applied to each pixel PX during the turn-on time ton of the thin film transistor of each pixel PX.

Next, in the data voltage switching step (S300), the switch 180-1d of the data driver 180 switches the data voltage Vdata in response to the delay switch signal DSE.

Referring to FIG. 7, the switch 180-1d outputs the data voltage Vdata only when the delay switch signal DSE equal to or higher than the turn-on voltage Von is applied. As a result, the data voltage Vdata is output according to the delay time of the gate driving voltage Vg.

Finally, the data voltage applying step ( S400 ) is a step of applying the switched data voltage Vdata to the plurality of data lines DL. In this way, the delayed data voltage Vdata is applied to the data line DL according to the delay time of the gate driving voltage Vg. Accordingly, the data voltage Vdata is accurately applied to each pixel PX. As a result, the data voltage Vdata to be applied at the turn-on time of the next gate line is not applied during the turn-on time of the corresponding gate line, thereby solving problems of color mixing and image defects.

Although many details have been specifically described in the foregoing description, this should be interpreted as an example of a preferred embodiment rather than limiting the scope of the invention. Therefore, the invention should not be defined according to the described examples, but should be defined according to the scope of the claims and the scope of the claims.

100: display device 120: display panel
140: timing control unit 142: SE generation unit
161, 162: first and second gate driving units
180: data drive unit PX: pixel
DL: data line GL: gate line
RCL: RC line SL: Selection line
SE: switch signal

Claims (12)

a display panel including gate lines, data lines, and RC lines;
a timing control unit generating a switch signal and outputting it to the RC line;
a first gate driver and a second gate driver disposed on both sides of the display panel to output a gate driving voltage to the gate line; and
A data driver synchronized with a delay switch signal delayed from the switch signal through the RC line and outputting a data voltage to the data line;
The data driver includes a plurality of data driver ICs;
Each of the plurality of data driving ICs,
a data control unit that aligns digital image data;
a DAC that converts the digital image data into a data voltage;
an output buffer stably transferring the data voltage to a switch; and
a switch receiving the delay switch signal delayed through the RC line and outputting the data voltage output from the output buffer to the data line of the display panel in response to the delay switch signal;
The RC line is disposed outside the outermost gate line of the display panel in parallel with the gate line, and the delay time of the gate driving voltage applied to the gate line from the first gate driver and the second gate driver Similarly, delaying the switch signal,
The timing controller is connected to both sides of the RC line to transmit the switch signal to both sides of the RC line. delete The method of claim 1, wherein the RC line
A display device disposed on the same layer as the gate line. According to claim 1,
and a plurality of selection lines electrically connecting the RC line and the data driver and transmitting the delay switch signal to the data driver. 5. The method of claim 4, wherein the selection line
A display device having the same arrangement interval as the arrangement interval of the data lines. delete delete The method of claim 1, wherein the timing controller
The display device further comprising a switch signal generator for generating the switch signal. The method of claim 8, wherein the switch signal generator
A display device that simultaneously outputs the switch signal and the data control signal. a display panel including gate lines, data lines, and RC lines; a timing control unit generating a switch signal and outputting it to the RC line; a first gate driver and a second gate driver disposed on both sides of the display panel to output a gate driving voltage to the gate line; and a data driver configured to output a data voltage to the data line in synchronization with a delay switch signal delayed from the switch signal through the RC line,
The data driver includes a plurality of data driver ICs;
Each of the plurality of data driving ICs,
a data control unit that aligns digital image data;
a DAC that converts the digital image data into a data voltage;
an output buffer stably transferring the data voltage to a switch; and
a switch receiving the delay switch signal delayed through the RC line and outputting the data voltage output from the output buffer to the data line of the display panel in response to the delay switch signal;
transmitting a switch signal from the timing controller to the RC line;
transmitting a delayed switch signal delayed from the switch signal to the switch of the driving IC through the RC line; and
outputting the data voltage output from the output buffer to the data line in response to the delay switch signal in the switch of the driving IC;
The RC line is disposed outside the outermost gate line of the display panel in parallel with the gate line, and the delay time of the gate driving voltage applied to the gate line from the first gate driver and the second gate driver Similarly, delaying the switch signal,
The timing controller is connected to both sides of the RC line to transmit the switch signal to both sides of the RC line. 11. The method of claim 10, wherein transmitting the switch signal
and simultaneously outputting, by the timing controller, a data control signal and the switch signal. delete

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