KR102393770B1 - 메모리 비트 셀의 동적 판독 동작에 대한 지연된 키퍼 회로의 누설―인식 활성화 제어 - Google Patents

메모리 비트 셀의 동적 판독 동작에 대한 지연된 키퍼 회로의 누설―인식 활성화 제어 Download PDF

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KR102393770B1
KR102393770B1 KR1020187028226A KR20187028226A KR102393770B1 KR 102393770 B1 KR102393770 B1 KR 102393770B1 KR 1020187028226 A KR1020187028226 A KR 1020187028226A KR 20187028226 A KR20187028226 A KR 20187028226A KR 102393770 B1 KR102393770 B1 KR 102393770B1
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leakage
circuit
nfet
pfet
indicator
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KR20180125490A (ko
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프랑소와즈 이브라힘 아탈라
호안 휴 응우옌
키이스 알렌 바우맨
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Read Only Memory (AREA)
KR1020187028226A 2016-03-30 2017-03-02 메모리 비트 셀의 동적 판독 동작에 대한 지연된 키퍼 회로의 누설―인식 활성화 제어 Active KR102393770B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/085,187 2016-03-30
US15/085,187 US9940992B2 (en) 2016-03-30 2016-03-30 Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell
PCT/US2017/020351 WO2017172230A1 (en) 2016-03-30 2017-03-02 Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell

Publications (2)

Publication Number Publication Date
KR20180125490A KR20180125490A (ko) 2018-11-23
KR102393770B1 true KR102393770B1 (ko) 2022-05-02

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KR1020187028226A Active KR102393770B1 (ko) 2016-03-30 2017-03-02 메모리 비트 셀의 동적 판독 동작에 대한 지연된 키퍼 회로의 누설―인식 활성화 제어

Country Status (8)

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US (1) US9940992B2 (enExample)
EP (1) EP3437101B1 (enExample)
JP (1) JP6949047B2 (enExample)
KR (1) KR102393770B1 (enExample)
CN (1) CN108780658B (enExample)
CA (1) CA3016028C (enExample)
ES (1) ES2897915T3 (enExample)
WO (1) WO2017172230A1 (enExample)

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US10181358B2 (en) * 2016-10-26 2019-01-15 Mediatek Inc. Sense amplifier
US10672439B2 (en) 2018-07-10 2020-06-02 Globalfoundries Inc. Data dependent keeper on global data lines
US12148464B2 (en) * 2021-07-26 2024-11-19 Xilinx, Inc. Current leakage management controller for reading from memory cells
KR20230036255A (ko) * 2021-09-07 2023-03-14 에스케이하이닉스 주식회사 누설 전류를 보상할 수 있는 반도체 집적 회로 및 그 구동 방법
JP2024072439A (ja) * 2022-11-16 2024-05-28 ルネサスエレクトロニクス株式会社 半導体装置

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US20140204687A1 (en) 2013-01-23 2014-07-24 Nvidia Corporation System and method for performing address-based sram access assists
US20150009751A1 (en) 2012-03-26 2015-01-08 Jaydeep P. Kulkarni Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks

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US6894528B2 (en) * 2002-09-17 2005-05-17 Sun Microsystems, Inc. Process monitor based keeper scheme for dynamic circuits
US6844750B2 (en) 2003-03-31 2005-01-18 Intel Corporation Current mirror based multi-channel leakage current monitor circuit and method
US7202704B2 (en) * 2004-09-09 2007-04-10 International Business Machines Corporation Leakage sensing and keeper circuit for proper operation of a dynamic circuit
US7256621B2 (en) * 2005-03-25 2007-08-14 Fujitsu Limited Keeper circuits having dynamic leakage compensation
JP4912016B2 (ja) * 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7551021B2 (en) * 2005-06-22 2009-06-23 Qualcomm Incorporated Low-leakage current sources and active circuits
US7332937B2 (en) 2005-12-28 2008-02-19 Intel Corporation Dynamic logic with adaptive keeper
US20070211517A1 (en) * 2006-03-10 2007-09-13 Freescale Semiconductor, Inc. System and method for operating a memory circuit
US7495971B2 (en) * 2006-04-19 2009-02-24 Infineon Technologies Ag Circuit and a method of determining the resistive state of a resistive memory cell
US7417469B2 (en) 2006-11-13 2008-08-26 International Business Machines Corporation Compensation for leakage current from dynamic storage node variation by the utilization of an automatic self-adaptive keeper
US7474132B2 (en) 2006-12-04 2009-01-06 International Business Machines Corporation Automatic self-adaptive keeper system with current sensor for real-time/online compensation for leakage current variations
US7902878B2 (en) * 2008-04-29 2011-03-08 Qualcomm Incorporated Clock gating system and method
US8214777B2 (en) * 2009-04-07 2012-07-03 International Business Machines Corporation On-chip leakage current modeling and measurement circuit
US7986165B1 (en) * 2010-02-08 2011-07-26 Qualcomm Incorporated Voltage level shifter with dynamic circuit structure having discharge delay tracking
US8644087B2 (en) 2011-07-07 2014-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage-aware keeper for semiconductor memory
US20130106524A1 (en) * 2011-11-01 2013-05-02 Nvidia Corporation System and method for examining leakage impacts
CN102436850B (zh) * 2011-11-30 2014-07-23 中国科学院微电子研究所 检测读取操作对临近单元干扰的方法
US8482316B1 (en) 2012-03-02 2013-07-09 Oracle International Corporation Adaptive timing control circuitry to address leakage
US8988954B2 (en) 2012-09-13 2015-03-24 Arm Limited Memory device and method of performing a read operation within such a memory device
US9460776B2 (en) * 2013-01-23 2016-10-04 Nvidia Corporation SRAM voltage assist
US20140293679A1 (en) * 2013-03-26 2014-10-02 International Business Machines Corporation Management of sram initialization
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US20150009751A1 (en) 2012-03-26 2015-01-08 Jaydeep P. Kulkarni Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks
US20140204687A1 (en) 2013-01-23 2014-07-24 Nvidia Corporation System and method for performing address-based sram access assists

Also Published As

Publication number Publication date
JP2019510332A (ja) 2019-04-11
US9940992B2 (en) 2018-04-10
CA3016028C (en) 2023-10-03
CA3016028A1 (en) 2017-10-05
JP6949047B2 (ja) 2021-10-13
BR112018069888A2 (pt) 2019-02-05
CN108780658A (zh) 2018-11-09
EP3437101B1 (en) 2021-10-13
EP3437101A1 (en) 2019-02-06
WO2017172230A1 (en) 2017-10-05
US20170287550A1 (en) 2017-10-05
ES2897915T3 (es) 2022-03-03
CN108780658B (zh) 2022-05-03
KR20180125490A (ko) 2018-11-23

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