KR102306084B1 - 클럭 디바이더 디바이스 및 그 방법 - Google Patents

클럭 디바이더 디바이스 및 그 방법 Download PDF

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KR102306084B1
KR102306084B1 KR1020197023013A KR20197023013A KR102306084B1 KR 102306084 B1 KR102306084 B1 KR 102306084B1 KR 1020197023013 A KR1020197023013 A KR 1020197023013A KR 20197023013 A KR20197023013 A KR 20197023013A KR 102306084 B1 KR102306084 B1 KR 102306084B1
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frequency
clock
stretch
enable signals
signal
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KR20190113809A (ko
Inventor
디페시 존
스티븐 콤루시
비브호르 미탈
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/30Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G06F1/305Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/324Power saving characterised by the action undertaken by lowering clock frequency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Microcomputers (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
KR1020197023013A 2017-02-24 2018-02-20 클럭 디바이더 디바이스 및 그 방법 Active KR102306084B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/441,613 US10303200B2 (en) 2017-02-24 2017-02-24 Clock divider device and methods thereof
US15/441,613 2017-02-24
PCT/US2018/018718 WO2018156485A1 (en) 2017-02-24 2018-02-20 Clock divider device and methods thereof

Publications (2)

Publication Number Publication Date
KR20190113809A KR20190113809A (ko) 2019-10-08
KR102306084B1 true KR102306084B1 (ko) 2021-09-28

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KR1020197023013A Active KR102306084B1 (ko) 2017-02-24 2018-02-20 클럭 디바이더 디바이스 및 그 방법

Country Status (6)

Country Link
US (1) US10303200B2 (enExample)
EP (1) EP3586214B1 (enExample)
JP (1) JP6905596B2 (enExample)
KR (1) KR102306084B1 (enExample)
CN (1) CN110226148B (enExample)
WO (1) WO2018156485A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2590660B (en) * 2019-12-23 2022-01-05 Graphcore Ltd Reactive droop limiter
US11895588B2 (en) * 2020-08-05 2024-02-06 Analog Devices, Inc. Timing precision maintenance with reduced power during system sleep
US12019499B2 (en) 2021-12-16 2024-06-25 Advanced Micro Devices, Inc. System and method to reduce power down entry and exit latency
CN117409828A (zh) * 2022-07-08 2024-01-16 长鑫存储技术有限公司 一种存储器、控制装置、时钟处理方法和电子设备
EP4325503B1 (en) 2022-07-08 2025-05-21 Changxin Memory Technologies, Inc. Memory, control apparatus, clock processing method, and electronic device
US12061509B2 (en) * 2022-12-15 2024-08-13 International Business Machines Corporation Voltage droop and overshoot management using non-linear slope detection

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040119521A1 (en) 2002-12-20 2004-06-24 Kurd Nasser A. Adaptive frequency clock signal
US20050022042A1 (en) 2003-07-25 2005-01-27 Tam Simo M. Power supply voltage droop compensated clock modulation for microprocessors
US20090138748A1 (en) 2007-11-28 2009-05-28 International Business Machines Corporation Apparatus and method for micro performance tuning of a clocked digital system
US20120169373A1 (en) 2011-01-05 2012-07-05 Texas Instruments Incorporated Glitch free clock switching circuit
US20120187991A1 (en) 2011-01-25 2012-07-26 Advanced Micro Devices, Inc. Clock stretcher for voltage droop mitigation
WO2016105643A1 (en) 2014-12-23 2016-06-30 Intel Corporation Systems and methods for core droop mitigation based on license state
US20170038789A1 (en) 2015-08-03 2017-02-09 Qualcomm Incorporated Power distribution network (pdn) droop/overshoot mitigation

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2959657B2 (ja) 1993-05-13 1999-10-06 キヤノン株式会社 電子機器
JP2000207381A (ja) 1999-01-20 2000-07-28 Mitsubishi Electric Corp マイクロコンピュ―タのリセット装置
US7114038B2 (en) 2001-12-28 2006-09-26 Intel Corporation Method and apparatus for communicating between integrated circuits in a low power mode
US6882238B2 (en) * 2003-03-21 2005-04-19 Intel Corporation Method and apparatus for detecting on-die voltage variations
US7007188B1 (en) 2003-04-29 2006-02-28 Advanced Micro Devices, Inc. Precision bypass clock for high speed testing of a data processor
US7076679B2 (en) 2003-10-06 2006-07-11 Hewlett-Packard Development Company, L.P. System and method for synchronizing multiple variable-frequency clock generators
DE10354215B4 (de) 2003-11-20 2010-02-25 Infineon Technologies Ag Taktregulierungsvorrichtung sowie Schaltungsanordnung
WO2006091826A2 (en) * 2005-02-23 2006-08-31 Multigig, Inc. Low noise divider
JP4492394B2 (ja) 2005-03-08 2010-06-30 株式会社デンソー マイクロコンピュータ
US7570122B2 (en) * 2007-12-22 2009-08-04 Broadcom Corporation Low voltage LOGEN
DE102008061034B3 (de) 2008-12-08 2010-04-08 Fujitsu Siemens Computers Gmbh Anordnung umfassend wenigstens zwei Stromversorgungseinheiten und wenigstens eine Strom verbrauchende Komponente, Computersystem sowie Verfahren zur Steuerung einer Anordnung
US8433944B2 (en) * 2010-04-12 2013-04-30 Qualcomm Incorporated Clock divider system and method with incremental adjustment steps while controlling tolerance in clock duty cycle
US8937511B2 (en) 2011-11-22 2015-01-20 Marvell World Trade Ltd. Frequency scaling of variable speed systems for fast response and power reduction
US9317342B2 (en) 2011-12-23 2016-04-19 Intel Corporation Characterization of within-die variations of many-core processors
US9065440B2 (en) * 2013-01-30 2015-06-23 Altera Corporation Bypassable clocked storage circuitry for dynamic voltage-frequency scaling
US10020931B2 (en) * 2013-03-07 2018-07-10 Intel Corporation Apparatus for dynamically adapting a clock generator with respect to changes in power supply
US8933737B1 (en) * 2013-06-28 2015-01-13 Stmicroelectronics International N.V. System and method for variable frequency clock generation
CN105375917B (zh) * 2013-12-13 2019-01-29 马维尔国际有限公司 分频器
US9798376B2 (en) * 2015-08-03 2017-10-24 Qualcomm Incorporated Power distribution network (PDN) droop/overshoot mitigation
US9915968B2 (en) * 2016-04-19 2018-03-13 Qualcomm Incorporated Systems and methods for adaptive clock design
US10148258B2 (en) * 2016-09-28 2018-12-04 Mellanox Technologies, Ltd. Power supply voltage monitoring and high-resolution adaptive clock stretching circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040119521A1 (en) 2002-12-20 2004-06-24 Kurd Nasser A. Adaptive frequency clock signal
US20050022042A1 (en) 2003-07-25 2005-01-27 Tam Simo M. Power supply voltage droop compensated clock modulation for microprocessors
US20090138748A1 (en) 2007-11-28 2009-05-28 International Business Machines Corporation Apparatus and method for micro performance tuning of a clocked digital system
US20120169373A1 (en) 2011-01-05 2012-07-05 Texas Instruments Incorporated Glitch free clock switching circuit
US20120187991A1 (en) 2011-01-25 2012-07-26 Advanced Micro Devices, Inc. Clock stretcher for voltage droop mitigation
WO2016105643A1 (en) 2014-12-23 2016-06-30 Intel Corporation Systems and methods for core droop mitigation based on license state
US20170038789A1 (en) 2015-08-03 2017-02-09 Qualcomm Incorporated Power distribution network (pdn) droop/overshoot mitigation

Also Published As

Publication number Publication date
WO2018156485A1 (en) 2018-08-30
JP2020510253A (ja) 2020-04-02
KR20190113809A (ko) 2019-10-08
CN110226148A (zh) 2019-09-10
EP3586214A4 (en) 2020-12-16
CN110226148B (zh) 2021-04-09
JP6905596B2 (ja) 2021-07-21
EP3586214B1 (en) 2023-05-31
US20180246557A1 (en) 2018-08-30
EP3586214A1 (en) 2020-01-01
US10303200B2 (en) 2019-05-28

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