KR102296743B1 - Organic light emitting display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to an organic light emitting display device and a method of manufacturing the same, and more particularly, to a gate line transmitting a gate signal and a data line transmitting a data signal on a substrate defining a plurality of pixel regions generated by crossing the data line transmitting the data signal. A display area, a light blocking layer disposed in a first pattern on the substrate corresponding to each pixel area, a buffer layer disposed on the light blocking layer, an activation layer disposed in a second pattern in the pixel area on the buffer layer, and the activation layer It is connected to the light blocking layer through a first contact hole formed by a fourth pattern of a gate positioned on the third pattern, an interlayer insulating layer positioned on the gate, and a fourth pattern of the interlayer insulating layer, and is formed by the fourth pattern. A display device comprising: a source electrode and a drain electrode connected to the activation layer through a second contact hole; a protective layer formed in a fifth pattern on the source electrode and the drain electrode; and a color filter corresponding to each pixel area; to provide.

Description

Organic light emitting display device and method of manufacturing same

The present invention relates to an organic light emitting display device and a method for manufacturing the same.

At least one transistor is disposed in a display panel for a display device such as a liquid crystal display device and an organic light emitting display device for displaying an image.

In particular, the organic light emitting display device, which has been spotlighted as a display device, has advantages of fast response speed, luminous efficiency, luminance, and viewing angle by using an organic light emitting diode (OLED) that emits light by itself.

Each pixel of the organic light emitting diode display includes, in addition to the organic light emitting diode, a data line and a gate line crossing each other, and a transistor having a structure connected thereto.

On the other hand, when external light is introduced into such a transistor, it has a possibility of causing a characteristic change of the transistor, which may cause image non-uniformity.

Therefore, research on blocking light from the outside by forming a light blocking layer on the transistor is being conducted.

Against this background, an object of the present invention is to block external light through a light blocking layer positioned opposite to a transistor, and to remove parasitic capacitance by connecting one electrode constituting the transistor with the light blocking layer.

Another object of the present invention is to reduce a process in connecting one electrode of a transistor and a light blocking layer and to prevent a case in which a pixel electrode is cut due to a step difference in the process of forming the transistor.

In order to achieve the above object, in one aspect, the present invention provides a display area defining a plurality of pixel areas generated by crossing a gate line transmitting a gate signal and a data line transmitting a data signal on a substrate, each of the above A light blocking layer positioned in a first pattern on the substrate corresponding to the pixel region of is connected to the light blocking layer through a first contact hole formed by a fourth pattern of a gate positioned as Provided is a display device including a source electrode and a drain electrode connected to the activation layer, a protective layer formed in a fifth pattern on the source electrode and the drain electrode, and a color filter corresponding to each pixel area.

In another aspect, the present invention provides a display area defining a plurality of pixel areas generated by crossing a gate line transmitting a gate signal and a data line transmitting a data signal on a substrate, and on the substrate corresponding to each pixel area A light blocking layer disposed in a first pattern, a buffer layer disposed on the light blocking layer, an activation layer disposed in a second pattern in the pixel region on the buffer layer, a gate disposed in a third pattern on the activation layer, on the gate A fifth pattern on the source electrode and drain electrode, the source electrode and the drain electrode connected to the activation layer and the light blocking layer through a first contact hole formed in the interlayer insulating layer positioned in the interlayer insulating layer, the fourth pattern of the interlayer insulating layer Provided is a display device including a protective layer formed of , and a color filter corresponding to each pixel area.

In another aspect, the present invention provides a display area defining a plurality of pixel areas generated by crossing a gate line transmitting a gate signal and a data line transmitting a data signal on a substrate to correspond to each pixel area on the substrate Forming a light blocking layer with a first pattern on the light blocking layer, forming a buffer layer on the light blocking layer, forming an activation layer in a second pattern in the pixel area on the buffer layer, in a third pattern on the activation layer Forming a gate, forming an interlayer insulating layer on the gate, forming a first contact hole exposing a portion of the light blocking layer in a fourth pattern in the interlayer insulating layer, and the first contact hole There is provided a method of manufacturing a display device comprising the step of forming a source electrode or a drain electrode in contact with the light blocking layer through the

As described above, according to the present invention, the mask for contacting the light blocking layer and the source/drain electrodes can be reduced by applying the halftone process in forming the contact hole in the interlayer insulating layer.

According to the present invention, it is possible to unify the contact hole in the sensing TR (Sense Transistor) region.

According to the present invention, it is possible to unify the contact hole in the sensing TR (Sense Transistor) region in order to improve the weak spot cluster defect.

1 is a system configuration diagram of a display device 100 to which embodiments are applied.
2A to 2E are process diagrams illustrating a process of forming a light blocking layer and forming a contact hole.
FIG. 3 is a view comparing the process of FIGS. 2A to 2E with the process to be reduced in the present invention.
4A to 4E are process diagrams illustrating a process of forming a contact hole of a light blocking layer and an interlayer insulating layer in one process according to the first embodiment of the present invention.
5A to 5D are views showing detailed cross-sections and configurations of the contact hole of the light blocking layer and the interlayer insulating layer according to the first embodiment of the present invention.
6A to 6E are cross-sectional views illustrating a process of etching the interlayer insulating layer according to the first embodiment of the present invention.
7A to 7C are views showing detailed cross-sections and configurations of a contact hole of a light blocking layer and an interlayer insulating layer according to a second embodiment of the present invention.
8A to 8E are cross-sectional views illustrating a process of etching an interlayer insulating layer according to a second embodiment of the present invention.
9 is a view showing a process process according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a system configuration diagram of a display device 100 to which embodiments are applied.

Referring to FIG. 1 , a display device 100 to which embodiments are applied includes a display panel 110 in which m data lines DL1 to DLm and n gate lines GL1 to GLn are formed, and m data lines. The data driver 120 supplying a data voltage to (DL1 to DLm), the gate driver 130 supplying a scan signal to the n gate lines GL1 to GLn, the data driver 120 and the gate driver 130 ) and a timing controller 140 for controlling the driving timing.

The aforementioned gate driver 130 may be positioned on only one side of the display panel 110 as shown in FIG. 1 or divided into two and positioned on both sides of the display panel 110 according to a driving method.

Also, the gate driving unit 130 may include a plurality of gate driving integrated circuits. The plurality of gate driving integrated circuits may include a tape automated bonding (TAB) method or a chip-on-glass (COG) method. to a bonding pad of the display panel 110 , or may be implemented as a GIP (Gate In Panel) type and directly formed on the display panel 110 , and in some cases, integrated into the display panel 110 . may be formed.

In addition, the data driver 120 may include a plurality of data driving integrated circuits (also referred to as source driving integrated circuits), and the plurality of data driving integrated circuits may include a Tape Automated Bonding (TAB) method or It may be connected to a bonding pad of the display panel 110 in a chip-on-glass (COG) method or may be directly formed on the display panel 110 , and in some cases, may be integrated on the display panel 110 to be formed. may be

The display device 100 to which these embodiments are applied may be a liquid crystal display (LCD) or an organic light emitting display (OLED). However, regardless of the type of the display device 100 , at least one transistor is disposed in each of the plurality of pixels defined in the display panel 110 . Meanwhile, a light shield (LS) may be formed under the transistor, which is formed on the substrate to block light entering from the outside. In addition, when the source/drain electrodes and the light blocking layer are grounded, static electricity is prevented. To this end, it is necessary to form a contact hole connecting the source/drain electrode and the light blocking layer in a process process. The light blocking layer may have a size corresponding to that of the thin film transistor.

2A to 2E are process diagrams illustrating a process of forming a light blocking layer and forming a contact hole.

FIG. 2A is a view in which a light blocking layer 210 is formed corresponding to the thin film transistor. A single mask may be used to define the pattern of the light-blocking layer that blocks light to form the light-blocking layer.

2B is a diagram illustrating a buffer layer coated on the light blocking layer 210 . The buffer layer 220 may be applied to the entirety, and 210a indicates the outline of the light blocking layer 210 formed in FIG. 2A . In addition, a contact hole such as 225 is formed in the buffer layer 220 , and the light blocking layer 210 is exposed through the contact hole 225 . One mask may be used to form the contact hole 225 on the buffer layer 220 .

2C is a diagram illustrating an active layer. A pattern for the activation layer is defined and the activation layer 230 formed through the pattern is formed using a predetermined mask, and during the formation process, the activation layer 230 is in contact with the light blocking layer 210 through the contact hole 225 . .

2D is a view in which a gate is formed on the activation layer. A gate insulating layer (not shown) and a gate 240 are formed. One mask can be used here. Here, only the activation layer under the gate is used as a channel, and the remaining region may be conductive.

2E shows that an inter-layer dielectric 250 is coated on the gate 240, and contact holes 255 and 257 are formed in the applied inter-layer dielectric layer 250 to form the gate 240 or A portion of the activation layer 230 is exposed. Similarly, the previously created contact hole 225 is also maintained in the interlayer insulating layer. One mask can be used in this process.

The contact hole 255 through which the gate 240 is exposed makes contact between the source/drain electrode formed later and the gate 240 , and the contact hole 257 through which the activation layer 230 is exposed is a source/drain electrode formed thereafter. and the activation layer 230 come into contact with each other. That is, after FIG. 2e, the source/drain electrodes are formed, and the color filter and overcoat of R/G/B (Red, Green, Blue), and the passivation layer and the pixel electrode and the bank are formed. proceed with the process.

In the process of FIGS. 2A to 2E , a contact hole exposing the activation layer and a contact hole exposing the light blocking layer are separately used.

In the process of FIGS. 2A to 2E , when the contact hole 225 on the buffer layer 220 for exposing the light blocking layer 210 and the contact hole 255 formed on the interlayer insulating layer 250 are simultaneously formed, the mask is can save

FIG. 3 is a view comparing the process of FIGS. 2A to 2E with the process to be reduced in the present invention. 310 is a mask used when the processes of FIGS. 2A to 2E and subsequent processes are performed. For a process for a thin film transistor, a light shielding layer (Light Shield, L/S) and a contact hole generation (L) of the light shielding layer are used. -CNT), and activation layer formation (ACT), gate insulating layer and gate (Gate/GI), interlayer insulating layer (ILD), source/drain electrode formation (SD) and protective layer (PAS), pixel electrode (PXL) In the process of forming a mask, a total of 8 masks are used. On the other hand, a total of five masks are used for the process for the color filter side: each color (Red, Green, Blue), overcoat (OC), and bank (BANK).

However, when the process of forming the contact hole of the light blocking layer and the process of forming the interlayer insulating layer in 320 corresponding to an embodiment of the present invention are combined into one process and mask as in 325, the manufacturing process can be reduced. . That is, since a separate mask is not used to form the contact hole for exposing the light blocking layer, the process and cost thereof can be reduced. In addition, it is possible to prevent a breakage phenomenon due to a step difference in forming a pixel electrode, which will be described later.

4A to 4E are process diagrams illustrating a process of forming a contact hole of a light blocking layer and an interlayer insulating layer in one process according to the first embodiment of the present invention.

In the first embodiment, a contact hole through which the light blocking layer and the source/drain electrodes are connected is indicated as a first contact hole, and a contact hole through which the activation layer and the source/drain electrodes are connected is indicated as a second contact hole.

4A is a view in which a light blocking layer 410 is formed corresponding to the thin film transistor. In forming the light blocking layer, one mask may be used.

4B is a diagram illustrating a buffer layer 420 coated on the light blocking layer 410 . The buffer layer may be applied to the entirety, and 410a indicates the outline of the light blocking layer 410 formed in FIG. 4A . Unlike FIG. 2B , since there is no process of forming a separate contact hole in the buffer layer 420 , the mask is reduced.

4C is a diagram illustrating an active layer. The activation layer 430 is formed using a predetermined mask. Similarly, in FIG. 4C , a separate contact hole is not formed.

4D is a view in which TGAT is formed on the activation layer. A gate insulating layer (not shown) and a gate 240 are formed. One mask can be used here.

In FIG. 4E , an interlayer insulating layer 450 is applied on the gate 440 , and contact holes 455 and 457 are formed in the applied interlayer insulating layer 450 to form a gate 440 or an activation layer 430 . part of it is exposed. In the same process, a contact hole 425 exposing a portion of the light blocking layer 410 may be formed, and a single mask may be used in this process.

In the contact hole 455 through which the gate 440 is exposed, the source/drain electrode formed later and the gate 440 contact each other, and the contact holes 457a and 457b through which the activation layer 430 are exposed are source/drain electrodes formed later. The drain electrode and the activation layer 430 come into contact. That is, after FIG. 4E , a process of forming source/drain electrodes, R/G/B (Red, Green, Blue) color filters and overcoat layers, and a protective layer, pixel electrodes, and banks is performed. .

In the first embodiment of the present invention, the first contact hole 425 exposes a portion of the light blocking layer 410 , and the second contact hole 457a exposes the activation layer. The first contact hole and the second contact hole are formed in one process using one mask.

5A to 5D are views showing detailed cross-sections and configurations of the contact hole of the light blocking layer and the interlayer insulating layer according to the first embodiment of the present invention.

FIG. 5A is a view showing a cross-section and a region requiring detailed enlargement to be examined in FIG. 4E. A cross-section I-I' of the contact hole 455 formed in the interlayer insulating layer on the gate 440 and a cross-section II-II' of the contact hole 457a formed in the interlayer insulating layer on the activation layer 430 (II-II'); , an enlarged view of the first contact hole 425 of the light blocking layer and the second contact hole 457a through which the activation layer is exposed, and cross-sections thereof.

FIG. 5B is a view showing the structure of a cross-section taken along line I-I' of FIG. 5A.

An interlayer insulating layer 450 is formed on the gate 440 , and a contact hole 455 is formed in the interlayer insulating layer 450 , through which the source/drain electrodes 512 come into contact with the gate 440 . .

FIG. 5C is a view showing the structure of a cross-section taken along line II-II' of FIG. 5A.

An interlayer insulating layer 450 is formed on the activation layer 430 , and a contact hole 457b is formed in the interlayer insulating layer 450 , through which the source/drain electrodes 514 are connected to the activation layer 440 and contact

FIG. 5D is a view showing an enlarged structure of 501 of FIG. 5A . In addition to 501, the structure after the source/drain electrodes, the protective layer, and the pixel electrode are formed is shown.

The source/drain electrodes 518 formed on the interlayer insulating layer are formed in the interlayer insulating layer, and come into contact with the activation layer 430 through the second contact hole 457a formed by the half tone of the mask. do. In addition, the source/drain electrodes 518 are formed in the interlayer insulating layer and contact the light blocking layer 410 through the first contact hole 425 formed by the full tone of the mask.

Meanwhile, the passivation layer contact hole 555 formed in the passivation layer partially overlaps the second contact hole 457a.

FIG. 5E is a cross-sectional view taken along line III-III′ of FIG. 5D .

As shown in FIG. 5D , a portion of the second contact hole 457a and the protective layer contact hole 555 formed in the protective layer overlap each other, and a first contact hole 425 is formed adjacent thereto.

6A to 6E are cross-sectional views illustrating a process of etching the interlayer insulating layer according to the first embodiment of the present invention. In the process of etching the interlayer insulating layer, the first contact hole 425 and the second contact hole 457a described above are formed using a single mask.

6A is a state in which a mask is applied on the interlayer insulating layer. A mask is formed with the photoresist 600 , the photoresist 600 is formed with halftones in regions 611 and 612 on the activation layer 430 , and the photoresist 600 is formed on the region 620 on the light blocking layer 410 . has been removed An activation layer 430 , a gate insulating layer 435 , and a gate 440 are formed on the buffer 420 , and an interlayer insulating layer 450 is applied thereon.

In FIG. 6B , the first contact hole 425 of the interlayer insulating layer is partially formed by etching the region 620 in which the photoresist 600 is not formed based on the mask.

6C shows a state in which the photoresists 611 and 612, which are regions where the photoresist 600 is formed with halftones, are removed. The height of the entire photoresist 600 is also lowered. In FIG. 6D , the second contact hole 457a is formed by etching while the photoresist 600 of the halftone region is removed, and the first contact hole 425 is completed at the same time.

6E is a form in which the photoresist is completely removed. A first contact hole 425 and a second contact hole 457a are formed, and then a source/drain electrode may be formed, and the source/drain electrode and the light blocking layer are connected through the first contact hole 425 . , the source/drain electrodes and the activation layer are connected through the second contact hole 457a.

The display device presented in the first embodiment of FIGS. 4A to 6E is as follows. A display area defining a plurality of pixel areas generated by crossing a gate line transmitting a gate signal and a data line transmitting a data signal on the substrate, and a light blocking area positioned in a first pattern on the substrate corresponding to each pixel area layer, a buffer layer positioned on the light blocking layer, an activation layer positioned in a second pattern in the pixel region on the buffer layer, a gate positioned in a third pattern on the activation layer, and an interlayer insulating layer positioned on the gate includes It also includes a source electrode and a drain electrode connected to the light blocking layer through a first contact hole formed in a fourth pattern of the interlayer insulating layer and connected to the activation layer through a second contact hole formed in the fourth pattern, , a protective layer formed in a fifth pattern on the source electrode and the drain electrode, and a color filter corresponding to each of the pixel areas.

Here, a protective layer contact hole partially overlapping the second contact hole is positioned in the protective layer, and in more detail, the first embodiment is a coplanar in which the gate wiring and the source electrode and the drain electrode are positioned on the activation layer. It can be applied to the structure, but is not limited thereto.

7A to 7C are views showing detailed cross-sections and configurations of a contact hole of a light blocking layer and an interlayer insulating layer according to a second embodiment of the present invention.

7A is a diagram illustrating a structure in which source/drain electrodes are connected to an activation layer and a light blocking layer using a single contact hole according to a second embodiment of the present invention.

After the process of FIGS. 4A to 4D , in the process of applying and etching the interlayer insulating layer, a mask can be used to form them as one contact hole 725 , unlike 457a and 425 of FIG. 4E , respectively. have. Since the other regions are the same as those of FIGS. 4E and 5A , the region 701 in which the contact hole is formed is enlarged as shown in FIG. 7B .

In the second embodiment of the present invention, the first contact hole 725 exposes the light blocking layer 410 and the activation layer 430 . The first contact hole 725 is formed in one process using one mask. Other than that, the contact hole 457b exposing the activation layer 430 without exposing the light blocking layer 410 and the contact hole 455 exposing the gate 440 are the same as those of the first embodiment, and thus descriptions will be omitted. .

FIG. 7B is an enlarged view of area 701 of FIG. 7A .

FIG. 7B is a view showing an enlarged structure of 701 of FIG. 7A . In addition to 701, the structure after the source/drain electrodes, the protective layer, and the pixel electrode are formed is shown.

The source/drain electrodes 718 formed on the interlayer insulating layer are formed in the interlayer insulating layer, and the activation layer 430 and the light blocking layer are formed through the first contact hole 725 formed by the full tone of the mask. (410) is connected.

Meanwhile, the passivation layer contact hole 755 formed in the passivation layer partially overlaps the first contact hole 725 .

FIG. 7C is a cross-sectional view taken along line IV-IV' of FIG. 7B.

As shown in FIG. 7C , a partial region of the first contact hole 425 and the passivation layer contact hole 755 formed in the passivation layer overlaps.

8A to 8E are cross-sectional views illustrating a process of etching an interlayer insulating layer according to a second embodiment of the present invention. In the process of etching the interlayer insulating layer, the first contact hole 725 described above is formed using a single mask.

8A is a state in which a mask is applied on the interlayer insulating layer. A mask is formed with the photoresist 800 , the photoresist 800 is formed as a halftone in the region 811 on the activation layer 430 , and the photoresist is formed in the region 820 on the activation layer 430 and the light blocking layer 410 . (800) has been removed. An activation layer 430 , a gate insulating layer 435 , and a gate 440 are formed on the buffer 420 , and an interlayer insulating layer 750 is applied thereon.

In FIG. 8B , the first contact hole 725 of the interlayer insulating layer is partially formed by etching the region 820 in which the photoresist 800 is not formed based on the mask.

FIG. 8C shows a state in which the photoresist of 811, which is a region where the photoresist 800 is formed with halftones, is removed. The height of the entire photoresist 800 is also lowered. In FIG. 8D , a contact hole not connected to the light blocking layer is formed by etching while the photoresist 800 in the halftone region is removed, and a first contact hole 725 is completed at the same time.

8E is a form in which the photoresist is completely removed. A first contact hole 725 is formed, and then a source/drain electrode may be formed, and the source/drain electrode, the light blocking layer 410 and the activation layer 430 are connected through the first contact hole 725 . do.

A second embodiment of the present invention will be described as follows. A light blocking layer positioned in a first pattern on the substrate to correspond to each pixel area in a display area defining a plurality of pixel areas generated by crossing a gate line transmitting a gate signal and a data line transmitting a data signal on the substrate , a buffer layer positioned on the light blocking layer, an activation layer positioned in a second pattern in the pixel region on the buffer layer, a gate positioned in a third pattern on the activation layer, and an interlayer insulating layer positioned on the gate do. In addition, a protective layer formed in a fifth pattern on the source electrode and the drain electrode connected to the activation layer and the light blocking layer through the first contact hole formed in the fourth pattern of the interlayer insulating layer and the source electrode and the drain electrode, and and a color filter corresponding to each pixel area. In particular, a passivation layer contact hole partially overlapping the first contact hole may be located in the passivation layer. In more detail, the second embodiment may be applied to a coplanar structure in which the gate wiring and the source electrode and the drain electrode are positioned on the activation layer, but is not limited thereto.

When the first and second embodiments are applied, the mask for contacting the light blocking layer and the source/drain electrodes can be reduced as shown in FIG. 3 by applying the halftone process in forming the contact hole in the interlayer insulating layer, and sensing It is possible to unify the contact hole in the TR (Sense Transistor) area.

In addition, as shown in FIG. 3, the mask on the substrate, which is a process for thin film transistors, is reduced (8 masks to 7 masks), and the process of forming the contact hole of the light blocking layer is replaced with the halftone process of the interlayer insulating layer. can In addition, it is possible to unify the contact hole in the sensing TR (Sense Transistor) region to improve the weak spot cluster defect that occurs when 7 masks are applied.

In particular, when the second exemplary embodiment is applied, the second contact hole 457a of the first exemplary embodiment is formed steeply, so that a step difference is abruptly generated, and the pixel electrode to be formed in the second contact hole 457a may be cut off. That is, when dry etching is performed on the hole of the interlayer insulating layer, the pixel electrode may be disconnected due to a change in taper due to wet etching caused by byproducts and seams in the protective layer. This creates a swarm of weak spots. Therefore, when the second embodiment is applied, the group of weak spots can be improved by unifying the contact holes.

Accordingly, the first embodiment reduces the process, and the second embodiment provides the effect of reducing both the process and the defect.

9 is a view showing a process process according to an embodiment of the present invention.

A process of forming a light blocking layer corresponding to the pixel area and forming a contact hole thereof in a display area defining a plurality of pixel areas generated by crossing a gate line transmitting a gate signal and a data line transmitting a data signal on a substrate is composed

First, a substrate is prepared (S910). Next, a light blocking layer is formed in a first pattern on the substrate corresponding to each pixel area ( S920 ). Thereafter, a buffer layer is formed on the light blocking layer (S930). In this process, a contact hole exposing the light blocking layer is not formed in the buffer layer. Then, an activation layer is formed in a second pattern in the pixel area on the buffer layer (S940). Thereafter, a gate is formed in a third pattern on the activation layer (S950). An interlayer insulating layer is formed on the gate (S960). A first contact hole exposing a portion of the light blocking layer is formed in the interlayer insulating layer in a fourth pattern (S970). Then, a source electrode or a drain electrode in contact with the light blocking layer is formed through the formed first contact hole ( S980 ).

In the above process of forming the first contact hole ( S970 ), the first contact hole may be formed to expose a portion of the activation layer. and

In the process of forming the source electrode or the drain electrode ( S980 ), the source electrode or the drain electrode in contact with the activation layer may be formed through the first contact hole. In addition, in the second embodiment, after the source electrode or drain is formed, a protective layer including a protective layer contact hole partially overlapping the first contact hole and exposing a part of the source electrode or drain electrode may be formed. This has been described previously in the second embodiment and FIGS. 7A to 8E .

Meanwhile, in the first embodiment, the first contact hole and the second contact hole are separately formed. In the process of forming the first contact hole ( S970 ), a part of the activation layer is exposed and the first contact hole is separated from the first contact hole. Two contact holes can be formed.

In the first embodiment, after the source electrode or the drain is formed, a protective layer contact hole partially overlapping the second contact hole and exposing a part of the source electrode or the drain electrode may be included.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine the configuration within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: organic light emitting display device 110: display panel
120: data driver 130: gate driver
140: timing controller 210, 410: light blocking layer
220, 420: buffer layer 230, 430: activation layer
240, 440: gates 425, 725: first contact hole
457a: second contact hole 555, 755: protective layer contact hole

Claims (11)

a display area defining a plurality of pixel areas formed by crossing a gate line transmitting a gate signal and a data line transmitting a data signal on the substrate;
a light blocking layer positioned in a first pattern on the substrate to correspond to each pixel area;
a buffer layer positioned on the light blocking layer;
an activation layer positioned in a second pattern in the pixel area on the buffer layer;
a gate positioned in a third pattern on the activation layer;
an interlayer insulating layer positioned on the gate and having first contact holes of a fourth pattern;
a source electrode and a drain electrode positioned on the interlayer insulating layer;
a protective layer partially overlapping the first contact hole and formed in a fifth pattern on the source electrode and the drain electrode;
a pixel electrode formed on the passivation layer; and
a color filter corresponding to each pixel area;
one of the source electrode and the drain electrode is connected to the light blocking layer and the activation layer through the first contact hole;
The first contact hole has a first step that is the thickness of the interlayer insulating layer, a second step that is the sum of the thicknesses of the activation layer and the buffer layer, and a third step that is the sum of the thicknesses of the buffer layer and the interlayer insulating layer,
The first contact hole is located in one region from which the interlayer insulating layer is removed,
In the one region, both a first region from which the interlayer insulating layer is removed on the activation layer and a second region from which the buffer layer and the interlayer insulating layer are removed from the light blocking layer exist;
At least a portion of the passivation layer is removed, and the passivation layer contact hole from which at least a portion of the passivation layer is removed overlaps the first contact hole in the first region;
In the first region, the activation layer is in contact with the one electrode and is electrically connected to the pixel electrode through the one electrode,
The one electrode and the pixel electrode extend from the first region to the second region, respectively, the light blocking layer in the second region contacts the one electrode, and the one of the one of the second region The protective layer and the pixel electrode are positioned on the electrode of
Both the upper surface of the one electrode and the upper surface of the pixel electrode have a step difference in the first region and the second region;
The upper surface of the passivation layer has a step difference in the second region.
delete According to claim 1,
and a coplanar structure in which the gate wiring and the source and drain electrodes are positioned on the activation layer.
delete delete delete In a display area defining a plurality of pixel areas generated by crossing a gate line transmitting a gate signal and a data line transmitting a data signal on the substrate.
forming a light blocking layer in a first pattern on a substrate corresponding to each of the pixel areas;
forming a buffer layer on the light blocking layer;
forming an activation layer in a second pattern in the pixel area on the buffer layer;
forming a gate in a third pattern on the activation layer;
forming an interlayer insulating layer on the gate;
forming a first contact hole exposing a portion of the light blocking layer and the activation layer in a fourth pattern in the interlayer insulating layer;
forming a source electrode or a drain electrode in contact with the light blocking layer through the first contact hole;
forming a protective layer after forming the source electrode and the drain electrode; and
forming a pixel electrode on the protective layer;
The first contact hole has a first step corresponding to the thickness of the interlayer insulating layer, a second step corresponding to the sum of the thicknesses of the activation layer and the buffer layer, and the sum of the thicknesses of the buffer layer and the interlayer insulating layer There is a third step to
The first contact hole is located in one region from which the interlayer insulating layer is removed,
In the one region, both a first region from which the interlayer insulating layer is removed on the activation layer and a second region from which the buffer layer and the interlayer insulating layer are removed from the light blocking layer exist;
at least a portion of the passivation layer is removed, and the passivation layer contact hole from which at least a portion of the passivation layer is removed overlaps the first contact hole in the first region;
In the first region, the activation layer is in contact with any one of the source electrode and the drain electrode, and is electrically connected to the pixel electrode through the one electrode,
The one electrode and the pixel electrode extend from the first region to the second region, respectively, the light blocking layer in the second region contacts the one electrode, and the one of the one of the second region The protective layer and the pixel electrode are positioned on the electrode of
Both the upper surface of the one electrode and the upper surface of the pixel electrode have a step difference in the first region and the second region;
A method of manufacturing a display device in which the upper surface of the passivation layer has a step in the second region.
8. The method of claim 7,
The step of forming the first contact hole
and forming the first contact hole to expose a portion of the activation layer;
The step of forming the source electrode or the drain electrode is
and forming the source electrode or the drain electrode in contact with the activation layer through the first contact hole.
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