JP2010039413A - Display, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display capable of restraining a light leakage current from being generated, while reducing the generation of a parasitic capacitance between a light shielding layer and a gate electrode, in the display including a thin film transistor having bottom gate structure. <P>SOLUTION: The display includes a substrate laminated sequentially with the light shielding layer (40) for restraining a light from get incident into a semiconductor layer, a first insulating film (31), the gate electrode (22) of the thin film transistor, a second insulating film (32), and the semiconductor layer (21). The light shielding layer (40) is formed not to overlap at least one part of the gate electrode (22) with the light shielding layer (40) via the first insulating film (31). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device that performs display control of a pixel using a thin film transistor (TFT) and a manufacturing method thereof.

  For example, some display devices such as a liquid crystal display device perform display control of each pixel by an active matrix method using a thin film transistor. In such a display device, a plurality of scanning signal lines and a plurality of video signal lines are arranged on a substrate (hereinafter referred to as a TFT substrate) so as to three-dimensionally cross each other, and an intersection of the scanning signal lines and the video signal lines. Each corresponds to a pixel of the display device. The scanning signal line is connected to the gate electrode of the thin film transistor, and the data signal line is connected to either the drain electrode or the source electrode of the thin film transistor (hereinafter referred to as the drain electrode). In addition, a pixel electrode is connected to an electrode that is not connected to the video signal line (hereinafter referred to as a source electrode). When a voltage is applied to the scanning signal line and the video signal line corresponding to the pixel to be controlled for display, the voltage is applied to the corresponding pixel electrode via the thin film transistor functioning as a switch element, and the display control of the pixel is performed. Is called.

In the thin film transistor used for the TFT substrate, when light is incident on the semiconductor layer, a light leakage current is generated, and as a result, the display quality of the display device may deteriorate. For example, in a thin film transistor having an LDD (Lightly Doped Drain) structure, when light is irradiated to a low-concentration impurity region, a light leakage current is generated due to the photoelectric conversion effect of polysilicon. In this regard, Patent Document 1 discloses that in a thin film transistor having a top gate structure, a conductive light-shielding layer containing a metal is provided below the semiconductor layer in order to suppress light such as backlight from entering the semiconductor layer. Is disclosed.
JP 2008-40399 A

  However, since Patent Document 1 relates to a thin film transistor having a top gate structure, if the technique described in Patent Document 1 is applied as it is to a thin film transistor having a bottom gate structure, inconvenience occurs. FIG. 19 shows an example where the technique described in Patent Document 1 is applied as it is to a thin film transistor having a bottom gate structure. In the example shown in FIG. 19, a light shielding layer 40, a protective insulating film 31, a gate electrode 22, a gate insulating film 32, a semiconductor layer 21, an interlayer insulating film 33, a conductor layer, and a protective insulating film 34 are sequentially formed on a glass substrate 30. Are stacked. Here, the conductor layer is a layer formed including the drain electrode 23 and the source electrode 24. The semiconductor layer 21 includes a channel region 21a, a low concentration drain region 21b, a low concentration source region 21c, a high concentration drain region 21d, and a high concentration source region 21e. The light shielding layer 40 includes a metal, and is formed so as to cover the semiconductor layer 21 when viewed from the glass substrate 30 side. The light shielding layer 40 shields the semiconductor layer 21 from incident light from the glass substrate 30 side. However, in the thin film transistor as illustrated in FIG. 19, parasitic capacitance is generated between the light shielding layer 40 and the gate electrode 22, and the switching operation of the thin film transistor may be hindered by the parasitic capacitance.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device including a thin film transistor having a bottom gate structure while reducing generation of parasitic capacitance between a light shielding layer and a gate electrode. An object of the present invention is to provide a display device capable of suppressing the occurrence of leakage current and a manufacturing method thereof.

  In order to solve the above problems, a display device according to the present invention includes a light-shielding layer for suppressing incidence of light on a semiconductor layer, a first insulating film, a gate electrode of a thin film transistor, a second insulating film, The semiconductor layer includes a substrate that is sequentially stacked, and the light shielding layer is formed so that at least a part of the gate electrode does not overlap with the light shielding layer via the first insulating film. And

  In one embodiment of the present invention, the light shielding layer includes an end portion of the gate electrode that overlaps an end portion of the light shielding layer with the first insulating film interposed therebetween, and the gate electrode is the end portion of the light shielding layer. Other portions may be formed so as not to overlap with the first insulating film.

  In one embodiment of the present invention, the light shielding layer may be electrically connected to a source electrode or a drain electrode of the thin film transistor.

  In one embodiment of the present invention, the light shielding layer may be formed as a conductor layer on which a source electrode or a drain electrode of the thin film transistor is formed.

  In addition, a method for manufacturing a display device according to the present invention includes a light shielding layer for suppressing light from entering a semiconductor layer, a first insulating film, a gate electrode of a thin film transistor, a second insulating film, and the semiconductor layer. And a first step of forming the light shielding layer on the substrate, and the first insulating film on the substrate on which the light shielding layer is formed. And a third step of forming the gate electrode on the substrate on which the first insulating film is formed. In the first step and the third step, the light shielding layer and The gate electrode is formed so that at least a part of the gate electrode does not overlap with the light shielding layer via the first insulating film.

  According to the present invention, in a display device including a thin film transistor having a bottom gate structure, it is possible to suppress generation of light leakage current while reducing generation of parasitic capacitance between the light shielding layer and the gate electrode. .

  Hereinafter, examples of embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, an example in which the present invention is applied to a so-called IPS (In Plane Switching) type liquid crystal display device will be described.

[First Embodiment]
The display device according to the present embodiment includes a TFT substrate on which a scanning signal line, a video signal line, a thin film transistor, a pixel electrode, and a common electrode are formed, a filter substrate provided with a color filter facing the TFT substrate, And a liquid crystal material sealed in a region sandwiched between both substrates. The TFT substrate and the filter substrate are both glass substrates.

  FIG. 1 is a circuit diagram showing a schematic circuit configuration of a scanning signal line 12, a video signal line 13, a thin film transistor 20, a pixel electrode 14, a common signal line 15, and a common electrode 16 mounted on a TFT substrate. FIG. 2 is a plan view of one pixel region of the TFT substrate.

  As shown in these drawings, a plurality of scanning signal lines 12 parallel to each other are arranged on the TFT substrate. Further, the plurality of video signal lines 13 are arranged so as to intersect with each of the plurality of scanning signal lines 12 so as to be substantially orthogonal to each other when viewed in parallel and in a plane. Each of the scanning signal lines 12 and the video signal lines 13 divides pixels arranged in a grid pattern, and each of the locations where the scanning signal lines 12 and the video signal lines 13 intersect is a display according to the present embodiment. Corresponds to the pixel of the device.

  In each of a plurality of pixel regions partitioned by the scanning signal line 12 and the video signal line 13, a thin film transistor 20 for performing display control of the pixel is formed. A gate electrode 22 of the thin film transistor 20 is connected to the scanning signal line 12. The drain electrode 23 is connected to the video signal line 13, and the source electrode 24 is connected to the pixel electrode 14. On the other hand, the common electrode 16 corresponding to each pixel electrode 14 is connected to one of a plurality of common signal lines 15 arranged in parallel with the scanning signal line 12.

  A voltage is selectively applied to the scanning signal line 12 at every predetermined timing by the scanning signal line driving circuit 10. In addition, a voltage is selectively applied to the video signal line 13 at every predetermined timing by the video signal line driving circuit 11. In this way, on / off of the thin film transistor 20 corresponding to the pixel electrode to be subjected to display control is controlled, and a voltage is applied to the pixel electrode 14 of the pixel to be displayed through the thin film transistor 20. Thereby, the display device according to the present embodiment controls the liquid crystal molecules by a horizontal electric field generated between the pixel electrode 14 and the common electrode 16 to perform display control for each pixel. Here, each of the pixel electrode 14 and the common electrode 16 is a transparent electrode film, and is arranged such that at least a part thereof overlaps with each other when viewed in a plan view.

  FIG. 3 is an enlarged plan view showing a portion where the thin film transistor 20 is formed on the TFT substrate in FIG. FIG. 4 is a partial cross-sectional view showing a cross-sectional state of the TFT substrate taken along line IV-IV in FIG.

  As shown in these drawings, a light shielding layer 40, a protective insulating film 31 (first insulating film), a gate electrode 22, a gate insulating film 32 (second insulating film), a semiconductor layer 21, and an interlayer are formed on a glass substrate 30. An insulating film 33, a conductor layer, and a protective insulating film 34 are sequentially stacked. Here, the conductor layer is a layer including the drain electrode 23, the source electrode 24, and the video signal line 13. The thin film transistor 20 has a bottom gate structure in which a gate insulating film 32 and a semiconductor layer 21 are stacked on a gate electrode 22.

  The semiconductor layer 21 is made of polysilicon, for example, and has an LDD structure. That is, the semiconductor layer 21 includes a channel region 21a, a low concentration drain region 21b, a low concentration source region 21c, a high concentration drain region 21d, and a high concentration source region 21e. The low concentration drain region 21b, the low concentration source region 21c, the high concentration drain region 21d, and the high concentration source region 21e are impurity regions in which impurities are contained in the polysilicon layer. The low concentration drain region 21b and the low concentration source region 21c are regions having a lower impurity concentration than the high concentration drain region 21d and the high concentration source region 21e. The low concentration drain region 21b is a drain side low concentration impurity region, and the high concentration drain region 21d is a drain side high concentration impurity region. The low concentration source region 21c is a low concentration impurity region on the source side, and the high concentration source region 21e is a high concentration impurity region on the drain side.

  The channel region 21 a is formed so as to overlap the gate electrode 22 with the gate insulating film 32 interposed therebetween. The high-concentration drain region 21d and the high-concentration source region 21e are formed so as to be line symmetric with respect to the extending direction of the gate electrode 22 with respect to the channel region 21a. The low concentration drain region 21b is formed between the channel region 21a and the high concentration drain region 21d, and the low concentration source region 21c is formed between the channel region 21a and the high concentration source region 21e. With such an impurity region, off current that flows when the thin film transistor 20 is in an off state is reduced, and a decrease in on current that flows when the thin film transistor 20 is in an on state is improved.

  The drain electrode 23 is electrically connected to the high concentration drain region 21 d through a contact hole 35 that penetrates the interlayer insulating film 33. Similarly, the source electrode 24 is electrically connected to the high concentration source region 21 e through a contact hole 36 that penetrates the interlayer insulating film 33.

  The light shielding layer 40 includes at least one metal such as titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), aluminum (Al), or tantalum (Ta), and has conductivity. is doing. The light shielding layer 40 may be formed of a single metal or may be formed of an alloy. Alternatively, the light shielding layer 40 may have a laminated structure of these metals. As shown in FIGS. 3 and 4, the light shielding layer 40 includes a drain side light shielding layer 41, a source side light shielding layer 42, and a connection portion 43 that connects the drain side light shielding layer 41 and the source side light shielding layer 42. .

  In the present embodiment, as shown in FIGS. 3 and 4, the light shielding layer 40 is not formed below the gate electrode 22. That is, the light shielding layer 40 is formed so that the gate electrode 22 does not overlap the light shielding layer 40 via the protective insulating film 31.

  The drain side light shielding layer 41 is formed below the low concentration drain region 21b and the high concentration drain region 21d. The drain side light shielding layer 41 is formed so as to cover the low concentration drain region 21b and the high concentration drain region 21d when viewed from the glass substrate 30 side. The drain side light shielding layer 41 is formed so that one end 41 a of the drain side light shielding layer 41 is in contact with one side edge 22 a of the gate electrode 22 when viewed in a plan view. That is, there is no gap between the drain-side light shielding layer 41 and the gate electrode 22 when viewed in plan.

  On the other hand, the source-side light shielding layer 42 is formed under the low-concentration source region 21c and the high-concentration source region 21e. The source-side light shielding layer 42 is formed so as to cover the low-concentration source region 21c and the high-concentration source region 21e when viewed from the glass substrate 30 side. Further, the source-side light shielding layer 42 is formed so that one end 42 a of the source-side light shielding layer 42 is in contact with one side edge 22 b of the gate electrode 22 when viewed in plan. That is, there is no gap between the source-side light shielding layer 42 and the gate electrode 22 when viewed in plan.

  In the example illustrated in FIG. 3, the light shielding layer 40 is integrally formed by the connection portion 43, but the connection portion 43 may not be provided. That is, the light shielding layer 40 may be formed separately for the drain side light shielding layer 41 and the source side light shielding layer 42.

  According to the present embodiment, the gate electrode 22 and the light shielding layer 40 are formed so that the semiconductor layer 21 is covered with the gate electrode 22 and the light shielding layer 40 when viewed from the glass substrate 30 side. Incidence of light from the 30 side to the semiconductor layer 21 is suppressed by the gate electrode 22 and the light shielding layer 40. As a result, generation of light leakage current is suppressed. Furthermore, according to the present embodiment, the gate electrode 22 and the light shielding layer 40 are formed so that the gate electrode 22 does not overlap the light shielding layer 40 with the protective insulating film 31 interposed therebetween. Generation of parasitic capacitance with the layer 40 is suppressed.

  Here, an example of a method for manufacturing the TFT substrate as described above will be described. FIGS. 5A to 5C are views for explaining the manufacturing method, and are partial cross-sectional views showing a cross-sectional state of the TFT substrate at the same location as FIG.

  First, the light shielding layer 40 is formed on the substrate surface of the glass substrate 30 by photolithography. Specifically, a film of a material constituting the light shielding layer 40 is formed on the glass substrate 30, and a resist material film (resist film) is laminated thereon. Then, the resist film is processed into a pattern corresponding to the shape of the light shielding layer 40 by exposure and development, and the light shielding layer 40 is formed by performing etching using the processed resist film as a mask. Thereafter, the remaining resist film is removed. In this case, the mask pattern for exposing the resist film is set so that the gate electrode 22 formed in the subsequent process does not overlap the light shielding layer 40 via the protective insulating film 31. FIG. 5A shows the state of the cross section of the TFT substrate at this stage.

  Next, a film of a material forming the protective insulating film 31 and a film of a material forming the gate electrode 22 are sequentially stacked in this order on the substrate surface of the TFT substrate in that state. For example, silicon nitride is used as the material of the protective insulating film 31. Thereafter, the gate electrode 22 is formed by photolithography. That is, a resist film is laminated on the material film constituting the gate electrode 22. Then, the resist film is processed into a pattern corresponding to the shape of the gate electrode 22 by exposure and development, and the gate electrode 22 is formed by performing etching using the processed resist film as a mask. In this case, the mask pattern for exposing the resist film is set so that the gate electrode 22 does not overlap the light shielding layer 40 via the protective insulating film 31. FIG. 5B shows a cross-sectional state of the TFT substrate at this stage.

  Next, a film of a material constituting the gate insulating film 32 and an amorphous silicon film are sequentially laminated in this order on the substrate surface of the TFT substrate in that state. Then, an amorphous silicon film is converted into a polysilicon film by annealing. Note that a polysilicon film may be directly formed on the gate insulating film 32 by using a low pressure CVD method or the like. Thereafter, the semiconductor layer 21 is formed by photolithography. That is, a resist film is formed on the polysilicon film. Then, the resist film is processed into a pattern corresponding to the shape of the semiconductor layer 21 by exposure and development, and the semiconductor layer 21 is formed by performing etching using the processed resist film as a mask.

  Next, a film of a material constituting the interlayer insulating film 33 is laminated on the substrate surface of the TFT substrate in that state. Thereafter, an impurity region is formed in the semiconductor layer 21 by masking with a resist material so as to cover the portion of the semiconductor layer 21 located on the gate electrode 22 and implanting impurities at a low concentration. Further, the semiconductor layer 21 is masked with a resist material so as to cover the portion of the semiconductor layer 21 located on the gate electrode 22 and its peripheral portion, and impurities are implanted at a high concentration, whereby the high concentration drain region 21d and the high concentration are formed in the semiconductor layer 21. A source region 21e is formed. FIG. 5C shows the state of the cross section of the TFT substrate at this stage.

  Next, after forming contact holes 35 and 36 penetrating the interlayer insulating film 33, the drain electrode 23 and the source electrode 24 are formed. The drain electrode 23 and the source electrode 24 are formed at positions corresponding to the contact holes 35 and 36. The drain electrode 23 and the source electrode 24 are also formed by photolithography. Further, in this state, the protective insulating film 34 is formed, and the TFT substrate is in the state shown in FIG.

[Second Embodiment]
The display device according to the second embodiment basically has the same configuration as that of the first embodiment (see FIGS. 1 and 2). FIG. 6 is an enlarged plan view showing a portion where the thin film transistor 20 is formed on the TFT substrate in FIG. 2, and corresponds to FIG. 3 in the first embodiment. FIG. 7 is a partial cross-sectional view showing the state of the cross section of the TFT substrate taken along the line VII-VII in FIG. 6, and corresponds to FIG. 4 in the first embodiment.

  The display device according to the present embodiment is different from the first embodiment in that wirings 50 and 51 are formed. The wiring 50 is electrically connected to the light shielding layer 40 (drain side light shielding layer 41) through a contact hole 52 that penetrates the protective insulating film 31. Similarly, the wiring 51 is electrically connected to the light shielding layer 40 (source side light shielding layer 42) through a contact hole 53 that penetrates the protective insulating film 31. The other ends of the wirings 50 and 51 connected to the light shielding layer 40 are connected to a constant potential source. For example, the wirings 50 and 51 are grounded.

  Also in the present embodiment, similarly to the first embodiment, incidence of light from the glass substrate 30 side on the semiconductor layer 21 is suppressed by the gate electrode 22 and the light shielding layer 40. As a result, generation of light leakage current is suppressed. Also in this embodiment, as in the first embodiment, the generation of parasitic capacitance between the gate electrode 22 and the light shielding layer 40 is suppressed.

  Incidentally, when the potential of the light shielding layer 40 is not stable, the operation of the thin film transistor 20 may become unstable due to the potential fluctuation of the light shielding layer 40. As a result, the quality of the display device may deteriorate. In this regard, according to the present embodiment, since the light shielding layer 40 is electrically connected to the constant potential source, the potential fluctuation of the light shielding layer 40 is suppressed, and as a result, the operation of the thin film transistor 20 is stabilized. .

  The manufacturing method of the TFT substrate in the present embodiment is different from the manufacturing method in the first embodiment in the points described below. That is, in this embodiment, after forming the protective insulating film 31, the contact holes 52 and 53 penetrating the protective insulating film 31 are formed. Thereafter, a film of a material constituting the gate electrode 22 and the wirings 50 and 51 is laminated on the protective insulating film 31. Then, the gate electrode 22 and the wirings 50 and 51 are formed by photolithography. The mask pattern for exposing the resist film is set so that the wirings 50 and 51 are connected to the light shielding layer 40 through the contact holes 52 and 53. Thereafter, the gate insulating film 32, the semiconductor layer 21, the interlayer insulating film 33, the drain electrode 23, the source electrode 24, and the protective insulating film 34 are formed in the same manner as in the first embodiment.

  In the example shown in FIG. 6, unlike the first embodiment (see FIG. 3), the light shielding layer 40 does not have the connection portion 43, and the light shielding layer 40 includes the drain side light shielding layer 41 and the source side light shielding layer. 42 and formed separately. However, similarly to the first embodiment, the light shielding layer 40 may include the connection portion 43.

[Third Embodiment]
The display device according to the third embodiment basically has the same configuration as that of the first embodiment (see FIGS. 1 and 2). FIG. 8 is an enlarged plan view showing a portion where the thin film transistor 20 is formed on the TFT substrate in FIG. 2, and corresponds to FIG. 3 in the first embodiment. FIG. 9 is a partial cross-sectional view showing a state of the cross section of the TFT substrate along the line IX-IX in FIG. 8, and corresponds to FIG. 4 in the first embodiment.

  The display device according to this embodiment is different from the first and second embodiments in that the light shielding layer 40 is electrically connected to the drain electrode 23 or the source electrode 24.

  In the present embodiment, the high-concentration drain region 21 d of the semiconductor layer 21 is connected to the drain-side light shielding layer 41 through the contact hole 60 that penetrates the protective insulating film 31 and the gate insulating film 32. Further, the drain electrode 23 is connected to the high-concentration drain region 21 d through a contact hole 35 that penetrates the interlayer insulating film 33. That is, the drain electrode 23 (in other words, drain wiring) and the drain side light shielding layer 41 are electrically connected.

  Similarly, the high-concentration source region 21 e of the semiconductor layer 21 is connected to the source-side light-shielding layer 42 through a contact hole 61 that penetrates the protective insulating film 31 and the gate insulating film 32. Further, the source electrode 24 is connected to the high-concentration source region 21 e through a contact hole 36 that penetrates the interlayer insulating film 33. That is, the source electrode 24 (in other words, the source wiring) and the source side light shielding layer 42 are electrically connected.

  Also in this embodiment, similarly to the first and second embodiments, incidence of light from the glass substrate 30 side to the semiconductor layer 21 is suppressed by the gate electrode 22 and the light shielding layer 40. As a result, generation of light leakage current is suppressed. Also in this embodiment, as in the first and second embodiments, the generation of parasitic capacitance between the gate electrode 22 and the light shielding layer 40 is suppressed. Furthermore, according to the present embodiment, the generation of parasitic capacitance between the drain electrode 23 (drain wiring) or the source electrode 24 (source wiring) and the light shielding layer 40 is also suppressed.

  Further, according to the present embodiment, since the light shielding layer 40 is connected to the drain electrode 23 or the source electrode 24, the potential of the light shielding layer 40 is stabilized, and as a result, the operation of the thin film transistor 20 is stabilized. It is done.

  By the way, when the light shielding layer 40 is connected to the constant potential source by the wirings 50 and 51 as in the second embodiment (see FIGS. 6 and 7), it is necessary to form the wirings 50 and 51 separately. For example, the degree of freedom in layout may be limited. In this regard, according to the present embodiment, it is not necessary to separately form the wirings 50 and 51, and as a result, it is possible to ensure, for example, a degree of freedom in layout.

  The manufacturing method of the TFT substrate in the present embodiment is different from the manufacturing method in the first embodiment in the points described below. That is, in this embodiment, after forming the gate insulating film 32, the contact holes 60 and 61 penetrating the gate insulating film 32 and the protective insulating film 31 are formed. Further, after forming the interlayer insulating film 33, contact holes 35 and 36 penetrating the interlayer insulating film 33 are formed. The contact hole 35 is formed at a position corresponding to the contact hole 60, and the contact hole 36 is formed at a position corresponding to the contact hole 61. Thereafter, as in the first embodiment, the drain electrode 23, the source electrode 24, and the protective insulating film 34 are formed.

  In the example shown in FIG. 8, unlike the first embodiment (see FIG. 3), the light shielding layer 40 does not have the connection portion 43, and the light shielding layer 40 includes the drain side light shielding layer 41 and the source side light shielding layer. 42 and formed separately. However, similarly to the first embodiment, the light shielding layer 40 may include the connection portion 43. In this case, the light shielding layer 40 is connected to either the drain electrode 23 (drain wiring) or the source electrode 24 (source wiring).

[Fourth Embodiment]
The display device according to the fourth embodiment basically has the same configuration as that of the first embodiment (see FIGS. 1 and 2). FIG. 10 is an enlarged plan view showing a portion where the thin film transistor 20 is formed on the TFT substrate in FIG. 2, and corresponds to FIG. 3 in the first embodiment. FIG. 11 is a partial cross-sectional view showing the state of the cross section of the TFT substrate taken along the line XI-XI in FIG. 10, and corresponds to FIG. 4 in the first embodiment.

  In the present embodiment, the light shielding layer 40 is formed as a conductor layer including the drain electrode 23 (drain wiring) and the source electrode 24 (source wiring). That is, in the present embodiment, the light shielding layer 40 functions as the drain electrode 23 (drain wiring) or the source electrode 24 (source wiring). In other words, in this embodiment, the drain electrode 23 (drain wiring) and the source electrode 24 (source wiring) also function as the light shielding layer 40. In this respect, the present embodiment is different from the first to third embodiments.

  Also in this embodiment, similarly to the first to third embodiments, incidence of light from the glass substrate 30 side to the semiconductor layer 21 is suppressed by the gate electrode 22 and the light shielding layer 40. As a result, generation of light leakage current is suppressed. Also in this embodiment, as in the first to third embodiments, the generation of parasitic capacitance between the gate electrode 22 and the light shielding layer 40 is suppressed. Furthermore, according to the present embodiment, the generation of parasitic capacitance between the drain electrode 23 (drain wiring) or the source electrode 24 (source wiring) and the light shielding layer 40 is also suppressed. Further, according to the present embodiment, since the light shielding layer 40 corresponds to the drain electrode 23 (drain wiring) or the source electrode 24 (source wiring), the potential of the light shielding layer 40 can be stabilized. As a result, the operation of the thin film transistor 20 is stabilized.

  The manufacturing method of the TFT substrate in the present embodiment is different from the manufacturing method in the first embodiment in the points described below. That is, in this embodiment, when the light shielding layer 40 is formed, the mask pattern used when exposing the resist film is such that the gate electrode 22 formed in the subsequent process is disposed on the light shielding layer 40 via the protective insulating film 31. The pattern is set so as not to overlap, and is set to a pattern corresponding to the shape of the drain electrode 23 (drain wiring) or the source electrode 24 (source wiring). In this embodiment, after forming the gate insulating film 32, contact holes 70 and 71 penetrating the gate insulating film 32 and the protective insulating film 31 are formed. The high-concentration drain region 21d of the semiconductor layer 21 is connected to the drain-side light-shielding layer 41 (that is, the drain electrode 23) through the contact hole 70, and the high-concentration source region 21e of the semiconductor layer 21 through the contact hole 71. Is connected to the source-side light shielding layer 42 (that is, the source electrode 24). Further, in the present embodiment, after the interlayer insulating film 33 is formed, the protective insulating film 34 is formed without performing the process for forming the conductor layer including the drain electrode 23 and the source electrode 24.

  According to the present embodiment, it is not necessary to separately perform the step of forming the light shielding layer 40 and the step of forming the conductor layer including the drain electrode 23 and the source electrode 24. It becomes possible to reduce. As a result, the manufacturing cost can be reduced.

[Fifth Embodiment]
The display device according to the fifth embodiment basically has the same configuration as that of the first embodiment (see FIGS. 1 and 2). FIG. 12 is an enlarged plan view showing a portion where the thin film transistor 20 is formed on the TFT substrate in FIG. 2, and corresponds to FIG. 3 in the first embodiment. FIG. 13 is a partial cross-sectional view showing a state of the cross section of the TFT substrate taken along line XIII-XIII in FIG. 12, and corresponds to FIG. 4 in the first embodiment.

  This embodiment is different from the first embodiment in that the end portion of the gate electrode 22 overlaps the end portion of the light shielding layer 40 via the protective insulating film 31. Note that the gate electrode 22 is not superimposed on a portion of the light shielding layer 40 other than the end portion.

  In the present embodiment, the end 41a of the drain side light shielding layer 41 is located inside the gate electrode 22 when viewed in plan. Specifically, the portion of the gate electrode 22 within a predetermined distance from the side edge 22a overlaps the portion of the drain side light shielding layer 41 within the predetermined distance from the end 41a with the protective insulating film 31 interposed therebetween. A side light shielding layer 41 is formed. In this case, the overlap width (the predetermined distance) is set to about 0.5 to 2.0 μm, for example.

  In the present embodiment, the end 42a of the source-side light shielding layer 42 is located inside the gate electrode 22 when viewed in plan. Specifically, the portion of the gate electrode 22 within a predetermined distance from the side edge 22b overlaps the portion of the source-side light shielding layer 42 within the predetermined distance from the end 42a with the protective insulating film 31 interposed therebetween. A side light shielding layer 42 is formed. In this case, the overlap width (the predetermined distance) is also set to about 0.5 to 2.0 μm, for example.

  Also in this embodiment, incidence of light from the glass substrate 30 side on the semiconductor layer 21 is suppressed by the gate electrode 22 and the light shielding layer 40. As a result, generation of light leakage current is suppressed.

  According to the present embodiment, the light shielding layer 40 is formed such that the end of the gate electrode 22 overlaps the end of the drain side light shielding layer 41 and the end of the source side light shielding layer 42 via the protective insulating film 31. Therefore, even when a misalignment occurs between the gate electrodes 22, a gap is hardly generated between the gate electrode 22 and the drain side light shielding layer 41 or the source side light shielding layer 42. As a result, it is possible to ensure that light from the glass substrate 30 side is not incident on the semiconductor layer 21 even when an interlayer misalignment occurs, and to ensure that no light leakage current occurs. It becomes possible.

  Further, according to the present embodiment, the light shielding layer 40 is formed such that the end of the gate electrode 22 overlaps the end of the drain side light shielding layer 41 and the end of the source side light shielding layer 42 via the protective insulating film 31. Therefore, even when light is incident on the glass substrate 30 at an angle, it is ensured that the light is not incident on the low-concentration drain region 21b or the low-concentration source region 21c. It becomes possible. That is, even when light is incident on the glass substrate 30 at an angle, it is possible to ensure that no light leakage current occurs.

  In the present embodiment, the light shielding layer 40 is formed such that only the end portion of the gate electrode 22 overlaps the end portion of the drain side light shielding layer 41 and the end portion of the source side light shielding layer 42 with the protective insulating film 31 interposed therebetween. The gate electrode 22 does not overlap with the region of the light shielding layer 40 other than the end of the drain side light shielding layer 41 and the end of the source side light shielding layer 42. In the present embodiment, since the area of the overlapping portion between the gate electrode 22 and the light shielding layer 40 is relatively small, the generation of parasitic capacitance between the gate electrode 22 and the light shielding layer 40 is reduced.

  The manufacturing method of the TFT substrate in the present embodiment is different from the manufacturing method in the first embodiment in the points described below. That is, in the present embodiment, when the light shielding layer 40 is formed, the mask pattern used when exposing the resist film includes the end portion of the gate electrode 22 and the end portion of the drain side light shielding layer 41 formed in a later step. In addition, only the end portion of the source-side light shielding layer 42 is set to overlap with the protective insulating film 31.

  The present invention is not limited to the embodiment described above.

  For example, the fifth embodiment may be combined with the second to fourth embodiments. FIG. 14 is a diagram illustrating an example in which the fifth embodiment is combined with the second embodiment, and corresponds to FIG. 7 in the second embodiment. FIG. 15 is a diagram illustrating an example in which the fifth embodiment is combined with the third embodiment, and corresponds to FIG. 9 in the third embodiment. FIG. 16 is a diagram illustrating an example in which the fifth embodiment is combined with the fourth embodiment, and corresponds to FIG. 11 in the fourth embodiment.

  For example, the present invention can also be applied to a display device in which a semiconductor layer is formed of amorphous silicon. In the above, an example in which the present invention is applied to a so-called IPS liquid crystal display device has been described, but the present invention can also be applied to a display device employing another method. For example, the present invention can also be applied to a so-called VA (Virtical Alignment) type or TN (Twisted Nematic) type liquid crystal display device. FIG. 17 is a circuit diagram showing a schematic circuit configuration of the scanning signal line 12, the video signal line 13, the thin film transistor 20, and the pixel electrode 14 mounted on the TFT substrate of the VA mode or TN mode liquid crystal display device. It is a figure corresponding to FIG. FIG. 18 is a plan view of one pixel region of the TFT substrate of the VA mode or TN mode liquid crystal display device, and corresponds to FIG. As shown in FIGS. 17 and 18, in the VA mode or TN mode liquid crystal display device, the common signal line 15 and the common electrode 16 are not formed on the TFT substrate, but a counter electrode is formed on the filter substrate. The liquid crystal molecules are controlled by a vertical electric field generated between the pixel electrode 14 of the TFT substrate and the counter electrode of the filter substrate.

It is a circuit diagram which shows the circuit structure mounted in the TFT substrate of the display apparatus which concerns on embodiment of this invention. It is a top view which shows the pixel area of the TFT substrate of the display apparatus which concerns on embodiment of this invention. It is an enlarged plan view which shows the location in which the thin-film transistor is formed of the TFT substrate in 1st Embodiment. It is a fragmentary sectional view of the TFT substrate in a 1st embodiment. It is a figure for demonstrating the manufacturing method of a TFT substrate. It is an enlarged plan view which shows the location in which the thin-film transistor is formed of the TFT substrate in 2nd Embodiment. It is a fragmentary sectional view of the TFT substrate in 2nd Embodiment. It is an enlarged plan view which shows the location in which the thin-film transistor is formed of the TFT substrate in 3rd Embodiment. It is a fragmentary sectional view of the TFT substrate in a 3rd embodiment. It is an enlarged plan view which shows the location in which the thin-film transistor is formed of the TFT substrate in 4th Embodiment. It is a fragmentary sectional view of the TFT substrate in 4th Embodiment. It is an enlarged plan view which shows the location in which the thin-film transistor is formed of the TFT substrate in 5th Embodiment. It is a fragmentary sectional view of the TFT substrate in 5th Embodiment. It is a figure which shows the example which combined 5th Embodiment with 2nd Embodiment. It is a figure which shows the example which combined 5th Embodiment with 3rd Embodiment. It is a figure which shows the example which combined 5th Embodiment with 4th Embodiment. It is a circuit diagram which shows the circuit structure mounted in the TFT substrate of the display apparatus which concerns on other embodiment of this invention. It is a top view which shows the pixel area | region of the TFT substrate of the display apparatus which concerns on other embodiment of this invention. It is a figure which shows the example at the time of using the technique regarding the light shielding layer disclosed regarding the thin-film transistor which has a top gate structure with the thin-film transistor which has a bottom gate structure.

Explanation of symbols

  10 scanning signal line drive circuit, 11 video signal line drive circuit, 12 scanning signal line, 13 video signal line, 14 pixel electrode, 15 common signal line, 16 common electrode, 20 thin film transistor, 21 semiconductor layer, 21a channel region, 21b low Concentration drain region, 21c low concentration source region, 21d high concentration drain region, 21e high concentration source region, 22 gate electrode, 22a, 22b side edge of gate electrode, 23 drain electrode, 24 source electrode, 30 glass substrate, 31, 34 Protective insulating film, 32 gate insulating film, 33 interlayer insulating film, 35, 36, 52, 53, 60, 61, 70, 71 contact hole, 40 light shielding layer, 41 drain side light shielding layer, 41a edge of drain side light shielding layer, 42 source side light shielding layer, 42a end of source side light shielding layer, 43 connection part, 50, 51 Wiring.

Claims (5)

A light-shielding layer for suppressing the incidence of light on the semiconductor layer, a first insulating film, a gate electrode of a thin film transistor, a second insulating film, and a substrate on which the semiconductor layer is sequentially stacked;
The light shielding layer is formed so that at least a part of the gate electrode does not overlap the light shielding layer via the first insulating film,
A display device characterized by that. The display device according to claim 1,
In the light shielding layer, an end portion of the gate electrode overlaps with an end portion of the light shielding layer through the first insulating film, and the gate electrode and the portion other than the end portion of the light shielding layer are in contact with the first insulating layer. A display device characterized by being formed so as not to overlap with a film. The display device according to claim 1,
The display device, wherein the light shielding layer is electrically connected to a source electrode or a drain electrode of the thin film transistor. The display device according to claim 1,
The display device, wherein the light shielding layer is formed as a conductor layer on which a source electrode or a drain electrode of the thin film transistor is formed. A display device including a substrate in which a light shielding layer for suppressing light incident on a semiconductor layer, a first insulating film, a gate electrode of a thin film transistor, a second insulating film, and the semiconductor layer are sequentially stacked. A manufacturing method comprising:
A first step of forming the light shielding layer on the substrate;
A second step of forming the first insulating film on the substrate on which the light shielding layer is formed;
Forming a gate electrode on the substrate on which the first insulating film is formed, and
In the first step and the third step, the light shielding layer and the gate electrode are formed such that at least a part of the gate electrode does not overlap with the light shielding layer via the first insulating film.
A manufacturing method of a display device characterized by the above.

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