KR20070088044A - Array substrate of lcd device and method of manufacturing the same - Google Patents

Abstract

An array substrate of an LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to prevent brightness differences from occurring between pixel areas by providing an ITO(Indium Tin Oxide) redundancy line contacting a data line and achieving uniform coupling parasitic electric capacitance between the ITO redundancy line and ITO electrodes. A plurality of pixel areas are defined by intersection of a gate lines and data lines(113) disposed on a glass substrate(110) in a matrix configuration. A thin film transistor including a gate electrode, an active layer, and source/drain electrodes is provided in each pixel area. In each pixel area, an ITO pixel electrode(115) is electrically connected to the corresponding thin film transistor, and an ITO redundancy line(116) is provided on the data line and directly contacts the data line. The ITO pixel electrode and the ITO redundancy line are formed of the same material on the same stacked level. The ITO redundancy line has a line width greater than that of the data line, and is spaced apart from the ITO pixel electrode at the same interval.

Description

Array substrate of LCD device and method of manufacturing the same {Array substrate of LCD device and method of manufacturing the same}

1 is a plan view schematically showing an array substrate of a conventional liquid crystal display device;

2 is a plan view schematically illustrating an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention;

3 is a cross-sectional view illustrating an array substrate of a liquid crystal display device taken along line III-III ′ of FIG. 2;

4A-4D are partial cross-sectional views sequentially illustrating the method of manufacturing the portion of FIG. 3.

<Description of the symbols for the main parts of the drawings>

100 ... array substrate 110 ... glass substrate

111 ... gate line 112 ... gate insulating film

113 ... data line 114 ... passivation layer

115 ... ITO pixel electrode 116 ... ITO redundancy line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate of a liquid crystal display device and a method of manufacturing the same, and more particularly to an array substrate of a liquid crystal display device and a method of manufacturing the same for equalizing parasitic capacitance between data lines and pixel electrodes.

In general, a liquid crystal display device is an electronic device that changes and transmits various electrical information generated by various devices into visual information by using a change in transmittance of a liquid crystal according to an applied voltage. An information display window of a portable terminal, a screen display of a notebook computer, etc. It is used as an information display window.

The liquid crystal display device includes a color filter substrate, an array substrate facing the color filter substrate, and a liquid crystal layer interposed between the color filter substrate and the array substrate.

Here, a thin film transistor is provided on the array substrate, and a pixel region in which the pixel electrode is provided by the intersection of the gate line and the data line is defined, and parasitic capacitance is generated between the data line and the neighboring pixel electrode.

However, when misalignment occurs in a mask process during an array substrate manufacturing process, a distance between a data line and a neighboring pixel electrode may be different, and thus parasitic capacitance may vary for each pixel region.

This is a phenomenon caused by the horizontal distance difference (D &gt; d) between the data line 12 and the pixel electrode 13 on each side of the data as shown in FIG. 1, and the difference in parasitic capacitance is the luminance in the pixel region. Will affect.

That is, when the data line 12 and the pixel electrode 13 are close by the misalignment, the parasitic capacitance is increased, and vice versa, the parasitic capacitance is decreased, based on the data line 12. When the parasitic capacitance is different between the pixel electrodes 13 provided at both sides, that is, when the coupling capacitance is different, the kickback voltage is influenced to affect the luminance difference in each pixel region A and A '. There is a problem that causes.

In order to solve this problem, a sufficient process margin must be secured so that the influence of parasitic capacitance is insignificant. When sufficient process margin is secured, the difference in parasitic capacitance can be overcome, but the aperture ratio of the liquid crystal display device is reduced accordingly. There is a problem.

Reference numeral 10 denotes an array substrate, and 11 denotes a gate line.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the liquid crystal display device, an ITO redundancy line electrically connected thereto is disposed on an upper portion of a data line using a process of forming an ITO pixel electrode, thereby providing an ITO redundancy line and an ITO redundancy line. It is an object of the present invention to provide an array substrate of an improved liquid crystal display device and a method of manufacturing the same, which can generate the same parasitic capacitance between ITO pixel electrodes to generate the same luminance without decreasing the aperture ratio in each pixel region.

In the array substrate of the liquid crystal display device of the present invention for achieving the above object, a plurality of pixel regions are defined by the intersection of the gate line and the data line arranged in a matrix form on the glass substrate, each pixel region In addition, a thin film transistor including a gate electrode, an active layer, and a source / drain electrode is provided. Each pixel area includes an ITO pixel electrode electrically connected to a corresponding thin film transistor, and is disposed on the data line to directly connect with the data line. And an ITO redundancy line in contact, wherein the ITO pixel electrode and the ITO redundancy line are formed at the same material and at the same stacking level, wherein the ITO redundancy line has a line width greater than that of the data line and at the same time from the ITO pixel electrode. Spaced at equal intervals The.

The method for manufacturing an array substrate of a liquid crystal display device according to the present invention includes: a gate line and a data line defining a plurality of pixel areas on a glass substrate; Providing a plurality of thin film transistors including a gate electrode, an active layer, and a source / drain electrode and disposed in each pixel region; Stacking a passivation layer to cover the entire surface of the substrate including the gate line, the data line and the thin film transistor; Patterning the passivation layer to expose a source electrode and a data line of the thin film transistor; Depositing an ITO layer on top of the patterned passivation layer; And an ITO pixel electrode disposed in each pixel region while being electrically connected to the source electrode by patterning the ITO layer, and having a line width larger than the line width of the data line while being disposed on the exposed data line. And dividing into ITO redundancy lines spaced at equal intervals from.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view schematically illustrating an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view illustrating the array substrate taken along line III-III ′ of FIG. 2.

Referring to the drawings, the array substrate 100 of the liquid crystal display device is provided with the ITO pixel electrode 115 by the intersection of the gate line 111 and the data line 113 arranged in a matrix form on the glass substrate 110. The pixel region B 'adjacent to the pixel region B is defined. 2 and 3 schematically illustrate only two neighboring pixel regions based on one data line 113, a person of ordinary skill in the art has a plurality of pixel regions in a matrix form on the glass substrate 110. You will notice.

2 and 3, the thin film transistor 120 disposed in the pixel region B includes a gate electrode 121 branched from the gate line 111, and a gate insulating layer 112 on the gate electrode 121. And a source electrode 122 and a drain electrode 123 formed via an active layer (not shown). The source electrode 122 is electrically connected to the ITO pixel electrode 115 through the contact hole 124, and the drain electrode 123 is branched from the data line 113.

Here, the gate insulating layer 112 is stacked on the entire surface of the substrate therebetween so that the gate line 111 and the data line 113 are insulated from each other with an interlayer separation. In addition, the passivation layer 114 may also be disposed on the entire surface of the substrate 110 to cover the lower layers including the thin film transistor 120 and the data line 113.

However, the passivation layer 114 not only exposes a part of the source electrode 121 so that the contact hole 124 is formed, but is also patterned so that a part or all of the top surface of the data line 113 is exposed to the outside.

The ITO pixel electrode 115 including the exposed data line 113 and the ITO pixel electrode 115 disposed in the pixel areas B and B ′ including the contact hole 124 may be formed on the upper stacked level of the passivation 114. An ITO redundancy line 116 disposed between 115 is provided.

Here, the line width X of the ITO redundancy line 116 is provided to be larger than the line width Y of the data line 113, so that the ITO redundancy line 116 is not only an upper surface of the data line 113 exposed to the outside. It is also disposed on the passivation layer 114 adjacent to the data line 113.

Accordingly, since the ITO redundancy line 116 is disposed to have a larger line width than the data line 113 while being in contact with the data line 113, the ITO pixel electrode adjacent to the data line 113 ( The parasitic capacitance generated between 115 is generated between the ITO redundancy line 116 and the neighboring ITO pixel electrode 115. In addition, since the ITO redundancy line 116 and the neighboring ITO pixel electrode 115 are formed by one process and are spaced apart at a desired interval, the parasitic capacitance is each pixel region B regardless of the misalignment during the process. Will occur consistently).

An array substrate having such a structure is manufactured sequentially in the order shown in FIGS. 4A to 4D.

However, in FIG. 4A to FIG. 4D, the thin film transistor portion is manufactured in a general process, and thus, the illustration thereof is omitted.

Referring to the drawings, an array substrate manufacturing method of a liquid crystal display device first prepares a gate line and a gate electrode branched from the gate line on a glass substrate.

A gate insulating film is formed over the glass substrate to cover the gate line and the gate electrode, and an active layer and a source / drain electrode are sequentially formed on the gate insulating film on the gate electrode so as to correspond to the gate electrode, thereby forming a thin film transistor. .

The drain electrode is branched from the data line, and the data line is provided on the gate insulating film 112 to cross the gate line as shown in FIG. 4A.

4, the passivation layer 114 is stacked to cover the entire surface of the glass substrate 110, that is, to cover the data line 113 and the gate insulating layer 112 (although not shown, but also the thin film transistor). Through patterning, some or all of the upper surface of the data line 113 is exposed to the outside as shown in FIG. 4C. In the patterning process of the passivation layer 114, a portion of the source electrode is also exposed to form a contact hole (not shown).

Finally, the ITO is stacked on the exposed source electrode, the data line 113 and the passivation layer 114, and then patterned using a single mask to form the passivation layer 114 on the pixel region as shown in FIG. 4D. An ITO pixel electrode 115 connected to the source electrode is formed through the contact hole, and simultaneously extends from the top of the exposed data line 113 to the top of the passivation layer 114 adjacent to the data line 113 and has a predetermined length. Line 116 is formed.

Here, the ITO redundancy line 116 is formed to extend from the top of the data line 113 to the top of the adjacent passivation layer 114, so that the line width X of the ITO redundancy line 116 is It is formed larger than the line width (Y).

Therefore, the ITO redundancy line 116 and the ITO pixel electrode 115 are formed through the same process, so that the interval between the ITO redundancy line 116 and the ITO pixel electrode 115 is formed in the same pixel area. In addition, since the ITO redundancy line 116 is in contact with the data line 113 with a line width larger than that of the data line 113, the parasitic capacitance generated between the conventional data line and the ITO pixel electrode is changed to each pixel. It occurs between the ITO redundancy line 116 and the ITO pixel electrode 115 disposed at equal intervals in the region.

In the array substrate of the liquid crystal display manufactured by the above method, the data line and the ITO redundancy lines contacted are formed to have the same interval through the same process as the ITO pixel electrode, so that parasitic capacitance is generated between the ITO redundancy line and the ITO pixel electrode. By doing so, the parasitic capacitance, that is, the coupling capacitance, can be prevented from generating a difference in luminance in each pixel region under the same conditions, and the liquid crystal display for securing sufficient process margin as in the prior art. It is not necessary to lower the aperture ratio of the apparatus.

As described above, according to the array substrate of the liquid crystal display and the method of manufacturing the same, a parasitic electrical coupling between the ITO redundancy line and the ITO electrodes provided in each pixel region is provided by providing an ITO redundancy line in contact with the data line. The capacitance is made uniform to provide the effect of preventing the occurrence of the luminance difference in each pixel region.

It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (2)

A plurality of pixel regions are defined by the intersection of gate lines and data lines arranged in a matrix on a glass substrate, and each of the pixel regions is further provided with a thin film transistor including a gate electrode, an active layer, and a source / drain electrode. Each pixel area includes an ITO pixel electrode electrically connected to a corresponding thin film transistor, and an ITO redundancy line disposed on the data line and in direct contact with the data line, wherein the ITO pixel electrode and the ITO redundancy line include: And the ITO redundancy lines are formed at the same material and at the same stacking level, and the line widths of the ITO redundancy lines are larger than the line widths of the data lines, and are spaced apart from the ITO pixel electrodes at equal intervals. A gate line and a data line defining a plurality of pixel regions on the glass substrate; Providing a plurality of thin film transistors including a gate electrode, an active layer, and a source / drain electrode and disposed in each pixel region; Stacking a passivation layer to cover the entire surface of the substrate including the gate line, the data line and the thin film transistor; Patterning the passivation layer to expose a source electrode and a data line of the thin film transistor; Depositing an ITO layer on top of the patterned passivation layer; And An ITO pixel electrode disposed in each pixel region while being electrically connected to the source electrode by patterning the ITO layer, and having a line width larger than the line width of the data line while being disposed on the exposed data line; A method of manufacturing an array substrate of a liquid crystal display device, the method comprising: dividing into ITO redundancy lines spaced at equal intervals.

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