KR102241444B1 - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The fringe field switching (FFS) liquid crystal display device of the present invention and a method of manufacturing the same are characterized in that an array substrate is manufactured in four mask processes using a lift-off process.
To this end, the common electrode is patterned by etching twice in the third mask process, and the overcoat layer is etched using the first patterned common electrode as a mask to form an overcoat layer hole. In addition, in the fourth mask process, a protective layer hole, a pixel electrode, and a pad portion electrode are simultaneously formed by using a half-tone mask and a lift-off process.
As described above, the reduction in the number of masks reduces manufacturing cost, increases productivity, and improves transmittance by forming fine overcoat layer holes.

Description

Fringe field type liquid crystal display device and its manufacturing method {FRINGE FIELD SWITCHING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a fringe field type liquid crystal display device and a method of manufacturing the same, and more particularly, to a fringe field type liquid crystal display device capable of simultaneously realizing high resolution and high transmittance, and a method of manufacturing the same.

Recently, as interest in information display has increased and the demand to use portable information media has increased, it has become a lightweight thin-film flat panel display (FPD) that replaces the existing display device, Cathode Ray Tube (CRT). Research and commercialization of Korea are being focused. In particular, among these flat panel display devices, a liquid crystal display (LCD) is a device that expresses an image by using the optical anisotropy of liquid crystal, and has excellent resolution, color display, and image quality, so it is actively applied to laptops and desktop monitors. have.

A liquid crystal display device is largely composed of a color filter substrate and an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

Hereinafter, a general liquid crystal display device will be described in detail with reference to the drawings.

1 is an exploded perspective view schematically showing the structure of a general liquid crystal display.

Referring to FIG. 1, a general liquid crystal display device is largely a color filter substrate 5 and an array substrate 10, and a liquid crystal layer 30 formed between the color filter substrate 5 and the array substrate 10. It consists of.

The color filter substrate 5 includes a color filter C and a sub-color filter 7 composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B). -It consists of a black matrix (BM) 6 that divides the color filters 7 and blocks unnecessary light, and a transparent common electrode 8 that applies a voltage to the liquid crystal layer 30.

In addition, the array substrate 10 is arranged vertically and horizontally to define a plurality of pixel regions P, a plurality of gate lines 16 and data lines 17, and a cross region between the gate lines 16 and the data lines 17. A thin film transistor (T), which is a switching device formed in, and a pixel electrode (18) formed on the pixel region (P).

The color filter substrate 5 and the array substrate 10 configured as described above are bonded to each other by a sealant (not shown) formed outside the image display area to form a liquid crystal panel. The bonding of the array substrate 10 is performed through the color filter substrate 5 or a bonding key (not shown) formed on the array substrate 10.

At this time, there is a twisted nematic (TN) method that drives nematic liquid crystal molecules in a vertical direction with respect to the substrate as a driving method generally used in liquid crystal display devices, but the twisted nematic liquid crystal display device has a viewing angle. It has the disadvantage of being narrow at about 90 degrees. This is due to the refractive index anisotropy of the liquid crystal molecules, and this is because liquid crystal molecules aligned horizontally with the substrate are aligned in a substantially vertical direction with the substrate when a voltage is applied to the liquid crystal panel.

Accordingly, there is an In Plane Switching (IPS) type liquid crystal display device in which the viewing angle is increased to 170 degrees or more by driving liquid crystal molecules in a horizontal direction with respect to a substrate, and this will be described in detail as follows.

2 is a schematic cross-sectional view of a part of an array substrate of a transverse electric field type liquid crystal display. In particular, FIG. 2 is a Fringe Field Switching (FFS) liquid crystal in which a fringe field formed between a pixel electrode and a common electrode penetrates a slit to drive liquid crystal molecules positioned on a pixel region and a pixel electrode to realize an image. A part of the array substrate of the display device is shown.

In this case, the drawing shows one pixel including a pixel portion, a data pad portion, and a gate pad portion for convenience of description.

Referring to FIG. 2, a gate line (not shown) and a data line 17 are formed on an array substrate 10 of a general fringe field type liquid crystal display device, arranged vertically and horizontally to define a pixel region. In addition, a thin film transistor, which is a switching element, is formed in a cross region between the gate line and the data line 17.

The thin film transistor includes a gate electrode 21 connected to a gate line, a source electrode 22 connected to a data line, and a drain electrode 23 connected to the pixel electrode 18. In addition, the thin film transistor is connected to the source electrode 22 by a gate insulating layer 15a for insulation between the gate electrode 21 and the source/drain electrodes 22 and 23, and a gate voltage supplied to the gate electrode 21. It includes an active layer 24 forming a conductive channel between the drain electrodes 23.

The source/drain regions of the active layer 24 form ohmic-contacts with the source/drain electrodes 22 and 23 through an ohmic contact layer 25.

Below the data line 17, a first amorphous silicon thin film pattern 24 ′ and a first n+ amorphous silicon thin film composed of an amorphous silicon thin film constituting the active layer 24 and an n+ amorphous silicon thin film constituting the ohmic-contact layer 25 A silicon thin film pattern 25' is formed.

In the pixel region, a common electrode 8 and a pixel electrode 18 are formed. In this case, a plurality of square-shaped pixel electrodes 18 are formed in the pixel electrode 18 together with the common electrode 8 to generate a fringe field. I include a slit (18s) of.

In the edge region of the array substrate 10 configured as described above, a data line 17 and a data pad electrode 27p and a gate pad electrode 26p electrically connected to the gate line are formed, respectively, and an external driving circuit unit (not shown) The data signal and the scan signal received from the data line 17 and the gate line are transmitted to the data line 17 and the gate line, respectively.

That is, the data line 17 and the gate line extend toward the driving circuit and are connected to the corresponding data pad line 17p and the gate pad line 16p, respectively. In addition, the data pad line 17p and the gate pad line 16p are the data pad electrode patterns 27p' and 27p electrically connected to the data pad line 17p and the gate pad line 16p, respectively. The data signal and the scan signal are respectively applied from the driving circuit unit through the gate pad electrode pattern 26p' and the gate pad electrode 26p.

In this case, a second amorphous silicon thin film pattern 24" and a second n+ amorphous silicon thin film pattern 25" made of an amorphous silicon thin film and an n+ amorphous silicon thin film are formed under the data pad line 17p.

For reference, reference numerals 15b, 15c, and 15d denote a first interlayer insulating layer, a second interlayer insulating layer, and a protective layer.

The fringe field type liquid crystal display configured as described above has an advantage in that the viewing angle and transmittance are improved compared to the conventional twisted nematic method. However, since a plurality of mask processes (ie, photolithography) of about 6 to 7 are required to fabricate an array substrate including a thin film transistor, a method of reducing the number of masks in terms of productivity is required.

3A to 3F are cross-sectional views sequentially showing a manufacturing process of the array substrate shown in FIG. 2.

Referring to FIG. 3A, a gate electrode 21 made of a conductive metal material, a gate line (not shown), and a gate pad line 16p are formed on the array substrate 10 by using a photolithography process (a first mask process). do.

Next, referring to FIG. 3B, a gate insulating layer 15a, an amorphous silicon thin film, and an n+ amorphous silicon thin film are sequentially formed on the front surface of the array substrate 10 on which the gate electrode 21, the gate line, and the gate pad line 16p are formed. And depositing a conductive metal material.

Thereafter, by selectively patterning an amorphous silicon thin film, an n+ amorphous silicon thin film, and a conductive metal material using a photolithography process (second mask process), the amorphous silicon layer is interposed on the gate electrode 21 with the gate insulating layer 15a interposed therebetween. An active layer 24 made of a thin film is formed. Further, a source electrode 22 and a drain electrode 23 made of a conductive metal material are formed on the active layer 24.

At this time, a data line 17 made of a conductive metal material is formed in the data line area of the array substrate 10 through the second mask process, and a data pad line made of a conductive metal material is formed on the data pad portion of the array substrate 10. (17p) is formed.

In this case, an ohmic-contact layer 25 formed of an n+ amorphous silicon thin film on the active layer 24 and for ohmic-contacting the source/drain regions of the active layer 24 and the source/drain electrodes 22 and 23 Is formed.

In addition, under the data line 17, a first amorphous silicon thin film pattern 24 ′ and a first n+ amorphous silicon thin film are formed of an amorphous silicon thin film and an n+ amorphous silicon thin film, respectively, and patterned in substantially the same shape as the data line 17. A silicon thin film pattern 25' is formed.

Further, under the data pad line 17p, a second amorphous silicon thin film pattern 24" and a second amorphous silicon thin film pattern 24" and a second amorphous silicon thin film made of an amorphous silicon thin film and an n+ amorphous silicon thin film, respectively, are patterned in substantially the same shape as the data pad line 17p. An n+ amorphous silicon thin film pattern 25" is formed.

Next, referring to FIG. 3C, a first interlayer insulating layer 15b and a second interlayer insulating layer 15c are formed on the entire surface of the array substrate 10.

Thereafter, the drain electrode 23 is selectively patterned using a photolithography process (third mask process) to selectively pattern some regions of the gate insulating layer 15a, the first interlayer insulating layer 15b, and the second interlayer insulating layer 15c. A first contact hole 40a exposing a part of) is formed. At the same time, a second contact hole 40b and a third contact hole 40c exposing portions of the data pad line 17p and the gate pad line 16p, respectively, are formed.

At this time, the second interlayer insulating layer 15c is made of photoacrylic.

Next, referring to FIG. 3D, after depositing a transparent conductive metal material on the entire surface of the array substrate 10, a conductive metal material that is transparent throughout the pixel portion is selectively patterned using a photolithography process (fourth mask process). A common electrode 8 made of is formed.

At this time, the data pad electrode pattern 27p' electrically connected to the data pad line 17p and the gate pad line 16p by selectively patterning a transparent conductive metal material through the fourth mask process. ) And a gate pad electrode pattern 26p', respectively.

Next, referring to FIG. 3E, a protective layer 15d is formed on the entire surface of the array substrate 10 at a low temperature.

Thereafter, the drain electrode 23, the data pad electrode pattern 27p' and the gate pad electrode pattern 26p' were selectively patterned by selectively patterning a partial region of the protective layer 15d using a photolithography process (a fifth mask process). A fourth contact hole 40d, a fifth contact hole 40e, and a sixth contact hole 40f exposing a portion of the are formed.

Next, referring to FIG. 3F, after depositing a transparent conductive metal material on the entire surface of the array substrate 10, the fourth contact hole 40d is selectively patterned using a photolithography process (sixth mask process). A pixel electrode 18 electrically connected to the drain electrode 23 through) is formed.

In addition, by selectively patterning a transparent conductive metal material through a sixth mask process, the data pad electrode pattern 27p' is formed through the fifth contact hole 40e and the sixth contact hole 40f in the data pad portion and the gate pad portion. And a data pad electrode 27p and a gate pad electrode 26p electrically connected to the gate pad electrode pattern 26p'.

At this time, the pixel electrode 18 includes a plurality of slits 18s in the pixel electrode 18 to generate a fringe field together with the common electrode 8 below it.

As described above, in order to form a vertical electric field between the common electrode 8 and the pixel electrode 18, the general fringe field type liquid crystal display device has the common electrode 8 and the pixel electrode in different layers with the protective layer 15d interposed therebetween. Form (18). In addition, the drain contact hole, that is, the first contact hole 40a and the fourth contact hole 40d are formed in the second process, and thus, at least two more mask processes are required compared to the horizontal electric field type liquid crystal display device. .

In addition, since the second interlayer insulating layer 15c is formed of photo acrylic, there is a limit to reducing the size of the drain contact hole due to the etching characteristics of photo acrylic. Therefore, there is a limit to realizing high resolution.

An object of the present invention is to solve the above-described problem, and to provide a fringe field type liquid crystal display device and a method of manufacturing the same, in which an array substrate is fabricated in the fourth mask process.

Another object of the present invention is to provide a fringe field type liquid crystal display device in which fine overcoat layer holes are formed by self-alignment, and a method of manufacturing the same.

In addition, other objects and features of the present invention will be described in the configuration and claims of the invention to be described later.

In order to achieve the above object, the fringe field type liquid crystal display device according to an embodiment of the present invention is composed of a double interlayer insulating layer of a first interlayer insulating layer and a second interlayer insulating layer, The first contact hole and the first contact hole are partially removed to expose a part of the first interlayer insulating layer on the drain electrode, and a partial region of the first protective layer is removed to expose a part of the drain electrode. It can be configured including 2 contact holes.

In this case, the common electrode may be disposed on the second interlayer insulating layer, and the first protective layer may be disposed on the common electrode.

The pixel electrode has a plurality of slits, and may be electrically connected to the drain electrode through a second contact hole.

At this time, the fringe field type liquid crystal display device according to an embodiment of the present invention includes an insulating layer pattern disposed in a slit of a pixel electrode, and a first protective layer between the pixel electrode in the second contact hole and the side surface of the second interlayer insulating layer. It is characterized by being interposed.

The common electrode may be positioned at a predetermined distance from the edge of the second interlayer insulating layer.

The insulating layer pattern maintains a predetermined distance from the pixel electrode and may be disposed in a direction parallel to the slit.

A second protective layer made of an insulating material constituting the first protective layer and the insulating layer pattern may be stacked on the data pad portion and the gate pad portion while the second interlayer insulating layer is removed.

In addition, a method of manufacturing a fringe field type liquid crystal display device according to an embodiment of the present invention includes forming a first contact hole exposing the first interlayer insulating layer on the drain electrode through a third mask process, and forming a second contact hole in the pixel portion. Forming a common electrode on the interlayer insulating layer, forming a first protective layer and a second protective layer on the common electrode, and forming a pixel electrode having a plurality of slits in the pixel portion of the first substrate through the fourth mask process And forming an insulating layer pattern made of the second protective layer in the slit of the pixel electrode.

In this case, in the manufacturing method of the fringe field type liquid crystal display according to an embodiment of the present invention, the data pad portion and the second interlayer insulating layer of the gate pad portion of the first substrate are removed using a third mask process. It may further include exposing the first interlayer insulating layer of the gate pad part.

The third mask process includes forming a third conductive layer on the second interlayer insulating layer, forming a first photoresist layer pattern and a second photoresist layer pattern on the third conductive layer, and using the first photoresist layer pattern and the second photoresist layer pattern as a mask. Forming a conductive layer pattern made of the third conductive layer in a pixel portion by selectively patterning a partial area of the third conductive layer, and using the first photoresist layer pattern, the second photoresist layer pattern, and the conductive layer pattern as a mask, and a second interlayer insulating layer And forming a first contact hole on the drain electrode to expose a part of the first interlayer insulating layer by selectively patterning a partial region of the.

At this time, patterning of the third conductive layer is performed using a wet etching method, and during wet etching, a part of the conductive layer pattern is over-etched to retreat from the side surfaces of the first photoresist pattern and the second photoresist pattern.

The second interlayer insulating layer is patterned using dry etching, and during dry etching, a portion of the first photoresist layer pattern and the second photoresist layer pattern are removed, thereby reducing the width and thickness of the first photoresist layer pattern and the second photoresist layer pattern. And a fourth photoresist pattern may be formed.

In this case, a common electrode made of a conductive layer may be formed in the pixel portion by secondarily patterning the conductive layer pattern using the third photoresist layer pattern and the fourth photoresist layer pattern as a mask.

In the fourth masking process, a photoresist pattern is formed on the second protective layer, and partial regions of the first interlayer insulating layer, the first protective layer, and the second protective layer are selectively patterned in the first contact hole using the photoresist pattern as a mask. Forming a second contact hole exposing a portion of the drain electrode, removing a part of the thickness of the photosensitive film pattern through an ashing process, and selectively patterning a partial region of the second protective layer to form an insulating film pattern under the ashed photosensitive film pattern Forming a conductive film on the pixel portion by selectively removing the ashed photosensitive film pattern and the conductive film on the ashed photosensitive film pattern through the step of forming, forming a conductive film thereon while the ashed photosensitive film pattern remains, and a lift-off process. It may include the step of forming a pixel electrode made of.

As described above, the fringe field type liquid crystal display device and its manufacturing method according to an exemplary embodiment of the present invention provide an effect of reducing manufacturing cost and increasing productivity as an array substrate is manufactured through four mask processes.

In addition, the fringe field type liquid crystal display according to an exemplary embodiment of the present invention and a method of manufacturing the same can improve transmittance by forming fine overcoat layer holes in self-alignment. Therefore, it provides an effect of improving image quality by implementing high resolution.

1 is an exploded perspective view schematically showing the structure of a general liquid crystal display.
2 is a schematic cross-sectional view of a part of an array substrate of a transverse electric field type liquid crystal display.
3A to 3F are cross-sectional views sequentially showing a manufacturing process of the array substrate shown in FIG. 2.
4 is a cross-sectional view schematically showing a part of an array substrate of a fringe field type liquid crystal display according to an exemplary embodiment of the present invention.
5A to 5D are cross-sectional views sequentially showing a manufacturing process of the array substrate shown in FIG. 4.
6A to 6F are cross-sectional views specifically showing the third mask process shown in FIG. 5C.
7A to 7H are cross-sectional views specifically showing the fourth mask process shown in FIG. 5D.
FIG. 8 is an enlarged cross-sectional view of portion A of the array substrate shown in FIG. 7G.

Hereinafter, a preferred embodiment of a fringe field type liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily implement it.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the present embodiments are intended to complete the disclosure of the present invention, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same elements throughout the specification. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity of description.

When an element or layer is another element or referred to as “on” or “on”, it includes not only directly above the other element or layer, but also a case in which another layer or other element is interposed in the middle. do. On the other hand, when a device is referred to as "directly on" or "directly on", it indicates that no other device or layer is interposed therebetween.

The terms "below, beneath", "lower", "above", and "upper", which are spatially relative terms, refer to one element or component as shown in the drawing. It can be used to easily describe the correlation between the and other devices or components. Spatially relative terms should be understood as terms including different directions of the device during use or operation in addition to the directions shown in the drawings. For example, if an element shown in the figure is turned over, an element described as “below” or “beneath” another element may be placed “above” another element. Accordingly, the exemplary term “below” may include both directions below and above.

The terms used in the present specification are for describing exemplary embodiments, and therefore, are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used in the specification, "comprise" and/or "comprising" refers to the presence of one or more other components, steps, actions and/or elements in which the recited component, step, operation and/or element Or does not preclude additions.

4 is a schematic cross-sectional view illustrating a part of an array substrate of a fringe field type liquid crystal display according to an exemplary embodiment of the present invention.

In this case, FIG. 4 shows a part of an array substrate of a fringe field type liquid crystal display device in which a fringe field formed between a pixel electrode and a common electrode penetrates a slit to drive liquid crystal molecules positioned on the pixel region and the pixel electrode to realize an image An example is shown.

In a fringe field type liquid crystal display, when the liquid crystal molecules are horizontally oriented, a common electrode is formed at the bottom while a pixel electrode having a slit is formed at the top, so that an electric field is generated in the horizontal and vertical directions, causing the liquid crystal molecules to twist ( It is driven by twisting and tilting.

In this case, the drawing shows one pixel including a pixel portion, a data pad portion, and a gate pad portion for convenience of description. That is, in an actual liquid crystal display device, there are MxN pixels by crossing N gate lines and M data lines, but one pixel is shown in the drawing for simplicity of explanation.

Referring to FIG. 4, a gate line (not shown) and a data line 117 are formed on an array substrate 110 according to an exemplary embodiment of the present invention and are arranged vertically and horizontally to define a pixel region.

In addition, a thin film transistor, which is a switching element, is formed in the crossing region of the gate line and the data line 117, and a common electrode 108 and a plurality of slits 118s for driving liquid crystal molecules by generating a fringe field in the pixel region. A pixel electrode 118 having a is formed.

The thin film transistor is a drain electrically connected to the pixel electrode 118 through a gate electrode 121 connected to a gate line, a source electrode 122 connected to the data line 117, and a second contact hole (ie, a drain contact hole). It consists of an electrode 123. In addition, the thin film transistor is connected to the source electrode 122 by the gate insulating layer 115a for insulation between the gate electrode 121 and the source/drain electrodes 122 and 123 and the gate voltage supplied to the gate electrode 121. It includes an active layer 124 forming a conductive channel between the drain electrodes 123.

In this case, the source/drain regions of the active layer 124 form ohmic-contacts with the source/drain electrodes 122 and 123 through the ohmic-contact layer 125.

A first amorphous silicon thin film pattern 124 ′ and a first n+ amorphous silicon thin film pattern formed of an amorphous silicon thin film and an n+ amorphous silicon thin film under the data line 117 and patterned in substantially the same shape as the data line 117 (125') is formed.

As described above, the common electrode 108 and the pixel electrode 118 are formed in the pixel region to generate a fringe field. At this time, the square-shaped pixel electrode 118 forms a fringe field together with the common electrode 108. A plurality of slits 118s are included in the pixel electrode 118 to generate.

However, the present invention is not limited to the structures of the common electrode 108 and the pixel electrode 118, and the present invention is applicable even when a pixel electrode is formed at the bottom and a common electrode having a plurality of slits is formed at the top. Do.

In this case, an insulating layer pattern 115 is formed in the slit 118s of the pixel electrode 118 and is made of an insulating material and is disposed in a direction parallel to the slit 118s while maintaining a predetermined distance from the pixel electrode 118. . However, the present invention is not limited thereto, and the insulating layer pattern 115 may contact the pixel electrode 118.

The common electrode 108 may be formed in a single pattern over the entire pixel portion except for a first contact hole (ie, an overcoat layer hole) region including the second contact hole region.

In this case, the common electrode 108 according to the exemplary embodiment of the present invention may be formed at a predetermined distance from the pixel electrode 118 so as not to be shorted with the pixel electrode 118 formed in the drain contact hole. That is, the common electrode 108 may be formed to be spaced apart from the edge of the second interlayer insulating layer 115c through two patterning.

The common electrode 108 is formed on the first interlayer insulating layer 115b and the second interlayer insulating layer 115c.

In this case, the buffer insulating layer serves as the first interlayer insulating layer 115b.

The second interlayer insulating layer 115c as an overcoat layer may be made of an organic insulating material such as photo acrylic to increase high resolution and transmittance.

At this time, the first passivation layer 115d is filled in the overcoat layer hole, and a portion of the first passivation layer 115d is removed to form a drain contact hole.

In the edge region of the array substrate 110 configured as described above, a data line 117 and a data pad electrode 127p and a gate pad electrode 126p electrically connected to the gate line are formed, respectively, and an external driving circuit unit (not shown) The data signal and the scan signal received from the data line 117 and the gate line are transmitted to the data line 117 and the gate line, respectively.

That is, the data line 117 and the gate line extend toward the driving circuit and are connected to the corresponding data pad line 117p and the gate pad line 116p, respectively. In addition, the data pad line 117p and the gate pad line 116p are electrically connected to the data pad line 117p and the gate pad line 116p, respectively, through the data pad electrode 127p and the gate pad electrode 126p. A data signal and a scan signal are respectively applied from the driving circuit unit.

At this time, a second amorphous silicon thin film pattern 124" and a second n+ amorphous silicon thin film pattern 125" made of an amorphous silicon thin film and an n+ amorphous silicon thin film are formed under the data pad line 117p.

As described above, the second interlayer insulating layer 115c is an organic insulating material having a low dielectric constant such as photoacrylic to reduce parasitic capacitance due to overlap between the data line 117 and the common electrode 108. It can be formed using In addition, the first interlayer insulating layer 115b and the first protective layer 115d may be formed of an inorganic insulating material such as a _{silicon nitride layer (SiNx) and a silicon oxide layer (SiO 2 ).}

In this case, in the embodiment of the present invention, the second interlayer insulating layer 115c of the data pad portion and the gate pad portion is removed. Accordingly, a defect in which the second interlayer insulating layer 115c made of an organic insulating material is torn when the pad portion is repaired can be prevented.

In addition, a second protective layer 115e made of the same insulating material as the insulating layer pattern 115 is formed on the first protective layer 115d around the data pad electrode 127p and the gate pad electrode 126p.

The second protective layer 115e including the insulating layer pattern 115 may be formed to be porous by using sputtering. Accordingly, since the etching speed is faster than that of the lower first passivation layer 115c, an under cut may be formed under the photoresist pattern.

The fringe field type liquid crystal display according to the embodiment of the present invention configured as described above uses a half-tone mask or a diffraction mask (hereinafter, when referring to a half-tone mask, a diffraction mask is included). As a result, the array substrate is manufactured through a total of four mask processes.

To this end, the common electrode is patterned by etching twice in the third mask process, and the overcoat layer is etched using the first patterned common electrode as a mask to form an overcoat layer hole. In addition, in the fourth mask process, the protective layer hole, the pixel electrode, and the pad portion electrode are simultaneously formed by using a half-tone mask and a lift-off process.

At this time, it is characterized in that the protective layer is formed of double, that is, a first protective layer and a second protective layer in order to smoothly proceed the lift-off process.

As described above, the fringe field type liquid crystal display device according to an exemplary embodiment of the present invention maintains the advantages of high resolution and high transmittance, while reducing the number of masks required to manufacture an array substrate, thereby reducing manufacturing cost and increasing productivity.

In addition, the overcoat layer holes may be formed by etching the overcoat layer using a common electrode as a mask instead of the photoresist pattern, thereby reducing the size of the overcoat layer holes by self-alignment. Therefore, it is possible to prevent a decrease in transmittance at high resolution.

Hereinafter, a method of manufacturing a fringe field type liquid crystal display according to an embodiment of the present invention configured as described above will be described in detail with reference to the drawings.

5A to 5D are cross-sectional views sequentially showing a manufacturing process of the array substrate shown in FIG. 4.

At this time, a process of manufacturing an array substrate of the pixel portion is shown on the left, and a process of manufacturing an array substrate of the data pad portion and the gate pad portion in turn is shown on the right.

As shown in FIG. 5A, a gate electrode 121, a gate line (not shown), and a common line (not shown) are formed in the pixel portion of the array substrate 110 made of a transparent insulating material such as glass. In addition, a gate pad line 116p is formed on the gate pad portion of the array substrate 110.

The gate electrode 121, the gate line, the common line, and the gate pad line 116p are formed by depositing a first conductive layer on the entire surface of the array substrate 110 and then selectively patterning through a photolithography process (a first mask process). .

The first conductive layer is formed of aluminum (Al), aluminum alloy, tungsten (W), copper (copper) to form the gate electrode 121, the gate line, the common line, and the gate pad line 116p. ; It may be formed of a low-resistance opaque conductive material such as Cu), chromium (Cr), molybdenum (Mo), and molybdenum alloy. In addition, the first conductive layer may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked.

Next, as shown in FIG. 5B, a gate insulating layer 115a, an amorphous silicon thin film, and n+ are formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line, the common line, and the gate pad line 116p are formed. An amorphous silicon thin film and a second conductive film are formed.

The second conductive layer may be made of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, and molybdenum alloy to form source/drain electrodes, data lines, and data pad lines. In addition, the second conductive layer may be formed in a multilayer structure in which two or more low-resistance conductive materials are stacked.

Thereafter, the amorphous silicon thin film, the n+ amorphous silicon thin film, and the second conductive film are selectively removed through a photolithography process (second mask process), so that the amorphous silicon thin film is interposed on the gate electrode 121 with the gate insulating layer 115a interposed therebetween. An active layer 124 made of is formed.

At the same time, a source electrode 122 and a drain electrode 123 made of a second conductive layer are formed on the active layer 124.

In addition, a data line 117 made of a second conductive layer is formed in the data line region of the array substrate 110 through a second mask process. At the same time, a data pad line 117p made of a second conductive layer is formed on the data pad portion of the array substrate 110.

In this case, the ohmic-contact layer 125 is made of an n+ amorphous silicon thin film on the active layer 124 and provides ohmic-contact between the source/drain regions of the active layer 124 and the source/drain electrodes 122 and 123 Is formed.

Further, under the data line 117, a first amorphous silicon thin film pattern 124' and a first n+ amorphous silicon thin film are formed of an amorphous silicon thin film and an n+ amorphous silicon thin film, respectively, and patterned in substantially the same shape as the data line 117. A silicon thin film pattern 125' is formed.

Further, under the data pad line 117p, a second amorphous silicon thin film pattern 124" and a second amorphous silicon thin film pattern 124" and a second amorphous silicon thin film formed of an amorphous silicon thin film and an n+ amorphous silicon thin film, respectively, and patterned in substantially the same shape as the data pad line 117p. An n+ amorphous silicon thin film pattern 125" is formed.

In this case, the second mask process according to the embodiment of the present invention may use a half-tone mask. However, the present invention is not limited thereto.

Next, as shown in FIG. 5C, the first active layer 124, the source/drain electrodes 122 and 123, the data line 117, and the data pad line 117p are formed on the front surface of the array substrate 110. An interlayer insulating layer 115b, a second interlayer insulating layer 115c, and a third conductive film are formed.

In this case, the first interlayer insulating layer 115b may be made of an inorganic insulating material such as a silicon nitride film or a silicon oxide film. The first interlayer insulating layer 115b serves as a buffer insulating layer.

As an overcoat layer, the second interlayer insulating layer 115c may be made of an organic insulating material having a low dielectric constant such as photoacrylic in order to increase high resolution and transmittance.

The third conductive layer may be made of a transparent conductive metal material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a common electrode.

Thereafter, a first contact hole for exposing a part of the first interlayer insulating layer 115b of the pixel portion by selectively removing the second interlayer insulating layer 115c and the third conductive layer through a photolithography process (a third mask process) That is, an overcoat layer hole) 140a is formed.

At the same time, a common electrode 108 made of a third conductive layer is formed in the pixel portion of the array substrate 110.

In addition, the data pad portion and the gate pad portion are opened by removing the second interlayer insulating layer 115c and the third conductive layer of the data pad portion and the gate pad portion through a third mask process. Accordingly, the data pad portion and the first interlayer insulating layer 115b of the gate pad portion are exposed.

At this time, in the third mask process, the common electrode 108 is patterned by two etchings, and the second interlayer insulating layer 115c is etched using the first patterned common electrode 108 as a mask to form the first contact hole 140a. It is characterized in that to form. Accordingly, the size of the first contact hole 140a can be reduced, which will be described in detail with reference to the following drawings.

6A to 6F are cross-sectional views specifically showing the third mask process shown in FIG. 5C.

6A, a first interlayer insulating layer 115b, a second interlayer insulating layer 115c, and a third conductive layer 130 are formed on the entire surface of the array substrate 110.

As described above, the first interlayer insulating layer 115b may be made of an inorganic insulating material such as a silicon nitride film or a silicon oxide film. The first interlayer insulating layer 115b serves as a buffer insulating layer.

As an overcoat layer, the second interlayer insulating layer 115c may be made of an organic insulating material having a low dielectric constant such as photoacrylic in order to increase high resolution and transmittance.

The third conductive layer 130 is made of a transparent conductive metal material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a common electrode. I can.

Next, as shown in FIG. 6B, after forming a photosensitive film 160 made of a photosensitive material such as photoresist on the array substrate 110 on which the third conductive film 130 is formed, The photosensitive film 160 is selectively irradiated with light.

At this time, the mask 170 is provided with a transmissive region (I) that transmits all the irradiated light and a blocking region (II) that blocks all the irradiated light, and only the light that has transmitted through the mask 170 is disposed on the photosensitive layer 160. It is investigated.

Subsequently, after the photosensitive layer 160 exposed through the mask 170 is developed, as shown in FIG. 6C, a first photoresist layer pattern 160a having a predetermined thickness is formed in the area where light is blocked through the blocking area II. And the second photosensitive film pattern 160b remains, and the photosensitive film is completely removed in the transmission region I through which light is transmitted, so that the surface of the third conductive film 130 is exposed.

Next, as shown in FIG. 6D, by using the first photoresist pattern 160a and the second photoresist pattern 160b as masks, a partial region of the third conductive layer formed under the first photoresist layer pattern 160a and the second photoresist layer pattern 160b is selectively removed (primary patterning). On the lower surface, a conductive layer pattern 130 ′ made of a third conductive layer is formed on the pixel portion.

In this case, the third conductive layer may be patterned by wet etching.

In this case, the conductive layer pattern 130 ′ may be partially over-etched to have a shape retracted from the side surfaces of the first photoresist layer pattern 160a and the second photoresist layer pattern 160b. However, the present invention is not limited thereto.

Further, as shown in FIG. 6E, the first photoresist pattern 160a, the second photoresist pattern 160b, and the conductive layer pattern 130' are used as masks, and the second interlayer insulating layer 115c under the first photoresist pattern 160a, the second photoresist pattern 160b, and the conductive layer pattern 130' are used as masks. When a partial region of) is selectively removed, a first contact hole (ie, an overcoat layer hole) 140a exposing a part of the first interlayer insulating layer 115b is formed on the drain electrode 123.

At the same time, as the second interlayer insulating layer 115c of the data pad portion and the gate pad portion is removed, the data pad portion and the gate pad portion are opened. Accordingly, the data pad portion and the first interlayer insulating layer 115b of the gate pad portion are exposed.

In this case, dry etching may be used for patterning the second interlayer insulating layer 115c.

At this time, there is a limit in reducing the size of the overcoat layer hole since dry etching is performed by using the photosensitive film pattern as a mask to form the hole in the overcoat layer. This is because, during dry etching, not only the overcoat layer, that is, the second interlayer insulating layer, but also a part of the width and thickness of the photoresist pattern is removed.

However, when a conductive layer pattern 130' made of a metal material is present under the first photoresist layer pattern 160a and the second photoresist layer pattern 160b as in the present invention, the conductive layer pattern 130' is formed in the form of the conductive layer pattern 130'. The second interlayer insulating layer 115c may be patterned. As a result, it is possible to form the fine overcoat layer hole (140a).

This is because even though the first photoresist pattern 160a and the second photoresist pattern 160b are partially removed during dry etching, the width and thickness thereof are reduced to the third photoresist pattern 160a' and the fourth photoresist pattern 160b'. This is because the conductive layer pattern 130 ′ existing under the layer acts as a mask.

Next, as shown in FIG. 6F, the conductive layer pattern 130' is secondarily patterned using the third photoresist layer pattern 160a' and the fourth photoresist layer pattern 160b' as a mask to form a third conductive layer on the pixel portion. A common electrode 108 made of is formed.

In this case, the third conductive layer may be patterned by wet etching.

In this case, the common electrode 108 may be formed in a single pattern over the entire pixel portion except for the first contact hole 140a.

In addition, the common electrode 108 according to the exemplary embodiment of the present invention may be formed at a predetermined distance from the pixel electrode so as not to be shorted with the pixel electrode to be formed in the drain contact hole. That is, the common electrode 108 is formed to be spaced apart from the edge of the second interlayer insulating layer 115c through the aforementioned secondary patterning. In addition, the common electrode 108 is formed to be spaced apart from the edges of the third photoresist pattern 160a' and the fourth photoresist pattern 160b'. As a result, it can be located at a certain distance from the pixel electrode.

Next, as shown in FIG. 5D, a first protective layer 115d and a second protective layer 115e are formed on the entire surface of the array substrate 110 on which the common electrode 108 is formed.

Thereafter, by selectively patterning using a photolithography process (a fourth mask process), a second contact hole exposing a part of the drain electrode 123 is formed in the first contact hole.

At the same time, a third contact hole and a fourth contact hole are formed in the data pad portion and the gate pad portion, respectively, exposing portions of the data pad line 117p and the gate pad line 116p.

Next, after the ashing process is performed, a fourth conductive layer is deposited on the entire surface of the array substrate 110 while the ashed photoresist layer pattern remains.

Thereafter, the pixel electrode 118 electrically connected to the drain electrode 123 through a second contact hole (ie, a drain contact hole) in the pixel portion by selectively removing the fourth conductive layer and the photosensitive layer pattern through a lift-off process. ) To form.

At the same time, the data pad electrode 127p and the gate pad electrode electrically connected to the data pad line 117p and the gate pad line 116p through a third contact hole and a fourth contact hole respectively in the data pad portion and the gate pad portion. (126p) is formed.

At this time, the square-shaped pixel electrode 118 includes a plurality of slits 118s in the pixel electrode 118 to generate a fringe field together with the common electrode 108.

In this case, an insulating layer pattern 115 made of an insulating material constituting the second protective layer 115e is formed in the slit 118s of the pixel electrode 118 and disposed in a direction parallel to the slit 118s.

As described above, the fourth mask process uses a half-tone mask and a lift-off process, and at the same time as the formation of the pixel electrode 118, the data pad electrode 127p, and the gate pad electrode 126p, 4 Protective layers 115d and 115e in which contact holes are formed are formed.

Hereinafter, the fourth mask process will be described in detail with reference to the drawings.

7A to 7H are cross-sectional views specifically showing the fourth mask process shown in FIG. 5D.

And, FIG. 8 is a cross-sectional view showing an enlarged portion A of the array substrate shown in FIG. 7G.

As shown in FIG. 7A, a first passivation layer 115d and a second passivation layer 115e are formed on the entire surface of the array substrate 110 including the inside of the first contact hole.

The first passivation layer 115d and the second passivation layer 115e may be formed of an inorganic insulating layer such as a silicon nitride layer or a silicon oxide layer.

In this case, the second protective layer 115e may be formed to secure a penetration path of a stripper for smoothly forming the pixel electrode 118 through a lift-off process to be described later. In this case, it is preferable to make the thickness d2 thicker than the thickness d1 of the fourth conductive layer 150 for the pixel electrode (see FIGS. 7A and 8 ).

In addition, the second protective layer 115e may be formed to be porous by using sputtering. Accordingly, since the etching speed is faster than that of the lower first passivation layer 115c, an under cut may be formed under the photoresist pattern.

Next, as shown in FIG. 7B, a photosensitive film 260 made of a photosensitive material such as a photoresist is formed on the array substrate 110 on which the second protective layer 115e is formed.

Thereafter, light is selectively irradiated to the photosensitive layer 260 through the half-tone mask 270 according to the embodiment of the present invention.

At this time, in the half-tone mask 270, a first transmission region (I) that transmits all the irradiated light, a second transmission region (II) that transmits only part of the light and blocks part of the light, and a blocking region that blocks all the irradiated light. (III) is provided, and only light that has passed through the half-tone mask 270 is irradiated onto the photosensitive film 260.

Subsequently, after the photosensitive film 260 exposed through the half-tone mask 270 is developed, as shown in FIG. 7C, all of the light is blocked through the blocking region III and the second transmission region II. The first photoresist pattern 260a to the sixth photoresist pattern 260f of a predetermined thickness remains in the partially blocked area, and the photoresist layer is completely removed in the first transmission area I through which all the light is transmitted, so that the second protective layer (115e) The surface is exposed.

At this time, the first photoresist pattern 260a to the third photoresist pattern 260c formed in the blocking region III is the fourth photoresist pattern 260d to the sixth photoresist pattern 260f formed through the second transmission region II. It is formed thicker. In addition, the photoresist film is completely removed in the region where all the light is transmitted through the first transmission region (I). This is because a positive type photoresist is used, and the present invention is not limited thereto, and a negative type photoresist is used. It is okay to do it.

Next, as shown in FIG. 7D, using the first photoresist pattern 260a to the sixth photoresist pattern 260f as a mask, the first interlayer insulating layer 115b and the first protective layer 115d formed under the first photoresist layer pattern 260a to the sixth photoresist layer pattern 260f ) And a partial region of the second passivation layer 115e, a second contact hole 140b exposing a portion of the drain electrode 123 is formed in the first contact hole.

At the same time, the gate insulating layer 115a, the first interlayer insulating layer 115b, and the first protective layer 115d are formed under the first photoresist pattern 260a to the sixth photoresist pattern 260f as a mask. When a partial region of the second passivation layer 115e is selectively removed, a third contact hole 140c exposing a portion of the data pad line 117p and the gate pad line 116p to the data pad portion and the gate pad portion, respectively. And a fourth contact hole 140d.

Thereafter, when the ashing process of removing a part of the thickness of the first photoresist pattern 260a to the sixth photoresist pattern 260f is performed, as shown in FIG. 7E, the fourth photoresist pattern of the second transmission region II is performed. To the sixth photoresist pattern are completely removed.

At this time, the first photoresist pattern to the third photoresist pattern are the seventh photoresist pattern 260a' to the ninth photoresist pattern 260c' from which the thickness of the fourth to sixth photoresist pattern has been removed. It remains only in the area corresponding to. At this time, the first transmission region I and the second transmission region II in which substantially the seventh photoresist pattern 260a' to the ninth photoresist pattern 260c' do not remain are pixelated through a lift-off process to be described later. It refers to a region in which an electrode, a data pad electrode, and a gate pad electrode are to be formed.

Next, as shown in FIG. 7F, a partial region of the second protective layer 115e under the second protective layer 115e is selectively removed through wet etching, so that the second protective layer 115e is formed under the seventh photoresist pattern 260a'. An insulating layer pattern 115 made of an insulating material constituting a is formed.

At this time, the insulating layer pattern 115 is over-etched by ΔP to the side so as to have a width narrower than the width of the seventh photoresist layer pattern 260a' thereon to secure the penetration path of the striper (Fig. 7F). And Fig. 8).

Next, as shown in FIG. 7G, a fourth conductive layer 150 is deposited on the entire surface of the array substrate 110 while the seventh photoresist pattern 260a' to the ninth photoresist pattern 260c' remain. .

In this case, the fourth conductive layer 150 may be made of a transparent conductive metal material having excellent transmittance such as indium-tin-oxide or indium-zinc-oxide to form the pixel electrode, the data pad electrode, and the gate pad electrode.

Thereafter, a predetermined heat treatment process may be performed, which is to facilitate lift-off by forming cracks on the surfaces of the 7th photoresist pattern 260a' to the ninth photoresist pattern 260c' during the lift-off process to be described later. to be. Heat treatment can be performed at around 200°C using an oven.

Here, referring to FIG. 7G, as described above, the common electrode 108 may be electrically insulated from the fourth conductive layer 150 for a pixel electrode because it is spaced apart from the edge of the second interlayer insulating layer 115c.

At this time, as described above, the insulating layer pattern 115 has the thickness d1 of the fourth conductive layer 150 for the pixel electrode in order to secure a penetration path of the stripper for smoothly forming the pixel electrode through a lift-off process to be described later. It is preferable to form the thickness (d2) thicker than) (see FIG. 8).

Next, as shown in FIG. 7H, the seventh photoresist pattern to the ninth photoresist pattern are removed through a lift-off process. At this time, portions other than the first and second transmission regions I and II are removed. The remaining fourth conductive film is removed together with the seventh to ninth photosensitive film patterns.

As a result, a pixel electrode 118 formed of a fourth conductive film in the pixel portion of the array substrate 110, that is, a pixel region, and electrically connected to the drain electrode 123 through the second contact hole is formed.

At this time, a plurality of slits 118s are included in the pixel electrode 118, and the slits 118s of the pixel electrode 118 are made of an insulating material, and the slits ( The insulating layer pattern 115 is disposed in a direction parallel to 118s). However, the present invention is not limited thereto, and the insulating layer pattern 115 may contact the pixel electrode 118.

At the same time, a data pad electrode electrically connected to the data pad line 117p and the gate pad line 116p through a third contact hole and a fourth contact hole in the data pad portion and the gate pad portion of the array substrate 110, respectively. 127p) and a gate pad electrode 126p are formed.

The array substrate of the embodiment of the present invention configured as described above is bonded to face the color filter substrate by a sealant formed on the outer edge of the image display area, and at this time, a color filter for realizing red, green, and blue colors is formed on the color filter substrate. Has been.

In this case, the color filter substrate and the array substrate are bonded to each other through an alignment key formed on the color filter substrate or the array substrate.

The present invention can be used not only for a liquid crystal display, but also for other display devices manufactured using a thin film transistor, for example, an organic light emitting display device in which organic light emitting diodes (OLEDs) are connected to a driving thin film transistor.

Although many items are specifically described in the above description, this should be construed as an example of a preferred embodiment rather than limiting the scope of the invention. Therefore, the invention should not be determined by the described embodiments, but should be determined by the claims and equivalents to the claims.

108: common electrode 115: insulating film pattern
115a: gate insulating layer 115b, 115c: interlayer insulating layer
115d, 115e: protective layer 118: pixel electrode
118s: slit 121: gate electrode
122: source electrode 123: drain electrode
124: active layer

Claims (11)

Forming a gate electrode in the pixel portion of the first substrate through a first mask process;
Forming a gate insulating layer on the gate electrode;
Forming an active layer, a source electrode, and a drain electrode in the pixel portion of the first substrate through a second mask process;
Forming a first interlayer insulating layer and a second interlayer insulating layer on the active layer, the source electrode, and the drain electrode;
Forming a first contact hole exposing the first interlayer insulating layer on the drain electrode through a third mask process, and forming a common electrode on the second interlayer insulating layer of the pixel portion;
Forming a first protective layer and a second protective layer on the common electrode; And
Forming a pixel electrode having a plurality of slits in a pixel portion of the first substrate through a fourth mask process, and forming an insulating layer pattern made of the second protective layer in the slit of the pixel electrode,
The third mask process
Forming a third conductive film on the second interlayer insulating layer,
Forming a first photoresist layer pattern and a second photoresist layer pattern on the third conductive layer,
Forming a conductive layer pattern made of the third conductive layer on the pixel portion by selectively patterning a partial region of the third conductive layer using the first photoresist layer pattern and the second photoresist layer pattern as a mask, and
A first contact for exposing a portion of the first interlayer insulating layer on the drain electrode by selectively patterning a partial region of the second interlayer insulating layer using the first photoresist layer pattern, the second photoresist layer pattern, and the conductive layer pattern as a mask Including the step of forming a hole,
The third conductive layer is patterned using wet etching, and during the wet etching, a portion of the conductive layer pattern is over-etched to retreat from the side surfaces of the first photoresist pattern and the second photoresist pattern. A method of manufacturing a liquid crystal display device. The method of claim 1, wherein the data pad portion and the second interlayer insulating layer of the gate pad portion of the first substrate are removed using the third mask process to expose the first interlayer insulating layer of the data pad portion and the gate pad portion. A method of manufacturing a fringe field type liquid crystal display device, characterized in that it further comprises a step. delete delete The method of claim 1, wherein the second interlayer insulating layer is patterned using dry etching, and when the dry etching is performed, a portion of the first photoresist layer pattern and the second photoresist layer pattern are removed to form the first photoresist layer pattern and the second photoresist layer pattern. A method of manufacturing a fringe field type liquid crystal display device, comprising forming a third photoresist layer pattern and a fourth photoresist layer pattern having a smaller width and thickness. The fringe field type liquid crystal of claim 5, wherein a common electrode made of the conductive layer is formed on the pixel portion by secondarily patterning the conductive layer pattern using the third photoresist layer pattern and the fourth photoresist layer pattern as a mask. Method of manufacturing a display device. The method of claim 1, wherein the fourth mask process
Forming a photoresist pattern on the second protective layer;
Forming a second contact hole exposing a portion of the drain electrode in the first contact hole by selectively patterning partial regions of the first interlayer insulating layer, the first passivation layer, and the second passivation layer using the photoresist pattern as a mask The step of doing;
Removing part of the thickness of the photoresist pattern through an ashing process;
Selectively patterning a partial region of the second passivation layer to form an insulating layer pattern under the ashed photosensitive layer pattern;
Forming a conductive film thereon while the ashed photosensitive film pattern remains; And
And forming a pixel electrode made of the conductive layer in the pixel portion by selectively removing the ashed photoresist layer pattern and the conductive layer over the ashed photoresist layer pattern through a lift-off process. A method of manufacturing a liquid crystal display device. A gate electrode disposed in the pixel portion;
A gate insulating layer over the gate electrode;
An active layer, a source electrode, and a drain electrode disposed on the gate insulating layer;
A first interlayer insulating layer and a second interlayer insulating layer over the active layer, the source electrode, and the drain electrode;
A first contact hole through which a portion of the second interlayer insulating layer is removed to expose a portion of the first interlayer insulating layer above the drain electrode;
A common electrode disposed on the second interlayer insulating layer;
A first protective layer over the common electrode;
A second contact hole located in the first contact hole, and partially exposing a portion of the drain electrode by removing a partial region of the first passivation layer;
A pixel electrode having a plurality of slits and electrically connected to the drain electrode through the second contact hole; And
And an insulating layer pattern disposed in the slit of the pixel electrode,
The fringe field type liquid crystal display device, wherein the first protective layer is interposed between a pixel electrode in the second contact hole and a side surface of the second interlayer insulating layer. 9. The fringe field type liquid crystal display device of claim 8, wherein the common electrode is positioned at a predetermined distance from an edge of the second interlayer insulating layer. 9. The fringe field type liquid crystal display device of claim 8, wherein the insulating layer pattern is disposed in a direction parallel to the slit while maintaining a predetermined distance from the pixel electrode. The method of claim 8, wherein a second protective layer made of an insulating material constituting the first protective layer and the insulating layer pattern is stacked on the data pad part and the gate pad part while the second interlayer insulating layer is removed. Fringe field type liquid crystal display device, characterized in that.

Images