KR102173090B1 - Selective-transferring method of carrier substrate, manufacturing method of display apparatus using this same and display apparatus manufactured by that method - Google Patents

Abstract

The present invention relates to a manufacturing method of a display apparatus, which are able to form three types of sub-RGB pixel CSPs on each wafer, selectively transcribe by using a carrier substrate, and selectively and consecutively transcribe the same on a display panel; and a display apparatus manufactured thereby. According to the present invention, a selective transcribing method of a carrier substrate comprises: an RGB sub-pixel forming step of forming sub-pixels for each R sub-pixel, G sub-pixel, and B sub-pixel on each wafer; a dicing step of dicing each wafer with the RGB sub-pixels formed thereon for each sub-pixel; and a transcription step of selectively transcribing a sub-pixel CSP array in a column direction or a row direction to the carrier substrate through the carrier substrate having an opening hole in a column direction or a row direction. Accordingly, it is possible to manufacture the display apparatus by using the same.

Description

TECHNICAL FIELD [0001] A method for selectively transferring a carrier substrate, a method for manufacturing a display device using the same, and a display device manufactured by the method TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method of manufacturing a display device and a display device, and more specifically, after forming three types of sub-RGB pixel CSPs on each wafer, selectively transferring them using a carrier substrate, and re-transferring them to a display panel. It relates to a method of manufacturing a display device capable of selectively sequentially transferring to and to a display device manufactured thereby.

Light Emitting Diode (LED) is one of light emitting devices that emit light when current is applied. Light-emitting diodes can emit high-efficiency light with low voltage, so they have excellent energy saving effects.

Recently, the problem of luminance of light emitting diodes has been greatly improved, and thus, it has been applied to various devices such as backlight units of liquid crystal display devices, electric signs, displays, and home appliances.

The size of a micro light emitting diode (μ-LED) is very small, ranging from 1 to 100 μm, and approximately 25 million or more pixels are required to implement a 40-inch display device.

Therefore, there is a problem in that it takes at least one month in time by a simple pick & place method to make one 40-inch display device.

Existing micro light-emitting diodes (μ-LEDs) are manufactured in plural on a sapphire substrate, and then, by a mechanical transfer method, pick & place, the micro light-emitting diodes are one by one on a glass or flexible substrate. Is transferred.

Since the micro light emitting diodes are picked up one by one and transferred, it is referred to as a 1:1 pick-and-place transfer method.

However, since the micro light emitting diode chip fabricated on the sapphire substrate is small in size and thin, the chip is damaged, the transfer fails, or the chip is aligned during the pick-and-place transfer process of transferring the micro light emitting diode chips one by one. There is a problem such as alignment failure or a chip tilt.

In addition, there is a problem that the time required for the transfer process takes too long.

Republic of Korea Patent Publication 10-2019-0096256

The present invention provides a method of manufacturing a display device capable of selectively and sequentially transferring a plurality of RGB subpixel CSPs to a display panel using a carrier substrate.

In addition, it provides a method of manufacturing a display device capable of rapidly manufacturing a micro LED-based display device and minimizing transfer errors.

In addition, it provides a method of manufacturing a display device capable of manufacturing a display device having a variety of sizes and pitches between pixels.

In addition, a method of manufacturing a display device capable of using a wafer including as many RGB pixels as possible on a limited area regardless of the resolution of the display device is provided.

In addition, a method of manufacturing a display device capable of rapidly manufacturing a large-area display device is provided.

In addition, there is provided a display device manufactured by a method of manufacturing a display device.

The problem to be solved of the present invention is not limited to the problems mentioned above, and other problems that are not mentioned can be clearly understood by those of ordinary skill in the technical field to which the present invention belongs from the following description. will be.

The selective transfer method of a carrier substrate according to the present invention includes: forming a sub-pixel for each of R sub-pixels, G sub-pixels and B sub-pixels on each wafer; Dicing each wafer on which the RGB sub-pixels are formed for each sub-pixel; And a transfer step of selectively transferring the subpixel CSP array in a row or column direction to the carrier substrate through a carrier substrate having opening holes in a row or column direction. It may include, and it is possible to manufacture a display device using this.

Here, the carrier substrate may include an R carrier substrate for R subpixel CSP array transfer, a G carrier substrate for G subpixel CSP array transfer, and a B carrier substrate for B subpixel CSP array transfer.

Here, the opening holes of the R carrier substrate are 2 rows or columns, 3 rows or columns, 5 rows or columns, 6 rows or columns of R subpixels formed on the wafer, ... , 3n+2 (n is 0, 1, 2, ...) is formed in a row or column, 3n+3 row or column, and the opening hole of the G carrier substrate is one row or column of G subpixels formed on the wafer, 3 Rows or columns, 4 rows or columns, 6 rows or columns,… , 3n+1 rows or columns, 3n+3 rows or columns, and the opening holes of the B carrier substrate are 1 row or column, 2 rows or columns, 4 rows or columns, 5 rows of B sub-pixels formed on the wafer Or heat,… , 3n+1 rows or columns, and 3n+2 rows or columns.

Here, the opening hole of the carrier substrate may be formed to correspond to a pitch interval of the R sub-pixel, G sub-pixel, and B sub-pixel of the wafer.

Here, it is preferable that an adhesive material is applied to a region of the carrier substrate in which an opening hole is not formed.

In addition, a method of manufacturing a display device using a method for selectively transferring a carrier substrate according to the present invention includes: forming subpixels for each of R subpixels, G subpixels, and B subpixels on each wafer; Dicing each wafer on which the RGB sub-pixels are formed for each sub-pixel; A primary transfer step of selectively transferring the subpixel CSP array in a row or column direction to the carrier substrate through a carrier substrate having opening holes in a row or column direction; And a secondary transfer step of sequentially transferring the subpixel CSP array transferred to the carrier substrate for each RGB subpixel to a display panel.

Here, the step of forming the RGB sub-pixels includes: growing a plurality of epits on one surface of the wafer; Forming a pad on the epitaxial; And forming a protective layer for passivating the epi and the pad, wherein the pad is exposed to the outside of the protective layer.

Here, the second transfer step may include applying a solder paste to a plurality of pads of the display panel; A soldering step of contacting and soldering the pad of the sub-pixel CSP selectively transferred to the carrier substrate to the applied solder paste; And separating and separating the carrier substrate from the display panel.

Here, in the second transfer step, any one of the arrays of the R sub-pixels, G sub-pixels, and B sub-pixels is selectively transferred to respective positions of the display panels different from each other, and the different displays It is preferable that the subpixel array transferred to each of the panels and the subpixel array other than the subpixel array are sequentially transferred adjacent to each other.

Here, in the step of forming the RGB sub-pixels, the step of forming an extended pad by expanding each pad of the RGB pixel may further include.

Here, an area moving step of increasing a pad spacing by moving a pair of pads facing each other on the display panel to the left and right may further include.

Here, each of the R sub-pixel, G sub-pixel, and B sub-pixel is formed in a sub-pixel CSP (Chip Scale Package) form, and the sub-pixel CSP is the R sub-pixel, G sub-pixel, and B sub-pixel are the display panel Can be transferred to and constitute one pixel CSP.

Here, each of the R sub-pixel, G sub-pixel, and B sub-pixel is formed in a sub-pixel CSP (Chip Scale Package) form, and the sub-pixel CSP includes the R sub-pixel, G sub-pixel, and B sub-pixel in rows and columns. A sub-pixel CSP array arranged in a direction may be formed, and the sub-pixel CSP array may be simultaneously transferred to the display panel to form one pixel CSP array.

Here, the carrier substrate may include an R carrier substrate for R subpixel CSP array transfer, a G carrier substrate for G subpixel CSP array transfer, and a B carrier substrate for B subpixel CSP array transfer.

Here, the opening holes of the R carrier substrate are 2 rows or columns, 3 rows or columns, 5 rows or columns, 6 rows or columns of R subpixels formed on the wafer, ... , 3n+2 (n is 0, 1, 2, ...) is formed in a row or column, 3n+3 row or column, and the opening hole of the G carrier substrate is one row or column of G subpixels formed on the wafer, 3 Rows or columns, 4 rows or columns, 6 rows or columns,… , 3n+1 rows or columns, 3n+3 rows or columns, and the opening holes of the B carrier substrate are 1 row or column, 2 rows or columns, 4 rows or columns, 5 rows of B sub-pixels formed on the wafer Or heat,… , 3n+1 rows or columns, and 3n+2 rows or columns.

Here, it is preferable that the opening hole of the carrier substrate is formed corresponding to the pitch interval of the R sub-pixel, G sub-pixel, and B sub-pixel of the wafer.

Here, it is preferable that an adhesive material is applied to a region of the carrier substrate in which an opening hole is not formed.

In addition, a method of manufacturing a display device using a method for selectively transferring a carrier substrate according to the present invention includes: forming subpixels for each of R subpixels, G subpixels, and B subpixels on each wafer; Dicing each wafer on which the RGB sub-pixels are formed for each sub-pixel; A first carrier that selectively transfers the R sub-pixel CSP array to the R sub-pixel CSP array using an adhesive material in a region where the opening holes are not formed through a first carrier substrate having opening holes in a row or column direction A substrate transfer step; A second carrier for selectively transferring the G sub-pixel CSP array using an adhesive material in a region where the opening holes are not formed through a second carrier substrate having opening holes in a row or column direction A substrate transfer step; A third carrier that selectively transfers the B sub-pixel CSP array using an adhesive material in a region where the opening holes are not formed through a third carrier substrate having opening holes in a row or column direction. A substrate transfer step; And a display panel transfer step of sequentially transferring the subpixel CSP array transferred to the first to third carrier substrates to a display panel.

In addition, the display device according to the present invention can be manufactured by a method of manufacturing a display device using the above-described selective transfer method of a carrier substrate.

Using the method of manufacturing a display device according to the embodiment, RGB sub-pixels are produced on each wafer in CSP format, allowing primary selective sequential transfer using a carrier substrate, and 2 Secondary selective sequential transcription is possible.

In addition, the manufacturing method of the display device according to the embodiment does not control the micro-level light emitting devices one by one, and can quickly transfer a plurality of light emitting devices to the display panel at once, thus significantly reducing the manufacturing cost and time of the display device. There is an advantage.

In addition, the method of manufacturing the display device according to the embodiment has an advantage of maximizing a transfer success rate because it uses a large difference in adhesion between transfer media, not a method of controlling physical force or adhesion such as electrostatic attraction.

In addition, when the size of the light emitting area of the light emitting device is 100 μm or less, the light efficiency rapidly decreases due to epi damage caused by dicing or the like. On the other hand, the present invention has an advantage that the light efficiency does not deteriorate because the transfer is performed in units of sub-pixel CSP rather than in units of light emitting diode chips.

More specifically, when the dicing process is performed, damage may be caused by the laser. The percentage (%) occupied by the damaged portion of the light emitting area varies according to the size of the light emitting area Epi of the light emitting diode.

That is, the ratio of the length of the surface circumference to the area increases as the size of the light emitting area decreases. For example, when the size of the light emitting area is 300x300um, the surface-to-area ratio is 1, and 50x50um is about 6 times larger. Therefore, the influence of defects on the surface can be at least 6 times greater.

As a result, the luminous efficiency drops sharply. On the other hand, the present invention is not dicing in units of chips, but dicing in units of sub-pixels regardless of the EPI area. Therefore, there is an advantage that there is little reduction in light efficiency at the pixel level.

In addition, there is an advantage in that a display device having various sizes and various pitches between sub-pixels can be manufactured.

In addition, since each wafer in which as many RGB subpixels are formed on a limited area regardless of the resolution of the display device is used, it is possible to reduce the cost of manufacturing a wafer and does not require a color conversion layer forming process.

In addition, when manufacturing a large-area display device, there is an advantage in that the transfer method can be rapidly manufactured by changing the position and repeatedly executing the transfer method.

1 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention.
2 is a view in which RGB subpixels are formed on each wafer according to an embodiment of the present invention.
3 is a process chart of growing each RGB Epi on each wafer according to an embodiment of the present invention.
4 is a process diagram of dicing each of RGB subpixels formed on each wafer according to an embodiment of the present invention in units of one subpixel CSP.
5 are cross-sectional views for comparing a conventional sub-pixel CSP having an unexpanded pad and a sub-pixel CSP having an extended pad.
6 is a front view showing a conventional conventional sub-pixel CSP array having a pad formed on a wafer.
7 is a front view showing that a sub-pixel CSP array having an extended pad according to an embodiment of the present invention is formed on a wafer.
8 to 10 are diagrams showing the structure of a carrier substrate for selectively transferring the subpixel CSP array shown in FIG. 1 by a carrier substrate.
11 to 13 are views for explaining in detail a step of selectively sequentially transferring to a wafer, a carrier substrate, and a display panel on which an R (Red) sub-pixel CSP array is formed.
14 to 16 are views for explaining in detail a step of selectively sequentially transferring to a wafer, a carrier substrate, and a display panel on which a green (G) sub-pixel CSP array is formed.
17 to 19 are views for explaining in detail a step of selectively sequentially transferring to a wafer, a carrier substrate, and a display panel on which a B (Blue) sub-pixel CSP array is formed.
20 is a view showing a comparison before and after movement of an electrode pad of a display panel.
21 is a diagram for explaining in detail a step of transferring a subpixel CSP array having an extended pad transferred to a carrier substrate to a display panel.

In the description of the embodiment, in the case of being described as being formed on the “top (top) or bottom (bottom)” of each component, the top (top) or bottom (bottom) of the two components directly contact each other Or one or more other components are disposed between the two components.

In addition, when expressed as "upper (upper) or lower (lower)", the meaning of not only an upward direction but also a downward direction based on one component may be included.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. Also, the size of each component does not fully reflect the actual size.

1 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention.

Referring to FIG. 1, in the method of manufacturing a display device according to an embodiment of the present invention, the step of forming a sub-pixel for each of a plurality of RGB on each wafer 110, each RGB sub-pixel into one sub-pixel Dicing the wafer with the pixel CSP (130), selectively transferring the RGB sub-pixel CSP array to the carrier substrate (150), and selectively sequentially transferring the RGB sub-pixel CSP array selectively transferred to the carrier substrate to the display panel. Including the step of transferring 170.

Steps 110, 130, 150, and 170 will be described in detail below with reference to the accompanying drawings.

2 is a view in which RGB subpixels are formed on each wafer according to an embodiment of the present invention.

In the embodiment of the present invention, three wafers each formed with RGB subpixels are described as an example, but the present invention is not limited thereto.

Referring to FIG. 2, a plurality of light-emitting elements 11R, 11G, and 11B that emit light of the same wavelength band are formed on each of the wafers 10R, 10G, and 10B.

Here, the light emitting elements 11R, 11G, and 11B may be light emitting chips that emit red, green, and blue light.

The plurality of light emitting devices 11R, 11G, and 11B may be arranged at equal intervals along a plurality of rows and columns on each wafer 10R, 10G, and 10B.

Since the light-emitting elements 11R, 11G, and 11B arranged at equal intervals are transferred to the display panel later in the row or column direction, the manufacturing cost of the light-emitting element can be reduced by efficiently utilizing the entire area of a relatively expensive wafer.

Here, each of the light emitting devices 11R, 11G, and 11B may correspond to a sub-pixel CSP (Chip Scale Package) packaged in units of one sub-pixel.

Meanwhile, after forming a plurality of RGB sub-pixels on each of the wafers 10R, 10G, and 10B, the wafer may be diced for each RGB sub-pixel and separated for each RGB sub-pixel CSP.

It is preferable that the pitch W between the RGB subpixels formed on each of the wafers 10R, 10G, and 10B is equal to the pitch between the subpixels of the display panel or is determined as a multiple of a proportional constant of a predetermined value.

3 is a process chart of growing each RGB Epi on each wafer according to an embodiment of the present invention.

Referring to FIG. 3, epis 11R, 11G, and 11B emitting predetermined light are grown on one surface of each of three wafers 10R, 10G, and 10B.

Here, the wafers 10R, 10G, and 10B may be a sapphire (Al2O3) substrate.

Protection by forming pads 14R, 14G, 14B on each of the grown epis 11R, 11G, 11B, and passivating the epis 11R, 11G, 11B and pads 14R, 14G, 14B A layer 13 is formed.

When forming the protective layer 13, it is preferable to form the pads 14R, 14G, and 14B to be exposed to the outside of the protective layer 13 in order to expand the pad area thereafter.

The pads 14R, 14G, and 14B may be manufactured in an expanded form unlike a conventional pad.

In other words, in the process of forming the pads (PAD) on the epis (11R, 11G, 11B) formed on each wafer (10R, 10G, 10B), the expanded shape of a larger size than that of a conventional general pad Can form a pad of.

In the following drawings including FIG. 3, the pads 14R, 14G, and 14B of extended sizes are shown, but the present invention is not limited thereto, and a conventional pad is used instead of the pads 14R, 14G, and 14B of the extended size. May be replaced.

In the case of using the extended size pads 14R, 14G, 14B, since the corresponding area is expanded when transferring to the electrode on the display panel, it has the advantage of preventing transfer errors and further improving the transfer speed and accuracy. In particular, the present invention Since it is possible to form each RGB sub-pixel CSP for each wafer, a surplus space that can expand the pad on the surplus area within the CSP can be formed, thereby improving the accuracy of the formation of an expanded pad and transfer through it. It has the advantage of being able to.

3 shows the cross-sectional views of the AA section and the BB section in FIG. 1, respectively, and preferably, a pair of (+) and (-) electrodes per sub-pixel are formed under the Epi layer, based on the AA section. It goes without saying that the electrode can be formed up and down, and it is also possible to form it left and right if necessary.

4 is a process diagram of dicing each of RGB subpixels formed on each wafer according to an embodiment of the present invention in units of one subpixel CSP.

Referring to FIG. 4, as shown in FIG. 3, epis and pads are formed on a wafer, and a plurality of RGB sub-pixels CSPs 100R, 100G, and 100B are formed by dicing each RGB sub-pixel CSP with a protective layer 13 formed thereon. do.

Here, there may be various methods of dicing for each RGB sub-pixel CSP (100R, 100G, 100B), but dicing may be performed using a laser as an example.

In the following drawings, one RGB sub-pixel CSP (100R, 100G, 100B) is shown as an RGB sub-pixel CSP (100R, 100G, 100B) formed in FIG. 4, but is not limited thereto. It may be an array of RGB sub-pixel CSPs 100R, 100G, and 100B diced in the column direction.

Each of the RGB sub-pixels CSPs 100R, 100G, and 100B may have a flip chip structure that does not require a wire.

Electrical connection is possible with the pad 14 instead of a wire, and each of the RGB sub-pixels CSPs 100R, 100G, and 100B may emit light of various colors according to an external control signal through the pad 14.

CSP (Chip Scale Package) of one RGB sub-pixel CSP (100R, 100G, 100B) is a generic term for a small package close to the size of a chip, and there is no wire for electrical connection with a lead frame that protects the appearance of the chip. It is a package that is close to the size of a chip.

In particular, in the present invention, each of the RGB sub-pixels CSPs 100R, 100G, and 100B may be a small package of a new concept manufactured in the form of a CSP by configuring sub-pixels for R, G, and B.

The R sub-pixel 100R, G sub-pixel 100G, and B sub-pixel 100B may constitute one pixel CSP.

One pixel CSP can function as one pixel that emits various colors in a display panel to be described later, and a plurality of RGB sub-pixels CSP (100R, 100G, 100B) are selectively arranged on a carrier substrate in a row and column direction. A pixel CSP array may be formed by being transferred and arranged, and a pixel CSP array arranged on a carrier substrate may be selectively transferred to a display panel to be described later.

FIG. 5 is a cross-sectional view illustrating a pixel CSP having a conventional general pad in which the pad is not extended and a pixel CSP having an extended pad, and FIG. 6 is a diagram illustrating that a pixel CSP array having a conventional general pad is formed on a wafer. Fig. 7 is a front view showing that a pixel CSP array having an extended pad is formed on a wafer.

FIG. 5 shows Section B-B of FIG. 1, and shows a cross-sectional structure of one sub-pixel CSP.

Comparing FIGS. 5A and 5B and FIG. 6 and FIG. 7, the pads 14R and 14R' expanded in the wafer manufacturing process are conventional unused within one pixel CSP 100'. By utilizing the redundant area, it is designed in an expanded shape with RGB pixels in mind, and is enlarged compared to the pads 14r and 14r' of the existing chip, so that the cross-sectional area can be enlarged.

In particular, in the case of micro-unit LED chips, the pixel unit is 30㎛ * 30㎛ to 100㎛ * 100㎛, so the width and length of the pads are also very fine, and electrical open occurs during the surface mounting process of these as the substrate of the display panel. As a result, the defective rate is inevitably increased.

On the other hand, by performing the surface mounting process on the display panel in units of pixel CSP that can be expanded, the electrical connection process of micro LEDs in tens of um area is scaled up to the electrical connection process of pixel CSPs in several hundreds of um area. It can minimize the defects of the back.

In addition, it is possible to minimize electrical defects by increasing an alignment margin between the pixel CSP pad and the pad of the display panel during the surface mounting process on the display device, and to quickly manufacture a large-area display device.

Next, as shown in FIG. 4, a selective transfer process for transferring the diced sub-pixel arrays in the form of RGB sub-pixel CSPs 100R, 100G, and 100B on each wafer to the display panel will be described.

The following drawings are described in terms of row (horizontal) arrangement in a sub-pixel CSP array arranged in a matrix on the wafer of FIG. 1.

The sub-pixel CSP array formed on each wafer is primarily selectively transferred by the carrier substrate, and the selectively primary-transferred sub-pixel CSP array is selectively transferred to the display panel secondarily, and one pixel CSP is sequentially transferred. It becomes possible to manufacture an arrayed display panel.

8 to 10 are diagrams showing the structure of a carrier substrate for selectively transferring the subpixel CSP array shown in FIG. 1 by a carrier substrate.

8 is a structure of a carrier substrate 200R for primary selective transfer from an R wafer on which an R subpixel array is formed, and FIG. 9 is a carrier substrate 200G for primary selective transfer from a G wafer on which a G subpixel array is formed. 10 is a structure of a carrier substrate 200B for primary selective transfer from a B wafer on which a B sub-pixel array is formed.

8 to 10 show structures of respective carrier substrates 200R, 200G, and 200B for selectively transferring in a column order in an R, G, and B subpixel CSP array formed on a wafer.

For example, in the case of sequentially selectively transferring the rows of the R wafer, the G wafer, and the B wafer first, the carrier substrate 200R is 1 row, 4 rows, 7 rows... Selective transfer is possible in order, and the carrier substrate (200G) has 2 rows, 5 rows, 8 rows… In this order, the carrier substrate 200B is 3 rows, 6 rows, 9 rows... Subpixels formed on each wafer may be selectively transferred in order.

Secondly, when the same rows of R wafer, G wafer, and B wafer are selectively transferred, each of the carrier substrates 200R, 200G, 200B is 1 row, 4 row, 7 row… Selective transfer is possible in order, followed by 2nd, 5th, 8th ... In that order, then row 3, row 6, row 9… In order, the subpixels formed on the wafer may be selectively transferred without leaving until all of them are transferred.

Assuming the first example case, the transfer method will be described below (only from column 1 to column 6 (first RGB sub-pixel CSP array, second RGB sub-pixel CSP array) of sub-pixels will be described as examples, and beyond (third , 4th, ..., nth RGB sub-pixel CSP array).

Referring to FIG. 8, (A) is a front view, (B) is an XX cross-sectional view of (A), and (C) is a drawing on which an adhesive material is applied in (B), and selectively transferred to the carrier substrate 200R. Opening holes 36 are formed in the remaining row portions except for the portions (row 1, row 4, …) (35-SP1, 35-SP4,…).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200R, and when the adhesive material 37 is applied to the surface of the carrier substrate 200R, the adhesive material is not applied to the opening hole 36. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area without the opening hole 36 so that only the corresponding heat can be picked up.

Referring to FIG. 9, (A) is a front view, (B) is an XX cross-sectional view of (A), and (C) is a drawing on which an adhesive material is applied in (B), and is selectively transferred to the carrier substrate 200G. Opening holes 36 are formed in the remaining row portions except for the portions (2nd row, 5th row, ...) (35-SP2, 35-SP5, ...).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200G, and when the adhesive material 37 is applied to the surface of the carrier substrate 200G, the adhesive material is not applied to the opening hole 36. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area without the opening hole 36 so that only the corresponding heat can be picked up.

Referring to FIG. 10, (A) is a front view, (B) is an XX cross-sectional view of (A), and (C) is a drawing on which an adhesive material is applied in (B), and selectively transferred to the carrier substrate 200B. Opening holes 36 are formed in the remaining row portions except for the portions (3 rows, 6 rows, ...) (35-SP3, 35-SP6, ...).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200B, and when the adhesive material 37 is applied to the surface of the carrier substrate 200B, the adhesive material is not applied to the opening hole 36. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area without the opening hole 36 so that only the corresponding heat can be picked up.

Next, a process of primary transfer from a wafer to a carrier substrate and a process of secondary transfer from a carrier substrate to a display panel using the prepared carrier substrates 200R, 200G, and 200B of FIGS. 8 to 10 will be described.

11 to 13 are steps of selectively sequentially transferring to a wafer on which an R (Red) sub-pixel CSP array is formed, a carrier substrate and a display panel, and FIGS. 14 to 16 are a wafer on which a G (Green) sub-pixel CSP array is formed, and a carrier substrate. And selectively sequentially transferring to a display panel, and FIGS. 17 to 19 illustrate a step of selectively sequentially transferring to a wafer, a carrier substrate, and a display panel on which a B (Blue) sub-pixel CSP array is formed.

First, FIGS. 11 to 13 are steps of selectively sequentially transferring to a wafer, a carrier substrate, and a display panel on which an R (Red) sub-pixel CSP array is formed.

11 shows a process in which the R subpixel CSP array is first transferred from the R wafer to the carrier substrate, where (A) is a front view of the R wafer 10R, and (B) is the R using the carrier substrate 200R. It is a front view of the 1st row and 4th row of the wafer 10R which was primary transferred, and (C) shows the XX cross-sectional view of (B).

Referring to FIG. 11, the R wafer 10R of (A) is in a state that has undergone the processes of FIGS. 3 and 4 (here, the process of FIG. 5 may be included), and the carrier substrate 200R of FIG. When the carrier substrate 200R is separated after aligning and contacting the wafer 10R, the R subpixel arrays in the first and fourth rows of the R wafer 10R in (A) are picked up and transferred to become empty, and (B)/( As shown in C), the first and fourth R sub-pixel arrays 100R-SP1 and 100R-SP4 are transferred to the carrier substrate 200R.

The step 150 of transferring the pixel CSP array to the carrier substrate may be referred to as'primary transfer'.

Here, the carrier substrate 200R may also be referred to as a'transfer adhesive member', and an adhesive or adhesive is applied to these materials such as PET, PP, PE, PS resin plates, or these materials have a thin thickness in the form of a tape. While having, an adhesive or adhesive may be applied to one side thereof.

The carrier substrate 200R may have a predetermined ductility, and the carrier substrate 200R having a predetermined ductility may be made of a material that can be easily bent by an external force.

If the carrier substrate 200R is a material that can be easily bent, the transfer efficiency can be further improved compared to the case where the carrier substrate 200R is a material that is not easily bent.

When the carrier substrate 200R is made of a material that is not easily bent, it is difficult to lift the carrier substrate at once after attaching each of the sub-pixels CSP (100R-SP1, 100R-SP2, 100R-SP3) to the carrier substrate. The reason is that the adhesive force between each of the sub-pixels CSP 100R-SP1, 100R-SP2, and 100R-SP3 and the carrier substrate 200R is significant.

However, if the carrier substrate 200R is a material that can be easily bent, after attaching each sub-pixel CSP (100R-SP1, 100R-SP2, 100R-SP3) to the carrier substrate 200R, the work of the carrier substrate 200R If only the side portion is raised upward, the number of pixel CSPs attached only to that portion is relatively small, so that the entire carrier substrate 200R can be easily lifted with little force.

In addition, the carrier substrate 200R may be made of a transparent material. If the carrier substrate 200R is a transparent material, when transferring each sub-pixel CSP (100R-SP1, 100R-SP2, 100R-SP3) to the carrier substrate 200R, it is possible to provide external vision for positioning and distortion. There is an advantage that can be adjusted or controlled through a system (not shown).

Meanwhile, the carrier substrate 200R may also be referred to as a first transfer medium in a method of manufacturing a display device according to an embodiment of the present invention. A first adhesive force is formed between the first transfer medium and the pixel CSP array. Specifically, the first adhesive force may be 2,000 gf/25mm to 4,000 gf/25mm. More preferably, the first adhesive force may be 3,000 gf/25mm.

12 shows a process of secondary transfer of an R subpixel CSP array from a carrier substrate to a display panel.

Referring to FIG. 12, (A) shows the pads 31-SP1… 31-SP6 of the display panel 300, and (B) is the carrier of FIG. 11B on the display panel 300 This shows a state in which the R sub-pixel array is secondarily transferred onto the display panel 300 by aligning the substrate 200R.

Pads 31-SP1… 31-SP6 are formed in rows 1 to 6 of the display panel 300, and solder pastes 33-SP1 and 33-SP4 are formed in rows 1 and 4, and the corresponding row positions Each of the R subpixels CSPs 100R-SP1 and 100R-SP4 is transferred to each other.

However, although it is shown that solder paste is formed only in the first row and the fourth row on the pads of the display panel 300, solder pastes 33-SP1… 33-SP6 may be formed in all rows. This is because the carrier substrate 200R has already selectively picked up and transferred the first row and the fourth row.

FIG. 13 is a cross-sectional view illustrating a process of transferring from a carrier substrate to a display panel in FIG. 12 in more detail.

Referring to FIG. 13, a solder paste 33 is applied on a plurality of pads 31 of the display panel 300 (FIG. 10A).

A TFT array substrate 400 may be disposed under the display panel 300.

Here, the solder paste 33 may be applied only on the first and fourth rows of the pads 31-SP1 and 31-SP4, but may be applied on the remaining pads.

One row of R sub-pixels CSP is selectively transferred to the first and fourth rows of pads (preferably pads arranged at intervals of the previous row + 3 rows), followed by the second and third row pads between rows 1 and 4 One row of the G sub-pixel CSP and one row of the B sub-pixel CSP are sequentially transferred to (the pads arranged at intervals of the previous column + 3 columns, respectively).

The solder paste 33 may be applied on the plurality of pads 31 of the display panel 300 through various methods such as screen printing, dispensing, and jetting.

Next, referring to (B) of FIG. 13, the carrier substrate 200R manufactured in FIG. 8 and the R subpixel CSPs 100R-SP1 and 100R-SP4 attached to the carrier substrate 200R are displayed on the display panel 300. ), and applied the pad 14 of the R sub-pixel CSP (100R-SP1, 100R-SP4) onto the pad 31 of the display panel 300 (33-SP1, 33-SP4) Contact with

After the pads 14 of some R sub-pixels CSPs (100R-SP1, 100R-SP4) and the pads 31 of the display panel 300 are in contact with each other through solder paste (33-SP1, 33-SP4), for example, For example, when a predetermined heat is applied using a self-aligning paste (SAP) soldering method, some of the solder particles contained in the solder pastes (33-SP1, 33-SP4) are partially R subpixel CSP It may be self-assembled between the pads 14 of (100R-SP1 and 100R-SP4) and the pads 31-SP1 and 31-SP4 of the display panel 300.

Meanwhile, the thermosetting resin included in the solder paste 33 may be cured by heat.

Next, referring to FIG. 13C, the pads 14 of some R sub-pixels CSPs 100R-SP1 and 100R-SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300 are When soldered, the carrier substrate 200R is separated.

Here, the soldering adhesive force between the pads 14 of some R sub-pixels CSPs (100R-SP1, 100R-SP4) and the pads 31-SP1 and 31-SP4 of the display panel 300 is the carrier substrate 200R and the carrier. Since the adhesion between the substrate 200R and the wafer 10R is much greater than that between the substrate 200R and the wafer 10R, only the carrier substrate 200R can be easily separated.

Next, FIGS. 14 to 16 are steps of selectively sequentially transferring to a wafer, a carrier substrate, and a display panel on which a green (G) sub-pixel CSP array is formed.

14 shows a process in which the G subpixel CSP array is first transferred from the G wafer to the carrier substrate, where (A) is a front view of the G wafer 10G, and (B) is a G using the carrier substrate 200G. It is a front view of the 1st row and 4th row of the wafer 10G primarily transferred, and (C) shows the XX cross-sectional view of (B).

Referring to FIG. 14, the G wafer 10G of FIG. 3 and FIG. 4 is passed through the process of FIG. 3 and FIG. 4 (here, the process of FIG. 5 may be included), and the carrier substrate 200G of FIG. When the carrier substrate 200G is separated after aligning and contacting the wafer 10G, the G sub-pixel arrays in the first and fourth columns of the G wafer 10G in (A) are picked up and transferred to become empty, and (B)/( As shown in C), the 2nd and 5th columns of G sub-pixel arrays 100G-SP1 and 100G-SP4 are transferred to the carrier substrate 200G.

The carrier substrate 200G may have the same material and properties as the carrier substrate 200R.

15 illustrates a process of secondary transfer of a G sub-pixel CSP array from a carrier substrate to a display panel.

Referring to FIG. 15, (A) shows pads 31-SP1… 31-SP6 of the display panel 300, and R subpixel arrays are formed in columns 1 and 4 through the processes of FIGS. 11 to 13 In the transferred state, (B) shows a state in which the G sub-pixel array is secondaryly transferred onto the display panel 300 by aligning the carrier substrate 200G of FIG. 14B on the display panel 300. Is shown.

Pads 31-SP1… 31-SP6 are formed in rows 1 to 6 of the display panel 300, and solder pastes 33-SP2 and 33-SP5 are formed in rows 2 and 5, and the corresponding row positions Each G sub-pixel CSP (100G-SP1, 100G-SP4) is transferred to each other.

However, although it is shown that solder pastes are formed only in rows 2 and 5 on the pads of the display panel 300, solder pastes 33-SP3 and 33-SP6 may be formed in rows 3 and 6. This is because the carrier substrate 200G has already selectively picked up and transferred 2nd and 5th rows.

FIG. 16 is a cross-sectional view illustrating a process of transferring from a carrier substrate to a display panel in FIG. 15 in more detail.

Referring to FIG. 16, a solder paste 33 is applied on the plurality of pads 31 of the display panel 300, and the R sub-pixel CSP array 100R-SP1, in the first row and the fourth row, has already been performed in the previous step. 100R-SP4) is located in a transferred state (Fig. 16A).

Here, the solder paste 33 may be applied only on the second and fifth rows of the pads 31-SP2 and 31-SP5, but may be applied on the remaining pads.

Next, referring to (B) of FIG. 16, the G sub-pixel CSPs 100G-SP1 and 100G-SP4 attached to the carrier substrate 200G of FIG. 14 by the carrier substrate 200G manufactured in FIG. 9 Solder paste 33-SP2, which is disposed on the display panel 300 and applied with the pad 14 of the G sub-pixel CSP (100G-SP1, 100G-SP4) on the pad 31 of the display panel 300, 33-SP5).

After the pad 14 of the G sub-pixel CSP (100G-SP1, 100G-SP4) and the pad 31 of the display panel 300 are in contact with each other through the solder pastes 33-SP2 and 33-SP5, for example, , When a predetermined heat is applied using a self-aligning paste (SAP) soldering method, the solder particles contained in the solder pastes (33-SP2, 33-SP5) become G sub-pixel CSP (100G). -It may be self-assembled between the pads 14 of the SP1 and 100G-SP4 and the pads 31-SP2 and 31-SP5 of the display panel 300.

Next, referring to FIG. 16C, the pad 14 of the G sub-pixel CSP (100G-SP1, 100G-SP4) and the pads 31-SP2 and 31-SP5 of the display panel 300 are soldered. If so, the carrier substrate 200G is separated.

Here, the soldering adhesion between the pad 14 of the G sub-pixel CSP (100G-SP1, 100G-SP4) and the pads 31-SP2 and 31-SP5 of the display panel 300 is the carrier substrate 200G and the carrier substrate. Since it is much larger than the adhesive force between 200G and the wafer 10G, only the carrier substrate 200G can be easily separated.

Next, FIGS. 17 to 19 are steps of selectively sequentially transferring to a wafer, a carrier substrate, and a display panel on which a B (Blue) sub-pixel CSP array is formed.

17 shows a process in which the B sub-pixel CSP array is first transferred from the B wafer to the carrier substrate, where (A) is a front view of the B wafer 10B, and (B) is a B using the carrier substrate 200B. It is a front view of the 1st row and 4th row of the wafer 10B primarily transferred, and (C) shows the XX cross-sectional view of (B).

Referring to FIG. 17, the B wafer 10B of FIG. 3 and FIG. 4 is passed through the process of FIG. 3 and FIG. 4 (here, the process of FIG. 5 may be included), and the carrier substrate 200B of FIG. When the carrier substrate 200B is separated after being aligned and contacted with the wafer 10B, the 1st and 4th rows of B subpixel arrays of the B wafer 10B of (A) are picked up and transferred to become empty, and (B)/( As shown in C), the B sub-pixel arrays 100B-SP1 and 100B-SP4 in three and six columns are transferred to the carrier substrate 200B.

The carrier substrate 200B may have the same material and properties as the carrier substrates 200R and 200G.

18 shows a process of secondary transfer of a B subpixel CSP array from a carrier substrate to a display panel.

Referring to FIG. 18, (A) shows the pads 31-SP1… 31-SP6 of the display panel 300, and through the processes of FIGS. 11 to 13 and the processes of FIGS. The R sub-pixel array is transferred to the 4th row and the G subpixel array is transferred to the 2nd and 5th columns. It shows a state in which the B sub-pixel array is secondarily transferred onto the display panel 300.

Pads 31-SP1… 31-SP6 are formed in rows 1 to 6 of the display panel 300, and solder pastes 33-SP3 and 33-SP6 are formed in rows 3 and 6, and the corresponding row positions B sub-pixels CSPs 100B-SP1 and 100B-SP4 are transferred to each other.

FIG. 19 is a cross-sectional view illustrating a process of transferring from a carrier substrate to a display panel in FIG. 18 in more detail.

Referring to FIG. 19, a solder paste 33 is applied on a plurality of pads 31 of the display panel 300, and R sub-pixels CSP are already in the first row and the fourth row, and the second and fifth rows. The arrays 100R-SP1 and 100R-SP4 and the G sub-pixel CSP arrays 100G-SP1 and 100G-SP4 are located in a transferred state (FIG. 19A).

Next, referring to (B) of FIG. 19, the B subpixels CSPs 100B-SP1 and 100B-SP4 attached to the carrier substrate 200B of FIG. 17 by the carrier substrate 200B manufactured in FIG. Solder paste 33-SP3, which is disposed on the display panel 300 and applied with the pad 14 of the B sub-pixel CSP (100B-SP1, 100B-SP4) on the pad 31 of the display panel 300, 33-SP6).

After the pad 14 of the B sub-pixel CSP (100B-SP1, 100B-SP4) and the pad 31 of the display panel 300 are in contact with each other through the solder paste (33-SP3, 33-SP6), for example, , When a predetermined heat is applied using a self-aligning paste (SAP) soldering method, the solder particles contained in the solder pastes (33-SP3, 33-SP6) become B sub-pixel CSP (100B). -It may be self-assembled between the pads 14 of the SP1 and 100B-SP4 and the pads 31-SP3 and 31-SP6 of the display panel 300.

Next, referring to (C) of FIG. 19, the pads 14 of the B sub-pixels CSPs 100B-SP1 and 100B-SP4 and the pads 31-SP3 and 31-SP6 of the display panel 300 are soldered. Then, the carrier substrate 200B is separated.

If the processes of FIGS. 11 to 13, 14 to 16, and 17 to 19 are sequentially applied, a display panel in which one completed RGB pixel CSP array is arranged can be manufactured, and FIGS. 11 and 14 17, each of the RGB sub-pixel arrays formed in each of the R wafers 10R, G wafers 10G, and B wafers 10B can be sequentially and selectively used from the first row to the last row.

Meanwhile, when configuring a display or a device by moving the pad area of the display panel, it is possible to solve an electrical connection problem (opening, sorting failure) occurring in the conventional surface mounting process of a chip unit.

Specifically, by simultaneously introducing a pixel CSP having an extended pad and a region-shifted pad (target substrate), the electrical connection process of the micro LED in a tens µm area is scaled up to a pixel CSP electrical connection process in a hundreds µm area. )can do.

Through this scale-up, it is possible to quickly manufacture a large-area display device by preventing an open/short defect between electrodes in a transfer process constituting a display device and increasing alignment margin.

Hereinafter, a concept of moving a pad on a display panel corresponding to an extended subpixel CSP pad will be described in detail with reference to FIGS. 20 and 21.

20 is a view showing a comparison before and after movement of an electrode pad of a display panel.

FIG. 20 shows a pad array of a display panel, which may have an arrangement corresponding to a plurality of pads of one sub-pixel CSP 100R, 100G, and 100B shown in FIG. 4.

(A1), (B1), and (C1) of FIG. 20 are schematic diagrams of arrangement of pads on a conventional display panel, and (A2), (B2), and (C2) are arrangements of pads on a display panel according to an embodiment of the present invention. Yes.

In the case of the micro LED, since the size is very small, the spacing d1 between the pads of the display panel corresponding thereto is also very narrow. In the embodiment of the present invention, by increasing the spacing d2 between pads of the display panel, it is possible to prevent a short circuit due to solder paste between the pads in advance.

The relationship between the pads d1 <d2 is established, and d2 can be implemented by moving regions left and right from respective positions of the pads 140 and 140'.

Prerequisites for increasing the spacing of the pads 140 and 140' of the display panel are as follows.

The embodiment of the present invention proposes a first transfer and/or a second transfer as a method for simultaneously transferring a plurality of sub-pixels CSP 100 shown in FIG. 4 to the display panel 300 at a high speed.

Here, for the second transfer, a transfer method using a difference in adhesion between the carrier substrate 200 and the solder paste 170 is adopted.

Therefore, in order to implement the second transfer, the solder paste 170 must be applied on the pad 140 of the display panel 300, and in this case, before the solder paste 170 is applied, the white ink ( White ink) is applied first.

If the gap between the pads 14 and 14' of the display panel is very narrow (less than 100㎛) as in the prior art, white ink (15) cannot be filled between the pads 14 and 14', and white ink A step is formed between the pads 14 and 14' that are not filled with (15), and the solder paste 17 is trapped, and a short circuit may occur due to the remaining solder paste.

Accordingly, the embodiment of the present invention increases the distance d2 between the pads 140 and 140 ′ by moving the pads 140 and 140 ′ of the display panel 300 left and right to solve the above problem. The white ink 150 makes it possible to form a white ink dam.

That is, the gap between the pads 140 and 140 ′ is widened, so that white ink may be filled between the pads.

The formation of the white ink dam may eliminate a step difference between the pads 140 and 140 ′, and a cause of a short circuit between electrodes may be eliminated because residual solder paste is not generated.

Next, as described above, if the electrode spacing is widened according to the precondition for increasing the spacing of the pads 140 and 140' of the display panel, the possible conditions for increasing the electrode spacing are as follows.

The possible condition for increasing the spacing of the pads 140 and 140 ′ of the display panel 300 is that the pads 14R, 14R', 14G, and 14B of the sub-pixel CSP 100 are extended as in FIG. 5 described above. Is possible by

21 is a view for explaining in detail a step of transferring a pixel CSP array having an extended pad transferred to a carrier substrate to a display panel.

Referring to FIG. 21A, a solder paste 170 is applied on a plurality of pads 140 of the display panel 300.

The solder paste 170 may be applied on the plurality of pads 140 of the display panel 300 through various methods such as screen printing, dispensing, and jetting.

Next, referring to FIG. 21B, the carrier substrate 200 and the wafer layer 10 attached to the carrier substrate 200 are transferred onto the display panel 300, and the pads 14R of each subpixel CSP , 14R') are brought into contact with the solder pastes 170 and 170' applied on the pads 140 and 140' of the display panel 300.

After the pads 14R and 14R' of each pixel CSP and the pads 140 and 140' of the display panel 300 are in contact with each other through the solder pastes 170 and 170', for example, self-alignment paste Paste, SAP) When a predetermined heat is applied using a soldering method, solder particles contained in the solder pastes 170 and 170 ′ are removed from the pads 14R and 14R ′ of the pixel CSP and the display panel 300. It may be self-assembled between the pads 140 and 140 ′.

Meanwhile, the thermosetting resin included in the solder pastes 170 and 170 ′ may be cured by heat.

Next, referring to FIG. 21C, when the pads 14R and 14R' of the sub-pixel CSP and the pads 140 and 140' of the display panel 300 are soldered, the carrier substrate 200 is transferred to the wafer ( 10).

Here, since the soldering adhesive force between the pads 14R and 14R' of the sub-pixel CSP and the pads 140 and 140' of the display panel 300 is much greater than the adhesive force between the carrier substrate 200 and the wafer 10, Only the carrier substrate 200 can be easily separated.

Referring to FIG. 21, it is possible to widely adjust the spacing between the pads 140 and 140 ′ of the display panel 300 by the first and second pads 14R and 14R ′ of the sub-pixel CSP, that is, the pad ( 140, 140') can be moved.

In other words, it is possible to improve the contact margin between the electrodes between the pixel CSP and the display panel 300 during the transfer process by the pads 14R and 14R' that are expanded than the conventional pads, and the pad 140 of the display panel 300, 140'), it is possible to move the same area as the spread of both sides, and thus it is possible to block the occurrence rate of a short between electrodes.

In particular, such contact margin and short-circuit prevention can improve the speed and accuracy of the transfer process when applied to a display device to which a micro-unit LED is applied.

Again, referring to FIG. 1, although not shown in FIG. 1, a rework step may be further included. In the rework step, a pixel CSP determined to be malfunctioning or defective among the pixel CSP array formed on the display panel is removed, and a new pixel CSP is placed in the position of the removed pixel CSP.

A new pixel CSP that is normally operating may be located using a pick and place device (not shown).

By further proceeding with the rework step, since the malfunction or defective pixel CSP is removed, and a new pixel CSP is filled in the position where the defective pixel CSP was to be located in the display panel, the display panel is compared with the manufacturing method of the display device shown in FIG. 1. There is an advantage that can significantly reduce the defect of the.

22 and 23 are exemplary diagrams of a process of selectively transferring each RGB subpixel formed on each wafer to a display panel in column units according to an embodiment of the present invention.

22 and 23 are explanatory diagrams for explaining in what order the transfer is performed for each RGB sub-pixel array on the wafer and the display panel corresponding to 1:1, and the order in FIGS. 13, 16 and 19 in parallel with this order A description of how to transfer each sub-pixel array according to the method is shown.

Figure 22 shows the RGB sub-pixel CSP array formed on each wafer (preferably includes a process of transferring to the carrier substrate (200R, 200G, 200B) through the primary transfer process), Figure 23 is a display It shows the panel 300.

For convenience of explanation, FIGS. 22 and 23 illustrate three display panels (Panel-1, Panel-2, Panel-3) and three wafers (R-Sub Pixel, G-Sub Pixel, and B-Sub Pixel). It is described as

22 and 23 show examples of selectively transferring an RGB subpixel CSP array in a column (vertical) arrangement, and the same applies to a row (horizontal) arrangement.

(A) of FIG. 22 is a state in which all subpixel CSPs before transfer are arrayed, (B) is a state in which one row of RGB subpixel CSP arrays is transferred, and (C) is a state in which two rows of RGB subpixel CSP arrays are transferred. It shows the status.

(A) of FIG. 23 shows a state in which a single row of RGB subpixel CSP arrays has been transferred to the display panel, (B) shows a state in which two rows of RGB subpixel CSP arrays are transferred to the display panel, and (C) is a third row of RGB. This shows the state in which the sub-pixel CSP array is transferred to the display panel.

First, the R sub-pixel CSP array (row 1, column 4, column 7 ...) formed on the wafer of FIG. 22 is transferred onto the first display panel (Panel-1) (row 1, column 4, column 7 ...). , G sub-pixel CSP array (row 1, column 4, column 7 …) formed on the wafer is transferred onto the second display panel (Panel-2) (row 2, column 5, column 8 …), on the wafer The formed B sub-pixel CSP array (row 1, column 4, column 7 …) is transferred onto the third display panel (Panel-3) (row 3, column 6, column 9 …), and the transfer state up to this point is displayed on the display panel. 23(A) on the top and FIG. 22(B) on the wafer correspond to this.

Next, the G sub-pixel CSP array (2 columns, 5 columns, 8 columns...) formed on the wafer of Fig. 22 is transferred onto the first display panel (Panel-1) (2 columns, 5 columns, 8 columns...). ), the B sub-pixel CSP array (2 columns, 5 columns, 8 columns …) formed on the wafer is transferred onto the second display panel (Panel-2) (2 columns, 5 columns, 8 columns …), and The R sub-pixel CSP array (3 columns, 6 columns, 9 columns …) formed in is transferred onto the third display panel (Panel-3) (1 column, 4 columns, 7 columns …), and the transfer status is displayed so far. Figure 23 (B) on the panel, and Figure 22 (C) on the wafer corresponds to this.

Finally, the B sub-pixel CSP array (3 columns, 6 columns, 9 columns...) formed on the wafer of FIG. 22 is transferred onto the first display panel (Panel-1) (3 columns, 6 columns, 9 columns...). ), the R subpixel CSP array (3 columns, 6 columns, 9 columns …) formed on the wafer is transferred onto the second display panel (Panel-2) (1 column, 4 columns, 7 columns …), and The G sub-pixel CSP array (3 columns, 6 columns, 9 columns …) formed in is transferred onto the third display panel (Panel-3) (2 columns, 5 columns, 8 columns …), and the transfer status is displayed so far. 23C is shown on the panel, and all subpixels are transferred on the wafer.

In this way, the RGB sub-pixel CSP array can be selectively transferred in units of columns or rows, and when the RGB sub-pixel CSP array is selectively and sequentially transferred in RGB order, RGB pixels on the display panel as shown in Fig. 23C All LED chips can be transferred as a unit.

Features, structures, effects, and the like described in the embodiments above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in each embodiment can be implemented by combining or modifying other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Accordingly, contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the embodiments have been described above, these are only examples and do not limit the present invention, and those of ordinary skill in the field to which the present invention pertains will not depart from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications not illustrated are possible. For example, each constituent element specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

10R, 10G, 10B: wafer
100R, 100G, 100B: Sub-pixel CSP
200R, 200G, 200B: carrier substrate
300: display panel
400: TFT array substrate

Claims (19)

Forming a sub-pixel CSP (Chip Scale Package) for each R sub-pixel CSP, G sub-pixel CSP, and B sub-pixel CSP on each wafer, forming an RGB sub-pixel CSP;
Dicing each wafer on which the RGB sub-pixel CSP is formed for each sub-pixel CSP to form a sub-pixel CSP array arranged in row and column directions;
A carrier substrate having an opening hole in a predetermined row or column direction and coated with an adhesive material on one surface of which the opening hole is not formed is brought into contact with the sub-pixel CSP array, and the adhesive material of the sub-pixel CSP array A first transfer step of selectively transferring some sub-pixel CSP arrays in contact with the carrier substrate; And
A solder paste is applied on a selected pad among a plurality of pads of a display panel, and the partial sub-pixel CSP array transferred to the carrier substrate is contacted with the solder paste and soldered to the RGB sub-pixel CSP from the carrier substrate to the display panel. A method of manufacturing a display device using a method of selectively transferring a carrier substrate, including; a secondary transfer step of selectively transferring each array. The method of claim 1,
The carrier substrate includes an R carrier substrate for R sub-pixel CSP array transfer, a G carrier substrate for G sub-pixel CSP array transfer, and a B carrier substrate for B sub-pixel CSP array transfer, using a selective transfer method of a carrier substrate Manufacturing method. The method of claim 2,
The opening holes of the R carrier substrate are 2 rows or columns, 3 rows or columns, 5 rows or columns, 6 rows or columns of the R sub-pixel CSP formed on the wafer, ... , 3n+2 (n is 0, 1, 2, …) formed in a row or column, 3n+3 row or column,
The opening hole of the G carrier substrate is 1 row or column, 3 row or column, 4 row or column, 6 row or column of the G sub-pixel CSP formed on the wafer, ... , Formed in 3n+1 rows or columns, 3n+3 rows or columns,
The opening holes of the B carrier substrate are 1 row or column, 2 rows or columns, 4 rows or columns, 5 rows or columns of the B sub-pixel CSP formed on the wafer, ... , A method of manufacturing a display device using a selective transfer method of a carrier substrate, which is formed in 3n+1 rows or columns, 3n+2 rows or columns. The method of claim 1,
The opening hole of the carrier substrate is formed to have the same pitch as each of the R sub-pixels CSP, G sub-pixels CSP, and B sub-pixels CSP of the wafer, a method of manufacturing a display device using a selective transfer method of the carrier substrate. delete delete delete The method of claim 1,
The secondary transfer step,
Applying a solder paste to a plurality of pads of the display panel;
A soldering step of contacting and soldering the pad of the sub-pixel CSP selectively transferred to the carrier substrate to the applied solder paste; And
Separating the carrier substrate from the display panel, separating step; including, a method of manufacturing a display device using a selective transfer method of the carrier substrate. The method of claim 1,
The secondary transfer step,
Any one of the arrays of each of the R sub-pixel CSP, G sub-pixel CSP, and B sub-pixel CSP is selectively transferred to corresponding positions of the three display panels, respectively,
An R sub-pixel CSP array, a G sub-pixel CSP array, and a B sub-pixel CSP array are sequentially transferred to each of the three display panels to be adjacent to each other. delete delete The method of claim 1,
In the sub-pixel CSP, the R sub-pixel CSP, G sub-pixel CSP, and B sub-pixel CSP are transferred to the display panel to form one pixel CSP. A method of manufacturing a display device using a selective transfer method of a carrier substrate. The method of claim 1,
The sub-pixel CSP forms a sub-pixel CSP array in which the R sub-pixel CSP, G sub-pixel CSP, and B sub-pixel CSP are arranged in row and column directions,
The sub-pixel CSP array is simultaneously or sequentially transferred to the display panel to form one pixel CSP array. A method of manufacturing a display device using a selective transfer method of a carrier substrate. delete delete delete delete Forming a sub-pixel CSP (Chip Scale Package) for each R sub-pixel CSP, G sub-pixel CSP, and B sub-pixel CSP on each wafer, forming an RGB sub-pixel CSP;
Dicing each wafer on which the RGB sub-pixel CSP is formed for each sub-pixel CSP to form an RGB sub-pixel CSP array arranged in row and column directions;
A first carrier substrate having a first opening hole in a predetermined row or column direction and coated with an adhesive material on one side of the first opening hole is not formed on the R sub-pixel CSP array, and the R sub A first carrier substrate transfer step of selectively transferring some R sub-pixel CSP arrays in contact with the adhesive material among the pixel CSP arrays to the first carrier substrate;
On the G sub-pixel CSP array, a second carrier substrate having a second opening hole in a predetermined row or column direction different from the first opening hole and on which the second opening hole is not formed is coated with an adhesive material. A second carrier substrate transfer step of selectively transferring some of the G sub-pixel CSP arrays in contact with the adhesive material from the G sub-pixel CSP array to the second carrier substrate;
A third carrier substrate having a third opening hole in a predetermined row or column direction different from the first and second opening holes, and on which the third opening hole is not formed, is coated with an adhesive material. A third carrier substrate transfer step of contacting a CSP array to selectively transfer some of the B sub-pixel CSP arrays in contact with the adhesive material to the third carrier substrate; And
The R sub-pixel CSP array, G sub-pixel CSP array, and B sub-pixel CSP array, respectively, transferred to the first to third carrier substrates are sequentially transferred to a display panel, on a selected pad among a plurality of pads of the display panel. A solder paste is applied to the first to third carrier substrates, and the partial RGB subpixel CSP arrays transferred to the first to third carrier substrates are contacted with the solder paste and soldered to the RGB subpixels from the first to third carrier substrates to the display panel. A display panel transfer step of selectively transferring each CSP array;
Containing, a method of manufacturing a display device using a selective transfer method of a carrier substrate. delete

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