KR102323586B1 - Led sub-pixel csp with extended electrode pad and manufactured method thereof - Google Patents

Abstract

The present invention relates to an LED sub-pixel CSP, and more particularly, to a red, green, and blue LED sub-pixel CSP (Sub-Chip Scale Package) including an extended electrode pad, and a method of manufacturing the same.
An LED sub-pixel CSP having an expansion pad according to the present invention comprises: a base substrate; a plurality of red LEDs, a plurality of green LEDs, or a plurality of blue LEDs formed on the base substrate; and a pair of expansion pads each having an area extended to each of the plurality of Red LEDs, the plurality of Green LEDs, or the plurality of Blue LEDs, wherein each of the plurality of Red LEDs, the plurality of Green LEDs or the plurality of Blue LEDs is one It has a CSP (Chip Scale Package) form of LED sub-pixel CSP.

Description

LED SUB-PIXEL CSP WITH EXTENDED ELECTRODE PAD AND MANUFACTURED METHOD THEREOF

The present invention relates to an LED sub-pixel CSP, and more particularly, to a red, green, and blue LED sub-pixel CSP (Sub-Chip Scale Package) including an extended electrode pad, and a method of manufacturing the same.

A light emitting diode (LED) is one of light emitting devices that emits light when an electric current is applied thereto. Light-emitting diodes can emit high-efficiency light with a low voltage, and thus have an excellent energy-saving effect.

Recently, the luminance problem of light emitting diodes has been greatly improved, and it has been applied to various devices such as a backlight unit of a liquid crystal display device, an electric sign board, a display device, and a home appliance.

The size of a micro light emitting diode (μ-LED) is very small, ranging from 1 to 100 μm, and approximately 25 million or more pixels are required to implement a 40-inch display device.

Therefore, there is a problem that it takes at least a month in terms of time by a simple pick and place method to make one 40-inch display device.

Existing micro light emitting diodes (μ-LED) are manufactured in plurality on a sapphire substrate, and then, by a mechanical transfer method, pick & place, micro light emitting diodes are placed on glass or flexible substrate one by one. are transcribed

Since the micro light emitting diodes are picked up one by one and transferred, it is referred to as a 1:1 pick-and-place transfer method.

However, since the size of the micro light emitting diode chip manufactured on the sapphire substrate is small and the thickness is thin, the chip is damaged or the transfer fails, or the chip alignment ( Alignment) fails, or a problem such as a tilt of the chip is generated.

In addition, there is a problem that the time required for the transcription process is too long.

Republic of Korea Patent Publication 10-2019-0096256

An object of the present invention is to provide an LED sub-pixel CSP capable of selectively transferring a plurality of RGB sub-pixels to a display panel quickly.

Another object of the present invention is to provide a method of manufacturing a display device capable of rapidly manufacturing a micro LED-based display device and minimizing a transfer error.

Another object of the present invention is to provide an LED sub-pixel CSP having an extended electrode pad so that micro-scale LEDs can be quickly transferred to a display device without errors, and a method for manufacturing the same.

In addition, it is intended to use a wafer having as many RGB sub-pixels as possible on a limited area irrespective of the resolution of the display device.

The problem to be solved of the present invention is not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. will be.

LED sub-pixel CSP having an expansion pad according to the present invention for solving the above problems, a base substrate; a plurality of red LEDs, a plurality of green LEDs, or a plurality of blue LEDs formed on the base substrate; and a pair of expansion pads each having an area extended to each of the plurality of Red LEDs, the plurality of Green LEDs, or the plurality of Blue LEDs, wherein each of the plurality of Red LEDs, the plurality of Green LEDs, or the plurality of Blue LEDs is one It has a CSP (Chip Scale Package) form of LED sub-pixel CSP.

Here, the base substrate may be a wafer or a carrier substrate on which each of the plurality of Red LEDs, the plurality of Green LEDs, or the plurality of Blue LEDs formed on the wafer is transferred.

Here, when the base substrate is a wafer, the expansion pad may be formed on the wafer, and when the base substrate is a carrier substrate, the expansion pad may be formed on the carrier substrate.

Here, it is preferable that the expansion pad extends from the pad of each light emitting device in one LED sub-pixel CSP and does not intersect the pad extended from the adjacent LED sub-pixel CSP.

Here, the pitch between the plurality of red LEDs, the plurality of green LEDs, or the plurality of blue LEDs formed on the base substrate may be formed based on an area expansion for forming the expansion pad.

Here, the base substrate is a carrier substrate to which each of the plurality of Red LEDs, the plurality of Green LEDs, or the plurality of Blue LEDs formed on the wafer is transferred, and the expansion pad includes the plurality of Red LEDs, the plurality of LEDs on the carrier substrate. It can be formed by a lift-off process after forming a photoresist layer covering each of the green LEDs or a plurality of blue LEDs, placing a photomask on the photoresist layer, depositing a metal on the portion exposed through UV exposure, and then performing a lift-off process. have.

Here, the pair of expansion pads may be formed to extend out of an area in which each of the plurality of red LEDs, the plurality of green LEDs, or the plurality of blue LEDs is formed.

Here, the pair of expansion pads may have a shape extending left and right through metal deposition on the respective pads of the plurality of Red LEDs, the plurality of Green LEDs, or the plurality of Blue LEDs.

Here, one Red LED sub-pixel CSP, a Green LED sub-pixel CSP, and a Blue LED sub-pixel CSP among the LED sub-pixel CSPs may constitute one LED pixel CSP.

When the method of manufacturing the display device according to the embodiment is used, there is an advantage in that RGB sub-pixels are manufactured on each wafer in the form of CSP, and a plurality of RGB sub-pixels can be selectively transferred to a display panel quickly and efficiently.

In addition, when the size of the light emitting region of the light emitting device is less than 100 μm, the light efficiency is sharply decreased due to epi damage caused by dicing or the like. On the other hand, the present invention has the advantage that light efficiency is not lowered because it is manufactured and transferred in units of LED sub-pixels CSP rather than in units of light emitting diode chips.

In addition, it is applicable to display devices having various sizes and various pitches between sub-pixels.

In addition, since each wafer having as many RGB sub-pixels as possible on a limited area is used regardless of the resolution of the display device, wafer manufacturing cost can be reduced and a process for forming a color conversion layer is not required.

In addition, each RGB sub-pixel CSP unit is manufactured, and it is possible to provide an LED sub-pixel CSP with an electrode directly extended on the wafer. It is possible to provide a sub-pixel CSP.

In addition, since the RGB sub-pixel CSP is manufactured on the wafer, the yield can be sharply increased by reducing the net die or gross die to increase the number of chips that can be produced per wafer.

1 is a diagram in which RGB sub-pixels are formed on each wafer according to a first embodiment of the present invention.
2 is a structural diagram in which each RGB Epi is grown on each wafer according to the first embodiment of the present invention.
3 is a process diagram of dicing each of the RGB sub-pixels formed on each wafer into one sub-pixel CSP unit according to the first embodiment of the present invention.
4 is a side cross-sectional view for comparing a sub-pixel CSP having a conventional conventional pad in which the pad is not expanded and a sub-pixel CSP having an expanded pad.
5 is a diagram in which RGB chips are formed on each wafer according to the second embodiment of the present invention.
6 is a process diagram of growing each RGB Epi on each wafer according to the second embodiment of the present invention.
7 is a process diagram of dicing each RGB chip formed on each wafer in a single chip unit according to the second embodiment of the present invention.
8 to 10 are views showing the structure of a carrier substrate for selectively transferring the chip array shown in FIG. 5 by the carrier substrate.
11 is a diagram for selectively transferring an R(Red) chip array to a carrier substrate.
12 and 13 are diagrams for explaining in detail a process of expanding an area of an R chip array transferred to a carrier substrate and expanding a pad.
FIG. 14 is a view for explaining in detail a step of transferring the sub-pixel CSP array shown in FIG. 1 to a carrier substrate.
15 to 18 are diagrams for explaining in detail the step of transferring the sub-pixel CSP array transferred to the carrier substrate to the display panel.
19 is a view showing a comparison before and after region movement of an electrode pad of a display panel.
20 is a view for explaining in detail the step of transferring the pixel CSP array having the extended pad transferred to the carrier substrate to the display panel.
21 illustrates a process in which the pad-extended R sub-pixel CSP array is secondary transferred from the carrier substrate to the display panel.
22 is a cross-sectional view illustrating in more detail a process of transferring from another carrier substrate to a display panel in FIG. 21 .
23 shows a process of primary transfer of a G chip array from a G wafer to a carrier substrate.
24 shows a process of secondary transfer of the pad-extended G sub-pixel CSP array from the carrier substrate to the display panel.
25 is a cross-sectional view illustrating in more detail a process of transferring from another carrier substrate to a display panel in FIG. 24 .
26 shows a process in which the B chip array is first transferred from the B wafer to the carrier substrate.
27 illustrates a process in which the pad-extended B sub-pixel CSP array is transferred from the carrier substrate to the display panel.
28 is a cross-sectional view illustrating in more detail a process of transferring from another carrier substrate to a display panel in FIG. 27 .

In the description of the embodiment, in the case where it is described as being formed on "above (above) or under (below)" of each component, the upper (above) or lower (below) two components are in direct contact with each other or one or more other components disposed between two components.

In addition, when expressed as "upper (upper) or lower (lower)", a meaning of not only an upper direction but also a lower direction based on one component may be included.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not fully reflect the actual size.

CSP, LED pixel CSP, and LED sub-pixel CSP used in the present invention may be defined as follows.

A chip scale package (CSP) is a package that has recently received a lot of attention in the development of a single chip package, and refers to a single chip package having a semiconductor/package area ratio of 80% or more.

LED pixel CSP refers to a single package in which one LED pixel is CSP packaged by using Red LED, Green LED, and Blue LED as one pixel unit.

The LED sub-pixel CSP refers to a single package in which each of Red LED, Green LED, and Blue LED is used as one sub-pixel unit and CSP is packaged in one LED sub-pixel unit.

[LED sub-pixel CSP with expansion pad according to the first embodiment of the present invention]

1 is a diagram in which RGB sub-pixels are formed on each wafer according to a first embodiment of the present invention.

In the embodiment of the present invention, three wafers each having RGB sub-pixels are described as an example, but the present invention is not limited thereto.

Referring to FIG. 1 , a plurality of light emitting devices 11R, 11G, and 11B emitting light of the same wavelength band are formed on each one wafer 10R, 10G, and 10B.

Here, the light emitting devices 11R, 11G, and 11B may be light emitting chips emitting red, green, and blue light.

The plurality of light emitting devices 11R, 11G, and 11B may be arranged at equal intervals along a plurality of rows and columns on each wafer 10R, 10G, and 10B.

Since the light emitting devices 11R, 11G, and 11B arranged at equal intervals are transferred to the display panel thereafter in the row or column direction, the manufacturing cost of the light emitting device can be reduced by efficiently utilizing the entire area of a relatively expensive wafer.

Here, each of the light emitting devices 11R, 11G, and 11B may correspond to a sub-pixel chip scale package (CSP) packaged in units of one sub-pixel.

Meanwhile, after forming a plurality of RGB sub-pixels on each of the wafers 10R, 10G, and 10B, the wafer may be diced for each RGB sub-pixel to separate each RGB sub-pixel CSP.

The pitch W1 between the RGB sub-pixels formed on each of the wafers 10R, 10G, and 10B is preferably the same as the pitch between the sub-pixels of the display panel or is set as a multiple of a proportional constant of a predetermined value.

2 is a structural diagram in which each RGB Epi is grown on each wafer according to the first embodiment of the present invention.

Referring to FIG. 2 , epis 11R, 11G, and 11B emitting a predetermined light are grown on one surface of each of the three wafers 10R, 10G, and 10B.

Here, the wafers 10R, 10G, and 10B may be a sapphire (Al2O3) substrate.

Forming pads 14R, 14G, and 14B on the grown epi (11R, 11G, 11B), respectively, and protecting the epi (11R, 11G, 11B) and the pad (14R, 14G, 14B) passivation (Passivation) A layer 13 is formed.

When the protective layer 13 is formed, it is preferable to form the pads 14R, 14G, and 14B to be exposed to the outside of the protective layer 13 in order to expand the area of the pad thereafter.

The pads 14R, 14G, and 14B are electrodes made of a + and - conductive material for applying power, and may be manufactured in an expanded form unlike a conventional pad.

In other words, in the process of forming the pad PAD on the epitaxial layers 11R, 11G, and 11B formed on each of the wafers 10R, 10G, and 10B, an expanded form having a size larger than that of a conventional pad. of pad can be formed.

The expanded pad may be manufactured by, for example, depositing a metal from the pad to an area extended from the pad by attaching a shadow mask, or by performing metal deposition after etching using a photomask and performing a lift-off method.

In the following drawings including FIG. 2 , the pads 14R, 14G, and 14B of the expanded size are shown, but the present invention is not limited thereto. Instead of the pads 14R, 14G, and 14B of the expanded size, a conventional general pad is used. may be replaced.

When the pads 14R, 14G, and 14B of the expanded size are used, the corresponding area is expanded when transferring to the electrode on the display panel, so it has the advantage of preventing transfer errors and further improving the transfer speed and accuracy. Since it is possible to form each RGB sub-pixel CSP for each wafer, a surplus space for extending the pad can be formed on the surplus area within the CSP, thereby improving the formation of the extended pad and the accuracy of transfer. has the advantage of being able to

2 shows the sectional views of the AA Section and the BB Section in FIG. 1, respectively, and preferably, a pair of (+), (-) electrodes per sub-pixel may be formed above and below Epi, and if necessary, Of course, it is also possible to form so as to be located on the left and right of the Epi.

3 is a process diagram of dicing each RGB sub-pixel formed on each wafer into one sub-pixel CSP unit according to the first embodiment of the present invention.

Referring to FIG. 3 , as shown in FIG. 2 , epi and pads are formed on the wafer and diced for each RGB sub-pixel CSP on which the protective layer 13 is formed to form a plurality of RGB sub-pixel CSPs 100R, 100G, and 100B. do.

Here, there may be various methods of dicing for each RGB sub-pixel CSP (100R, 100G, 100B), but dicing may be performed using a laser as an example.

In the drawings below, one RGB sub-pixel CSP (100R, 100G, 100B) is illustrated as the RGB sub-pixel CSP ( 100R, 100G, 100B) formed in FIG. 3 , but is not limited thereto. It may be an array of columnwise diced RGB sub-pixel CSPs (100R, 100G, 100B).

Each of the RGB sub-pixel CSPs 100R, 100G, and 100B may have a flip-chip structure that does not require wires.

An electrical connection is possible through the pad 14 instead of a wire, and each of the RGB sub-pixel CSPs 100R, 100G, and 100B may emit light of various colors according to an external control signal through the pad 14 .

The CSP (Chip Scale Package) of one RGB sub-pixel CSP (100R, 100G, 100B) is a generic term for a small package close to the size of a chip. It is a package with a size close to that of a chip.

In particular, in the present invention, each of the RGB sub-pixel CSPs 100R, 100G, and 100B may be a small package of a new concept manufactured in the form of a CSP by configuring each sub-pixel for each R, G, and B.

Each of the R sub-pixel 100R, the G sub-pixel 100G, and the B sub-pixel 100B may constitute one independent sub-pixel CSP.

One sub-pixel CSP can function as one pixel emitting various colors in a display panel to be described later, and each of the RGB sub-pixel CSPs (100R, 100G, 100B) is arranged in a plurality of rows and columns on a carrier substrate As a result, a sub-pixel CSP array can be formed, and the sub-pixel CSP array arranged on a carrier substrate can be selectively transferred to a display panel to be described later, and the R sub-pixel 100R, G sub-pixel 100G, and B sub-pixel 100B may be grouped to form one LED pixel.

4 is a cross-sectional side view for comparing a pixel CSP (A) having a conventional conventional pad in which the pad is not expanded and a pixel CSP (B) having an expanded pad, and shows a section B-B of FIG. 1 .

Comparing (A) and (B) of FIG. 4 , the pads 14R and 14R' expanded in the wafer manufacturing process are RGB using an existing surplus area that is not used within the area of one pixel CSP 100'. It is designed in an expanded form with the pixel in mind, and is enlarged compared to the pads 14r and 14r' of the existing chip so that the cross-sectional area thereof is widened.

In order to form the extended pads 14R and 14R' on the wafers 10R, 10G, and 10B of FIG. 1 , the sub-pixel pitch W1 may be determined according to the extended pitch interval between the pads.

In particular, in the case of a micro-unit LED chip, since the pixel unit is 30㎛ * 30㎛ to 100㎛ * 100㎛, the width or length of the pad is also very fine, and electrical open occurs during the surface mounting process of these as a substrate of a display panel. As a result, the defect rate can be very high.

On the other hand, by performing the surface mounting process in units of pixel CSP that can expand the pad on the display panel, the micro LED electrical connection process in the tens of um area is scaled up to the pixel CSP electrical connection process in the hundreds of um area. defects can be minimized.

In addition, it is possible to minimize electrical defects by increasing the alignment margin between the pixel CSP pad and the pad of the display panel during the surface mounting process on the display device, and to rapidly manufacture a large-area display device.

[LED sub-pixel CSP with expansion pad according to the second embodiment of the present invention]

5 is a diagram in which RGB chips are formed on each wafer according to the second embodiment of the present invention.

As shown in FIG. 5 , in the second embodiment of the present invention, three wafers each on which RGB chips are formed are described as an example, but the present invention is not limited thereto.

Referring to FIG. 5 , a plurality of light emitting devices 11R, 11G, and 11B emitting light of the same wavelength band are formed on each one wafer 10R, 10G, and 10B.

Here, the light emitting devices 11R, 11G, and 11B may be light emitting chips emitting red, green, and blue light.

The plurality of light emitting devices 11R, 11G, and 11B may be arranged at equal intervals along a plurality of rows and columns on each wafer 10R, 10G, and 10B.

Since the light emitting devices 11R, 11G, and 11B arranged at equal intervals are transferred to the display panel thereafter in the row or column direction, the manufacturing cost of the light emitting device can be reduced by efficiently utilizing the entire area of a relatively expensive wafer.

Meanwhile, after forming a plurality of RGB chips on each of the wafers 10R, 10G, and 10B, the wafers may be diced for each RGB chip to be separated for each RGB chip.

It is preferable that the pitch W2 between the RGB chips formed on each of the wafers 10R, 10G, and 10B is the same as the pitch between the sub-pixel CSPs formed on the display panel or is set as a multiple of a proportional constant of a predetermined value.

The pitch W2 between the RGB sub-pixel CSPs formed on each of the wafers 10R, 10G, and 10B may be narrower than the pitch W1 between the RGB sub-pixel CSPs of FIGS. 1 to 4, which is a Net Die Alternatively, the yield can be increased by reducing the Gross Die to increase the number of chips that can be produced per wafer.

The reason is that, since the first embodiment has a structure in which an extended electrode is formed directly on a wafer, a corresponding chip formation area is required depending on the extended electrode, but in the second embodiment, on a separate carrier substrate instead of on a wafer (This is transferred from the wafer to the carrier substrate) Since the expanded electrode is formed, it is not necessary to widen the chip formation area as much as the electrode pad has an unexpanded normal size on the wafer.

6 is a process diagram of growing each RGB Epi on each wafer according to the second embodiment of the present invention.

Referring to FIG. 6 , epis 11R, 11G, and 11B emitting a predetermined light are grown on one surface of each of the three wafers 10R, 10G, and 10B.

Here, the wafers 10R, 10G, and 10B may be a sapphire (Al2O3) substrate.

Forming a pad 14r, 14g, 14b on each of the grown epi (11R, 11G, 11B), and protecting the epi (11R, 11G, 11B) and the pad (14r, 14g, 14b) passivation (Passivation) A layer 13 is formed. Here, the pads 14r, 14g, and 14b are not expanded and may have the size and shape of a general pad.

When the protective layer 13 is formed, it is preferable to form the pads 14r, 14g, and 14b to be exposed to the outside of the protective layer 13 in order to expand the area of the pad thereafter.

6 shows the cross-sectional views of the AA Section and the BB Section in FIG. 5, respectively. Preferably, a pair of (+), (-) electrodes per chip are formed under the Epi layer, and the electrodes are based on the AA section. Of course, it can be formed up and down, and it is also possible to form left and right if necessary.

Comparing the B-B section of FIG. 6 and FIG. 2 , it can be seen that in FIG. 2 the pad has an expanded form, and in FIG. 6 , the pad has a form before the pad is expanded.

7 is a process diagram of dicing each RGB chip formed on each wafer in a single chip unit according to the second embodiment of the present invention.

Referring to FIG. 7 , as shown in FIG. 6 , epis 11R, 11G, 11B and pads 14r, 14g, and 14b are formed on the wafer and diced for each RGB chip on which the protective layer 13 is formed, so that a plurality of RGB The chips 100R, 100G, and 100B are formed.

Here, there are various methods of dicing for each RGB chip 100R, 100G, and 100B, but dicing may be performed using a laser as an example.

In the drawings below, one RGB chip 100R, 100G, 100B is illustrated as the RGB chip 100R, 100G, 100B formed in FIG. 7, but is not limited thereto, and the die in the row and column directions in FIG. It may be a single RGB chip (100R, 100G, 100B) array.

Each of the RGB chips 100R, 100G, and 100B may have a flip-chip structure that does not require wires.

Electrical connection is possible with pads 14r, 14g, and 14b instead of wires, and each of the RGB chips 100R, 100G, 100B emits light of various colors according to an external control signal through the pads 14r, 14g, 14b. can do.

In addition, in the present invention, each of the RGB chips 100R, 100G, and 100B may be a small package of a new concept manufactured in the form of a CSP by configuring sub-pixels for each R, G, and B, respectively.

The R chip 100R, the G chip 100G, and the B chip 100B may constitute one light emitting device.

A chip array can be formed by selectively transferring and arranging a plurality of RGB chips 100R, 100G, and 100B on a carrier substrate in row and column directions, and by expanding the region of the chip array selectively transferred to the carrier substrate The pixel CSP may be formed, and the sub-pixel CSP array arranged on the carrier substrate may be selectively transferred to a display panel to be described later by extending the pad of the sub-pixel CSP.

8 to 10 are views showing the structure of a carrier substrate for selectively transferring the chip array shown in FIG. 5 by the carrier substrate.

8 is a structure of a carrier substrate 200R for primary selective transfer from an R wafer on which an R chip array is formed, and FIG. 9 is a structure of a carrier substrate 200G for primary selective transfer from a G wafer on which a G chip array is formed. and FIG. 10 is a structure of a carrier substrate 200B for primary selective transfer from a B wafer on which a B chip array is formed.

8 to 10 show the structure of each of the carrier substrates 200R, 200G, and 200B for selective transfer in the order of columns in the R, G, and B chip arrays formed on the wafer.

For example, in the case of sequentially selectively transferring rows of the R wafer, the G wafer, and the B wafer, the carrier substrate 200R is formed in rows 1, 4, and 7 ?? Selective transfer is possible in that order, and the carrier substrate 200G has 2 rows, 5 rows, 8 rows ?? In order, the carrier substrate 200B has 3 rows, 6 rows, 9 rows ?? The chips formed on each wafer may be selectively transferred in this order.

Second, when the same rows of the R wafer, the G wafer, and the B wafer are selectively transferred, each of the carrier substrates 200R, 200G, and 200B is in the 1st row, the 4th row, and the 7th row ?? Select transcription is possible in that order, followed by columns 2, 5, and 8 ?? in that order, then column 3, column 6, column 9 ?? Sequentially, it can be selectively transferred without leaving any chips formed on the wafer until all transferred.

Assuming the first exemplary case, the transfer method will be described below (only columns 1 to 6 of the chip (first RGB chip array, second RGB chip array) are described as examples, and more (third, fourth, ? ?, nth RGB chip array) is omitted).

Referring to FIG. 8, (A) is a front view, (B) is a XX cross-sectional view of (A), (C) is a view in which an adhesive material is applied in (B), and is selectively transferred to the carrier substrate 200R. Opening holes 36 are formed in the remaining rows except for the parts (1st row, 4th row, ??) (35-SP1, 35-SP4, ??).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200R, and when the adhesive material 37 is applied to the surface of the carrier substrate 200R, the adhesive material is not applied to the opening hole 36 portion. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area where the opening hole 36 is not, so that only the corresponding column can be picked up. The material of the carrier substrate 200R may be metal, ceramic, glass, plastic, polymer, or the like.

9, (A) is a front view, (B) is a XX cross-sectional view of (A), (C) is a view in which the adhesive material is applied in (B), the carrier substrate 200G to be selectively transferred Opening holes 36 are formed in the remaining rows except for the parts (2nd row, 5th row, ??) (35-SP2, 35-SP5,??).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200G, and when the adhesive material 37 is applied to the surface of the carrier substrate 200G, the adhesive material is not applied to the opening hole 36 portion. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area where the opening hole 36 is not, so that only the corresponding column can be picked up. The material of the carrier substrate 200G may be metal, ceramic, glass, plastic, polymer, or the like.

Referring to FIG. 10, (A) is a front view, (B) is a XX cross-sectional view of (A), (C) is a view in which an adhesive material is applied in (B), and the carrier substrate 200B is to be selectively transferred. Opening holes 36 are formed in the remaining columns except for the portions (3rd row, 6th row, ??) (35-SP3, 35-SP6,??).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200B, and when the adhesive material 37 is applied to the surface of the carrier substrate 200B, the adhesive material is not applied to the opening hole 36 portion. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area where the opening hole 36 is not, so that only the corresponding column can be picked up. The material of the carrier substrate 200B may be metal, ceramic, glass, plastic, polymer, or the like.

Next, the primary transfer process of transferring the chip from the wafer to the carrier substrate 200R, 200G, and 200B using the prepared carrier substrates 200R, 200G, and 200B of FIGS. 8 to 10, and by expanding the area of the chip A process of forming a sub-pixel CSP, a pad extension process of the sub-pixel CSP array, and a secondary transfer process of transferring the sub-pixel CSP array to a display panel will be described.

11 to 13 show the formation of an R(Red) subpixel CSP array through selective transfer of an R(Red) chip array to a carrier substrate, an area expansion of the R(Red) chip array, and an R(Red) subpixel CSP array. The steps of pad-extended and pad-extended R (Red) sub-pixel CSP arrays to the display panel will be described sequentially.

11 shows a process of primary transfer of an R chip array from an R wafer to a carrier substrate, (A) is a front view of the R wafer (10R), (B) is an R wafer ( 10R) is a front view in which rows 1 and 4 are first transcribed, (C) is a XX cross-sectional view of (B).

Referring to FIG. 11 , the R wafer 10R of (A) is a state that has undergone the processes of FIGS. 3 and 4 , and the carrier substrate 200R of FIG. 8 is aligned with the R wafer 10R to contact the carrier substrate. When 200R is separated, the R chip arrays in rows 1 and 4 of the R wafer 10R in (A) are picked up and transferred to become empty, and as in (B)/(C), the R chip arrays 100R in rows 1 and 4 are empty. -SP1 and 100R-SP4 are transferred to the carrier substrate 200R.

The step of transferring the chip array to the carrier substrate may be referred to as 'primary transfer'.

Here, the carrier substrate 200R may also be referred to as a 'transfer adhesive member', and an adhesive or adhesive is applied to such materials as PET, PP, PE, PS resin board, or these materials are thin in the form of a tape. An adhesive or a pressure-sensitive adhesive may be applied to one side while having it.

The carrier substrate 200R may have a predetermined ductility, and the carrier substrate 200R having the predetermined ductility may be made of a material that can be easily bent by an external force.

When the carrier substrate 200R is a material that can be easily bent, transfer efficiency can be further improved compared to the case where the carrier substrate 200R is made of a material that is not easily bent.

When the carrier substrate 200R is made of a material that is not easily bent, it is difficult to lift the carrier substrate at once after attaching the respective chips 100R-SP1, 100R-SP2, and 100R-SP3 to the carrier substrate. The reason is that the adhesive force between the respective chips 100R-SP1, 100R-SP2, and 100R-SP3 and the carrier substrate 200R is significant.

However, if the carrier substrate 200R is a material that is easily bendable, after attaching each of the chips 100R-SP1 , 100R-SP2 , and 100R-SP3 to the carrier substrate 200R, one side portion of the carrier substrate 200R When the bay is raised upward, since the number of pixel CSPs attached only to that portion is relatively small, the entire carrier substrate 200R can be easily lifted with a small force.

Also, the carrier substrate 200R may be made of a transparent material. If the carrier substrate 200R is a transparent material, when transferring each of the chips 100R-SP1, 100R-SP2, 100R-SP3 to the carrier substrate 200R, position adjustment and misalignment are performed by an externally provided vision system ( It has the advantage of being able to adjust or control it through (not shown).

Meanwhile, the carrier substrate 200R may also be referred to as a first transfer medium in the method of manufacturing a display device according to an embodiment of the present invention. A first adhesive force is formed between the first transfer medium and the pixel CSP array. Specifically, the first adhesive force may be 2,000 gf/25mm to 4,000 gf/25mm. More preferably, the first adhesive force may be 3,000 gf/25mm.

Referring to FIG. 11C , when transferring the first and fourth rows of R chip arrays 100R-SP1 and 100R-SP4 to the carrier substrate 200R, the first and fourth rows of R chip arrays 100R-SP1 and 100R - The pad 14r side of SP4 is transferred to the carrier substrate 200R. This is for area expansion and pad expansion, which will be described later with reference to FIGS. 12 and 13 .

12 and 13 are diagrams for explaining in detail a process of expanding an area of an R chip array transferred to a carrier substrate and expanding a pad.

12(A) shows the formation (or coating) of the photoresist layer 18 so as to cover the R chip arrays 100R-SP1 and 100R-SP4 on the carrier substrate 200R after turning over FIG. 11(C). )do. Here, the photoresist layer 18 is an epoxy-based material, and may be SU-8.

Referring to FIG. 12B , the photoresist layer 18 is patterned through a photo process and a develop process. One R chip 100R-SP1 or 100R-SP4 is positioned inside the patterned photoresist layer 18R. A patterned photoresist layer 18R surrounds one R chip 100R-SP1 or 100R-SP4. As the patterned photoresist layer 18R is coupled to one R chip 100R-SP1 or 100R-SP4, one R sub-pixel CSP 100R-SP1 or 100R-SP4 may be formed. One R sub-pixel CSP has a larger volume than one R chip, and as a result, an area of one R sub-pixel CSP 100R-SP1 or 100R-SP4 is expanded. As such, in the R sub-pixel CSP, the patterned photoresist layer 18R is bonded to the R chip, and the surface area of the R sub-pixel CSP is increased to be greater than that of the R chip, thereby securing a pad expansion area. Since the size of the micro LED is a few micro units, the size of the pad is inevitably small as well. However, by making each chip into a sub-pixel CSP in this way, an area in which the size of the pad can be increased can be secured.

As such, a single sub-pixel CSP (Chip Scale Package) is a term distinct from a chip, and collectively refers to a small package close to the size of a chip. There is no wire for electrical connection with a lead frame that protects the appearance of the chip. It may be a package with a size close to that of a bare chip.

Referring to FIG. 12C , the area-extended R sub-pixel arrays 100R-SP1 and 100R-SP4 are transferred from a carrier substrate 200R to another carrier substrate 210R. This is a process for exposing the pad 14r to the outside for pad expansion. After attaching another carrier substrate 210R on the patterned photoresist layer 18R of the region-extended R sub-pixel arrays 100R-SP1 and 100R-SP4, the carrier substrate 200R is applied to the region-extended R sub-pixel arrays 100R-SP1 and 100R-SP4. It can be detached from the arrays 100R-SP1 and 100R-SP4. Here, in order to compare the other carrier substrate 210R with the carrier substrate 200R, it may be referred to as a carrier substrate for area expansion or may be referred to as an additional carrier substrate.

FIG. 12(D) is an upside-down view of FIG. 12(C). Referring to FIG. 12D , a state in which a photoresist 19 is coated and baked on the area-extended R sub-pixel arrays 100R-SP1 and 100R-SP4 is shown.

Referring to FIG. 13E , after the patterned photomask 500 is positioned on the photoresist 19 , the R sub-pixel arrays 100R-SP1 and 100R-SP4 on which the photomask 500 is disposed. UV exposure on the

Referring to FIG. 13F , when the photomask 500 is removed after UV exposure, only a portion requiring metal deposition is exposed as shown in FIG. 13F .

Referring to FIG. 13G , a metal M for pad extension is deposited to a predetermined thickness on the exposed R sub-pixel arrays 100R-SP1 and 100R-SP4.

Referring to (H) of FIG. 13 , after the deposition of the metal M for pad extension is completed, the photoresist ( 19), an extension pad 14R made of a pad extension metal may be formed on the pad 14r of the region-extended R sub-pixel arrays 100R-SP1 and 100R-SP4. The pad 14r and the expansion pad 14R are in contact and are electrically connected.

A comparison between the expanded pad and the normal size pad is the same as the description in FIG. 4 .

[Transfer process to display panel using LED sub-pixel CSP with expansion pad according to the first embodiment of the present invention]

Next, a selective transfer process for transferring sub-pixel arrays diced in the form of RGB sub-pixel CSPs 100R, 100G, and 100B on each wafer to the display panel as shown in FIG. 3 will be described.

The following drawings are described based on a cross-section arranged in rows (horizontal) in a matrix-arranged sub-pixel CSP array on a wafer.

FIG. 14 is a view for explaining in detail a step of transferring the sub-pixel CSP array shown in FIG. 1 to a carrier substrate.

The step of transferring the pixel CSP array to the carrier substrate may be referred to as 'primary transfer'.

Referring to FIG. 14 , each RGB wafer 10R, 10G, and 10B diced for each RGB sub-pixel CSP 100R, 100G, and 100B may be prepared.

Each of the RGB sub-pixel CSPs (100R, 100G, 100B) shows three for convenience of description, and the description is based on the R sub-pixel CSP ( 100R), and the G sub-pixel CSP ( 100G) and the B sub-pixel CSP ( 100B) ) can be replaced by the description of the R sub-pixel CSP 100R.

A carrier substrate 200 is attached to the upper surface of each of the sub-pixel CSPs 100R-SP1, 100R-SP2, and 100R-SP3.

Specifically, the carrier substrate 200 may be attached to the upper surface of the wafer 10R of each of the sub-pixel CSPs 100R-SP1, 100R-SP2, and 100R-SP3.

Here, the carrier substrate 200 may also be referred to as a 'transfer adhesive member', and an adhesive or adhesive is applied to PET, PP, PE, PS resin plates, etc., or these materials are thin in the form of a tape. An adhesive or a pressure-sensitive adhesive may be applied to one side while having it.

The carrier substrate 200 may have a predetermined ductility, and the carrier substrate 200 having a predetermined ductility may be made of a material that can be easily bent by an external force.

When the carrier substrate 200 is a material that can be easily bent, transfer efficiency can be further improved compared to the case where the carrier substrate 200 is made of a material that is not easily bent.

When the carrier substrate 200 is made of a material that is not easily bent, it is difficult to lift the carrier substrate at once after attaching each of the sub-pixel CSPs 100R-SP1, 100R-SP2, and 100R-SP3 to the carrier substrate. The reason is that the adhesive force between each of the sub-pixel CSPs 100R-SP1 , 100R-SP2 , and 100R-SP3 and the carrier substrate 200 is significant.

However, if the carrier substrate 200 is a material that is easily bendable, after attaching each of the sub-pixel CSPs 100R-SP1 , 100R-SP2 , and 100R-SP3 to the carrier substrate 200 , one When only the side portion is lifted upward, since the number of pixel CSPs attached only to the portion is relatively small, the entire carrier substrate 200 can be easily lifted with a small force.

Also, the carrier substrate 200 may be made of a transparent material. When the carrier substrate 200 is a transparent material, when transferring each sub-pixel CSP (100R-SP1, 100R-SP2, 100R-SP3) to the carrier substrate 200, the position adjustment and misalignment, etc. can be controlled by an externally provided vision. It has the advantage of being able to adjust or control it through a system (not shown).

Meanwhile, the carrier substrate 200 may also be referred to as a first transfer medium in the method of manufacturing a display device according to an embodiment of the present invention. A first adhesive force is formed between the first transfer medium and the pixel CSP array. Specifically, the first adhesive force may be 2,000 gf/25mm to 4,000 gf/25mm. More preferably, the first adhesive force may be 3,000 gf/25mm.

15 to 18 are diagrams for explaining in detail the step of transferring the sub-pixel CSP array transferred to the carrier substrate to the display panel.

15 is a view for explaining the structure of the display panel 300, (A) of FIG. 15 is an enlarged plan view of a portion of the display panel 300, (B) of FIG. 15 (A) ) is a side view of

Referring to FIG. 15 , the display panel 300 includes each pad of the plurality of sub-pixel CSPs 100R-SP1 … 100R-SP6, 100G-SP1 … 100G-SP6, 100B-SP1 … 100B-SP6 shown in FIG. 14 . A plurality of pads 31 electrically connected to 14 are included.

The plurality of pads 31 may be arranged on the upper surface of the display panel 300 , and the TFT array substrate 400 may be arranged under the display panel 300 .

The plurality of pads 31 are arranged along the row and column directions for each of the plurality of pad groups. Each pad group includes a plurality of pads electrically connected to one sub-pixel CSP.

Fig. 16 is a process for selectively transferring the R sub-pixel CSP array, Fig. 17 is a process for selectively transferring the G sub-pixel CSP array, and Fig. 18 is a process for selectively transferring the B sub-pixel CSP array .

When the selective transfer process for each RGB sub-pixel CSP of FIGS. 16 to 18 is performed, one RGB pixel CSP is formed, and a plurality of RGB pixel CSP arrays can be formed.

Referring to FIG. 16 , a solder paste 33 is applied on the plurality of pads 31 of the display panel 300 ( FIG. 16A ).

Here, the solder paste 33 is applied only on the pads 31-SP1 and 31-SP4 in rows 1 and 4, and the rest is not applied on the pads between rows 1 and 4.

One row of R sub-pixel CSP is selectively transferred to the pads in rows 1 and 4 (preferably pads arranged at intervals of the previous row + row 3), and then the pads in rows 2 and 3 between rows 1 and 4 One column of the G sub-pixel CSP and one column of the B sub-pixel CSP are sequentially transferred to (pads arranged at intervals of the previous column + three columns, respectively).

The solder paste 33 may be applied on the plurality of pads 31 of the display panel 300 through various methods such as screen printing, dispensing, jetting, and the like.

Next, referring to FIG. 16B , the carrier substrate 200 manufactured in FIG. 14 and the R sub-pixel CSPs 100R-SP1 ... 100R-SP6 attached to the carrier substrate 200 are combined with the display panel 300 . ), and pads 14 of some R sub-pixel CSPs (100R-SP1, 100R-SP4) among all R sub-pixel CSPs 100R-SP1 … 100R-SP6 are placed on the pad 31 of the display panel 300 . ) to the solder paste (33-SP1, 33-SP4) applied on it. Since there is no solder paste 33 under the remaining R sub-pixel CSPs (100R-SP2, 100R-SP3, 100R-SP4, 100R-SP5), the remaining R sub-pixel CSPs (100R-SP2, 100R-SP3, 100R) The pads 14 of -SP4 and 100R-SP5 cannot come into contact with the solder paste 33 .

After the pads 14 of some R sub-pixel CSPs 100R-SP1 and 100R-SP4 are in contact with the pads 31 of the display panel 300 through the solder pastes 33-SP1 and 33-SP4, for example, For example, when a predetermined amount of heat is applied using the Self Align Paste (SAP) soldering method, the solder particles contained in the solder pastes (33-SP1, 33-SP4) become part of the R sub-pixel CSP. It may be self-assembled between the pads 14 of the ( 100R-SP1 and 100R-SP4 ) and the pads 31 -SP1 and 31 -SP4 of the display panel 300 . Meanwhile, the thermosetting resin included in the solder paste 33 may be cured by heat.

Next, referring to FIG. 16C , the pads 14 of some R sub-pixel CSPs 100R-SP1 and 100R-SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300 are After soldering, the carrier substrate 200 separates some R sub-pixel CSPs 100R-SP1 and 100R-SP4.

Here, the soldering adhesive force between the pads 14 of some R sub-pixel CSPs 100R-SP1 and 100R-SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300 is the carrier substrate 200 and the carrier. Since the adhesive force between the substrate 200 and the wafer 10R is much greater, only the carrier substrate 200 and the remaining R sub-pixel CSPs 100R-SP1 and 100R-SP4 can be easily separated. Since the remaining R sub-pixel CSPs 100R-SP2, 100R-SP3, 100R-SP5, and 100R-SP6 are not soldered to the pad 31 of the display panel 300 , they remain attached to the carrier substrate 200 . It is separated together with the substrate 200 .

17 and 18 are the same process as in FIG. 16, except that FIG. 17 is different from selectively transferring the G sub-pixel CSP, and FIG. 18 is different from selectively transferring the B sub-pixel CSP.

In addition, if the R sub-pixel CSP is selectively transferred to the first and fourth columns of the display panel in FIG. 16, the G sub-pixel CSP is selectively transferred to the second and fifth columns in FIG. 18, and in FIG. 18, the B sub-pixel is transferred to the third and sixth columns The pixel CSP is selectively transferred. Specifically, the R sub-pixel CSP, the G sub-pixel CSP, and the B sub-pixel CSP may be selectively transferred at intervals of three columns.

When each RGB sub-pixel CSP is sequentially selectively transferred, an RGB pixel CSP is formed.

Referring to FIG. 17 , the solder paste 33 is applied only on the pads 31-SP2 and 31-SP5 in rows 2 and 5, and is not applied on the pads in the remaining rows 3 and 6 (31-SP3, 31-SP6). (FIG. 17A).

Solder paste applied to the pads 14 of some of the sub-pixel CSPs (100G-SP2, 100G-SP5) among all the G sub-pixel CSPs (100G-SP1 … 100G-SP6) on the pad 31 of the display panel 300 After making contact with (33-SP2, 33-SP5) (FIG. 17B), the pad 14 of some sub-pixel CSPs 100G-SP2, 100G-SP5 and the pad 31-SP2 of the display panel 300 , 31-SP5 are soldered, the carrier substrate 200 is separated from some sub-pixel CSPs 100G-SP2 and 100G-SP5 ( FIG. 17C ).

Referring to FIG. 18 , the solder paste 33 is applied only on the pads 31-SP3 and 31-SP6 in the third and sixth rows ( FIG. 18A ).

Solder paste applied to the pads 14 of some of the sub-pixel CSPs 100B-SP3 and 100BG-SP6 among all the B sub-pixel CSPs 100B-SP1 … 100B-SP6 on the pad 31 of the display panel 300 . After contacting (33-SP3, 33-SP6) (FIG. 18B), the pad 14 of some sub-pixel CSPs (100G-SP3, 100G-SP6) and the pad 31-SP3 of the display panel 300 , 31-SP6 are soldered, the carrier substrate 200 is separated from some sub-pixel CSPs 100B-SP3 and 100B-SP6 ( FIG. 18C ).

19 is a view showing a comparison before and after region movement of an electrode pad of a display panel.

19 illustrates a pad array of a display panel, which may have an arrangement corresponding to a plurality of pads of one sub-pixel CSP 100R, 100G, 100B illustrated in FIG. 3 .

19 (A1), (B1), and (C1) are layout diagrams of pads on a conventional display panel, and (A2), (B2) and (C2) are layout diagrams of pads on a display panel according to an embodiment of the present invention. Yes.

In the case of the micro LED, since the size thereof is very small, the distance d1 between the pads of the display panel corresponding thereto is also very narrow. In the embodiment of the present invention, a short circuit due to solder paste between the pads can be prevented in advance by widening the interval d2 between the pads of the display panel.

The interval between the pads has a relationship of d1 < d2, and d2 can be implemented by moving the regions from the respective positions of the pads 140 and 140 ′ to the left and right, respectively.

The precondition for widening the gap between the pads 140 and 140' of the display panel is as follows.

The embodiment of the present invention proposes the first transfer and/or the second transfer as a method for simultaneously transferring the plurality of sub-pixel CSPs 100 shown in FIG. 3 to the display panel 300 at a high speed. Here, the second transfer employs a transfer method using a difference in adhesive force between the carrier substrate 200 and the solder paste 170 .

Therefore, in order to implement the second transfer, the solder paste 170 must be applied on the pad 140 of the display panel 300, and in this case, the white ink ( White ink) is applied first.

If the gap between the pads 14 and 14' of the display panel is very narrow (100 μm or less) as in the prior art, the white ink 15 cannot be filled between the pads 14 and 14', and the white ink A step may be formed between the pads 14 and 14' in which the (15) is not filled, and the solder paste 17 may be trapped, resulting in a short circuit due to the remaining solder paste.

Therefore, in the embodiment of the present invention, in order to solve the above problem, the space d2 between the pads 140 and 140' is widened by moving the pads 140 and 140' of the display panel 300 from side to side. A white ink dam can be formed by the white ink 150 .

That is, the gap between the pads 140 and 140 ′ is widened so that white ink can be filled between the pads.

With the formation of the white ink dam, the step difference between the pads 140 and 140 ′ can be removed, and the cause of the short circuit between the electrodes can be eliminated because residual solder paste is not generated.

Next, as described above, if the electrode spacing is widened by the preemptive condition of widening the spacing between the pads 140 and 140' of the display panel, the possible conditions for widening the electrode spacing are as follows.

A possible condition for widening the distance between the pads 140 and 140' of the display panel 300 is that the pads 14R, 14R', 14G, and 14B of the sub-pixel CSP 100 are extended as shown in FIG. 4 above. it is possible by

20 is a view for explaining in detail the step of transferring the pixel CSP array having the extended pad transferred to the carrier substrate to the display panel.

Referring to FIG. 20A , solder paste 170 is applied on the plurality of pads 140 of the display panel 300 .

The solder paste 170 may be applied on the plurality of pads 140 of the display panel 300 through various methods such as screen printing, dispensing, jetting, and the like.

Next, referring to FIG. 20B , the carrier substrate 200 and the wafer layer 10 attached to the carrier substrate 200 are moved onto the display panel 300 , and the pads 14R of each sub-pixel CSP are , 14R′) is brought into contact with the solder pastes 170 and 170′ applied on the pads 140 and 140′ of the display panel 300 .

After the pads 14R, 14R' of each pixel CSP and the pads 140 and 140' of the display panel 300 are in contact with each other through the solder pastes 170 and 170', for example, a self-aligning paste (Self Alignment) When a predetermined heat is applied using the Paste, SAP) soldering method, the solder particles contained in the solder paste (170, 170') are transferred to the pads (14R, 14R') of the Pixel CSP and the display panel (300). It may be self-assembled between the pads 140 and 140'.

Meanwhile, the thermosetting resin included in the solder pastes 170 and 170 ′ may be cured by heat.

Next, referring to FIG. 20C , when the pads 14R and 14R' of the sub-pixel CSP and the pads 140 and 140' of the display panel 300 are soldered, the carrier substrate 200 is transferred to the wafer ( 10) is removed from it.

Here, since the soldering adhesion between the pads 14R and 14R' of the sub-pixel CSP and the pads 140 and 140' of the display panel 300 is much greater than the adhesion between the carrier substrate 200 and the wafer 10, Only the carrier substrate 200 can be easily separated.

Referring to FIG. 20 , it is possible to widen the distance between the pads 140 and 140' of the display panel 300 by the first and second pads 14R and 14R' of the sub-pixel CSP, that is, the pads ( 140, 140') is possible.

That is, it is possible to improve the contact margin ratio between the electrodes between the pixel CSP and the display panel 300 during the transfer process by using the pads 14R and 14R′ that are extended than the conventional pads, and the pad 140, 140'), it is possible to move the same area as the widening of both sides, so that it is possible to block the occurrence of short circuit between electrodes.

In particular, this contact margin rate and short-circuit prevention can ensure the speed and accuracy of the transfer process when applied to a display device to which a micro LED is applied.

[Transfer process to display panel using LED sub-pixel CSP with expansion pad according to the second embodiment of the present invention]

21 illustrates a process in which the pad-extended R sub-pixel CSP array is secondary transferred from the carrier substrate to the display panel.

Referring to FIG. 21 , (A) shows the pads 31-SP1 to 31-SP6 of the display panel 300 , and (B) is the display panel 300 on the display panel 300 of FIG. 11B . A state in which the pad-extended R sub-pixel array is secondarily transferred onto the display panel 300 by aligning the carrier substrate 200R is shown.

Pads 31-SP1 ?? 31-SP6 are formed in columns 1 to 6 of the display panel 300 , and solder pastes 33-SP1 and 33-SP4 are formed in columns 1 and 4, and the corresponding columns The pad-extended R sub-pixels CSP (100R-SP1, 100R-SP4), respectively, are transferred to the positions.

However, although it is illustrated that the solder paste is formed on only the first and fourth columns on the pad of the display panel 300 , the solder pastes 33-SP1 ?? 33-SP6 may be formed on all the columns. The reason is that the first row and the fourth row have already been selectively picked up and transferred on the carrier substrate 200R.

22 is a cross-sectional view illustrating in more detail a process of transferring from another carrier substrate to a display panel in FIG. 21 .

Referring to FIG. 22A , solder paste 33 is applied on the plurality of pads 31 of the display panel 300 .

A TFT array substrate 400 may be disposed under the display panel 300 .

Here, the solder paste 33 may be applied only on the pads 31-SP1 and 31-SP4 in rows 1 and 4, but may also be applied on the remaining pads.

One row of R sub-pixel CSP is selectively transferred to the pads in rows 1 and 4 (preferably pads arranged at intervals of the previous row + row 3), and then the pads in rows 2 and 3 between rows 1 and 4 One column of the G sub-pixel CSP and one column of the B sub-pixel CSP are sequentially transferred to (pads arranged at intervals of the previous column + three columns, respectively).

The solder paste 33 may be applied on the plurality of pads 31 of the display panel 300 through various methods such as screen printing, dispensing, jetting, and the like.

Next, referring to FIG. 22B , R sub-pixel CSPs 100R-SP1 and 100R-SP4 attached to another carrier substrate 210R manufactured in FIG. 4 and having an expansion pad 14R are formed on a display panel. Solder pastes 33-SP1 and 33 applied on the pad 31 of the display panel 300 by placing the extension pad 14R of the R sub-pixel CSPs 100R-SP1 and 100R-SP4 on the 300 . -SP4).

After the expansion pad 14R of some R sub-pixel CSPs (100R-SP1, 100R-SP4) and the pad 31 of the display panel 300 are in contact with the solder paste (33-SP1, 33-SP4), Yes For example, when a certain amount of heat is applied using the Self Align Paste (SAP) soldering method, the solder particles contained in the solder pastes (33-SP1, 33-SP4) become some R sub-pixels. It may be self-assembled between the expansion pads 14R of the CSPs 100R-SP1 and 100R-SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300 .

Meanwhile, the thermosetting resin included in the solder paste 33 may be cured by heat.

Next, referring to FIG. 22C , the expansion pads 14R of some R sub-pixel CSPs 100R-SP1 and 100R-SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300 are shown. When is soldered, the other carrier substrate 210R is separated.

Here, the carrier substrate 210R having different soldering adhesion between the expansion pads 14R of some R sub-pixel CSPs 100R-SP1 and 100R-SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300 . Since the adhesive force between the and R sub-pixel CSPs 100R-SP1 and 100R-SP4 is much greater, only the other carrier substrates 210R can be easily separated.

Next, FIGS. 23 to 25 show that the G (Green) chip array is selectively transferred to the carrier substrate, and the region of the G (Green) chip selectively transferred to the carrier substrate is expanded to form a G sub-pixel CSP, and the G sub-pixel CSP is formed. It is a drawing for explaining in detail the step of extending the pad of the sub-pixel CSP and selectively sequentially transferring the G (Green) sub-pixel CSP having the expanded pad to the display panel.

23 shows a process of primary transfer of a G chip array from a G wafer to a carrier substrate, (A) is a front view of the G wafer (10G), (B) is a G wafer ( 10G) is a front view of the primary transfer of rows 1 and 4, (C) shows the XX cross-sectional view of (B).

Referring to FIG. 23 , the G wafer 10G of (A) has undergone the processes of FIGS. 6 and 7 , and the carrier substrate 200G of FIG. 9 is aligned to the G wafer 10G and brought into contact with the carrier substrate When (200G) is separated, the G chip arrays in rows 1 and 4 of the G wafer 10G in (A) are picked up and transferred to become empty, and as shown in (B)/(C), the G chip arrays in rows 2 and 5 (100G) -SP1 and 100G-SP4 are transferred to the carrier substrate 200G.

The carrier substrate 200G may have the same material and the same properties as the carrier substrate 200R.

Referring to FIG. 23C , when the first and fourth rows of G chip arrays 100G-SP1 and 100G-SP4 are transferred to the carrier substrate 200G, the first and fourth rows of G chip arrays 100G-SP1 and 100G - The pad 14g side of SP4 is transferred to the carrier substrate 200G. This is for area expansion and pad expansion. Since the area expansion and the pad expansion are the same as those of FIGS. 12 and 13 described above, a description thereof will be omitted.

24 shows a process of secondary transfer of the pad-extended G sub-pixel CSP array from the carrier substrate to the display panel.

Referring to FIG. 24 , (A) shows the pads 31-SP1 to 31-SP6 of the display panel 300. R sub-pixel arrays are arranged in columns 1 and 4 through the processes of FIGS. 21 to 22. is a transferred state, and (B) shows a state in which the pad-extended G sub-pixel array is secondarily transferred onto the display panel 300 by aligning the carrier substrate 200G on the display panel 300 .

Pads 31-SP1 ?? 31-SP6 are formed in columns 1 to 6 of the display panel 300 , and solder pastes 33-SP2 and 33-SP5 are formed in columns 2 and 5, and the corresponding columns Each pad-extended G sub-pixel CSP (100G-SP1, 100G-SP4) is transferred to the position.

However, although it is illustrated that the solder paste is formed on only the second and fifth columns on the pad of the display panel 300 , the solder pastes 33-SP3 and 33-SP6 may be formed on the third and sixth columns. The reason is that the second and fifth rows have already been selectively picked up and transferred on the carrier substrate 200G.

25 is a cross-sectional view illustrating in more detail a process of transferring from another carrier substrate to a display panel in FIG. 24 .

Referring to FIG. 25A , solder paste 33 is applied on the plurality of pads 31 of the display panel 300 , and R sub-pixels that have already been pad-extended in the previous step in rows 1 and 4 The CSP arrays 100R-SP1 and 100R-SP4 are positioned in a transcribed state.

Here, the solder paste 33 may be applied only on the pads 31-SP2 and 31-SP5 in the second and fifth rows, but may also be applied on the remaining pads.

Next, referring to FIG. 25B , a G sub-pixel CSP 100G having an expansion pad 14G attached to another carrier substrate 210G manufactured by the same method as those shown in FIGS. 12 and 13 . -SP1, 100G-SP4) is placed on the display panel 300, and the expansion pad 14G of the G sub-pixel CSP (100G-SP1, 100G-SP4) is placed on the pad 31 of the display panel 300 Contact the applied solder paste (33-SP2, 33-SP5).

After the expansion pad 14G of the G sub-pixel CSP (100G-SP1, 100G-SP4) and the pad 31 of the display panel 300 are in contact with the solder paste (33-SP2, 33-SP5), for example, For example, when a predetermined heat is applied using the Self Align Paste (SAP) soldering method, the solder particles contained in the solder pastes (33-SP2, 33-SP5) become It may be self-assembled between the expansion pads 14G of the 100G-SP1 and 100G-SP4 and the pads 31-SP2 and 31-SP5 of the display panel 300 .

Next, referring to FIG. 25C , the expansion pads 14G of the G sub-pixel CSPs 100G-SP1 and 100G-SP4 and the pads 31-SP2 and 31-SP5 of the display panel 300 are After soldering, the other carrier substrate 210G is separated.

Here, the carrier substrate 210G having different soldering adhesion between the expansion pad 14G of the G sub-pixel CSPs 100G-SP1 and 100G-SP4 and the pads 31-SP2 and 31-SP5 of the display panel 300 is Since the adhesive force between the G sub-pixel CSPs 100G-SP1 and 100G-SP4 is much greater, only the different carrier substrates 210G can be easily separated.

Next, FIGS. 26 to 28 show that the B (Blue) chip array is selectively transferred to the carrier substrate, and the region of the B (Blue) chip selectively transferred to the carrier substrate is expanded to form a B sub-pixel CSP, It is a drawing for explaining in detail the step of extending the pad of the B sub-pixel CSP and selectively sequentially transferring the B (Blue) sub-pixel CSP having the expanded pad to the display panel.

26 shows a process in which a B chip array is first transferred from a B wafer to a carrier substrate, (A) is a front view of the B wafer 10B, and (B) is a B wafer ( 10B) is a front view in which rows 1 and 4 are first transcribed, (C) is a XX cross-sectional view of (B).

Referring to FIG. 26 , the B wafer 10B of (A) is a state that has gone through the processes of FIGS. 6 and 7 , and the carrier substrate 200B of FIG. 10 is aligned with the B wafer 10B and contacted with the carrier substrate When 200B is separated, the B chip arrays in rows 1 and 4 of the B wafer 10B in (A) are picked up and transferred to become empty, and as shown in (B)/(C), the B chip arrays 100B in rows 3 and 6 -SP1 and 100B-SP4 are transferred to the carrier substrate 200B.

The carrier substrate 200B may have the same material and the same properties as the carrier substrates 200R and 200G.

Referring to FIG. 26C , when transferring the first and fourth columns of B chip arrays 100B-SP1 and 100B-SP4 to the carrier substrate 200B, the first and fourth columns of the B chip arrays 100B-SP1 and 100B - The pad 14b side of SP4 is transferred to the carrier substrate 200B. This is for area expansion and pad expansion. Since the area expansion and the pad expansion are the same as those of FIGS. 12 and 13 described above, a description thereof will be omitted.

27 illustrates a process in which the pad-extended B sub-pixel CSP array is transferred from the carrier substrate to the display panel.

Referring to FIG. 27 , (A) shows the pads 31-SP1 to 31-SP6 of the display panel 300, which is 1 through the processes of FIGS. 21 to 22 and FIGS. 24 to 25 . R sub-pixel CSP arrays are transferred to columns and 4 columns, and G sub-pixel CSP arrays are transferred to columns 2 and 5. A state in which the pad-extended B sub-pixel CSP array by alignment is secondarily transferred onto the display panel 300 is shown.

Pads 31-SP1 ?? 31-SP6 are formed in columns 1 to 6 of the display panel 300 , and solder pastes 33-SP3 and 33-SP6 are formed in columns 3 and 6, and the corresponding columns The pad-extended B sub-pixels CSPs 100B-SP1 and 100B-SP4, respectively, are transferred to the positions.

28 is a cross-sectional view illustrating in more detail a process of transferring from another carrier substrate to a display panel in FIG. 27 .

Referring to (A) of FIG. 28 , solder paste 33 is applied on the plurality of pads 31 of the display panel 300, and in each of the 1st and 4th columns, the 2nd and 5th columns, it is already in the previous step. The pad-extended R sub-pixel CSP arrays 100R-SP1 and 100R-SP4 and the pad-extended G sub-pixel CSP arrays 100G-SP1 and 100G-SP4 are positioned in a transferred state.

Next, referring to FIG. 28B , the B sub-pixel CSP 100B having an expansion pad 14B attached to another carrier substrate 210B manufactured by the same method as that shown in FIGS. 12 and 13 . -SP1, 100B-SP4) is placed on the display panel 300, and the expansion pad 14B of the B sub-pixel CSP (100B-SP1, 100B-SP4) is placed on the pad 31 of the display panel 300 Contact the applied solder paste (33-SP3, 33-SP6).

After the expansion pad 14B of the B sub-pixel CSP (100B-SP1, 100B-SP4) and the pad 31 of the display panel 300 are in contact with the solder paste (33-SP3, 33-SP6), for example, For example, when a predetermined heat is applied using the Self Align Paste (SAP) soldering method, the solder particles contained in the solder paste (33-SP3, 33-SP6) are converted into the B sub-pixel CSP (CSP). It may be self-assembled between the expansion pads 14B of the 100B-SP1 and 100B-SP4 and the pads 31-SP3 and 31-SP6 of the display panel 300 .

Next, referring to FIG. 28C , the extension pads 14B of the B sub-pixel CSPs 100B-SP1 and 100B-SP4 and the pads 31-SP3 and 31-SP6 of the display panel 300 are After soldering, the other carrier substrate 210B is separated.

Here, the carrier substrate 210B having different soldering adhesion between the extension pads 14B of the B sub-pixel CSPs 100B-SP1 and 100B-SP4 and the pads 31-SP3 and 31-SP6 of the display panel 300 and Since the adhesive force between the B sub-pixel CSPs 100B-SP1 and 100B-SP4 is much greater, only the different carrier substrates 210B can be easily separated.

If the processes of FIGS. 21 to 28 are sequentially applied in this way, it is possible to manufacture a display panel in which one complete RGB pixel CSP array is arranged, and the R wafer 10R, G of FIGS. 11, 23 and 26 , respectively. Each of the R, G, and B chip arrays formed on the wafer 10G and the B wafer 10B can be used sequentially and selectively from the first row to the last row.

Meanwhile, as in FIGS. 19 and 20, when configuring a display or device by moving the pad area of the display panel, the electrical connection problem (open, sort failure) occurring in the conventional chip-unit surface mounting process can be solved. have.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified with respect to other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the embodiment has been mainly described in the above, it is only an example and does not limit the present invention, and those of ordinary skill in the art to which the present invention pertains to the above in the range that does not depart from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications not illustrated are possible. For example, each component specifically shown in the embodiment can be implemented by deformation|transformation. And differences related to such modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

10R, 10G, 10B: Wafer
100R, 100G, 100B: Sub-pixel CSP
200: carrier substrate
300: display panel
400: TFT array substrate

Claims (9)

base substrate;
at least one Red LED, Green LED or Blue LED formed on the base substrate; and
A pair of expansion pads having an area extended to each of the one or more Red LEDs, Green LEDs or Blue LEDs; includes;
Each of the one or more Red LED, Green LED or Blue LED constitutes one CSP (Chip Scale Package) type LED sub-pixel CSP,
forming a photoresist layer covering each of the at least one Red LED, Green LED or Blue LED on the base substrate;
The LED sub-pixel CSP having an expansion pad, wherein the expansion pad is formed to extend over the photoresist layer. According to claim 1,
The base substrate is a wafer,
An LED sub-pixel CSP having an expansion pad, which is a carrier substrate on which each of the one or more Red LED, Green LED, or Blue LED formed on the wafer is transferred. 3. The method of claim 2,
When the base substrate is a wafer, the expansion pad is formed on the wafer,
The LED sub-pixel CSP having an expansion pad, wherein when the base substrate is a carrier substrate, the expansion pad is formed on the carrier substrate. According to claim 1,
wherein the expansion pad extends from the pad of each light emitting element within one of the LED sub-pixel CSPs and does not intersect the pad extending from an adjacent LED sub-pixel CSP. According to claim 1,
The LED sub-pixel CSP having an expansion pad, wherein a pitch between the one or more Red LED, Green LED, or Blue LED formed on the base substrate is formed based on an area expansion for forming the expansion pad. 6. The method of claim 5,
The base substrate is a carrier substrate to which each of the one or more Red LED, Green LED or Blue LED formed on the wafer is transferred,
The expansion pad,
An LED sub-pixel CSP having an expansion pad, which is formed by a lift-off process after a photomask is placed on the photoresist layer and metal is deposited on a portion exposed through UV exposure. According to claim 1,
The pair of expansion pads is formed to extend out of an area in which each of the at least one Red LED, Green LED or Blue LED is formed, the LED sub-pixel CSP having an expansion pad. According to claim 1,
The pair of expansion pads has a shape extending from side to side through metal deposition on each pad of the one or more Red LED, Green LED or Blue LED, LED sub-pixel CSP having an expansion pad.
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