KR102173102B1 - Probe card, testing apparaus and method using the probe card, manufacturing method of display apparatus using this same and display apparatus manufactured by that method - Google Patents

Abstract

The present invention relates to a probe card, a test device and a test method using the probe card, a method of manufacturing a display device, and a display device manufactured by the method, capable of testing electrical connection characteristics and optical characteristics of a sub-pixel CSP. According to an embodiment of the present invention, the test device using the probe card includes: a probe card including a base substrate having a plurality of openings, and at least two probe pins disposed in the openings, respectively, and electrically connected to the base substrate; and a carrier substrate to which a plurality of sub-pixel CSPs having one-to-one correspondence with the openings are transferred. The sub-pixel CSPs are arranged in rows and columns on one plane of the carrier substrate, and two adjacent sub-pixel CSPs among the sub-pixel CSPs are spaced apart from each other by a predetermined interval so as to form an air gap therebetween. Each of the sub-pixel CSPs includes: a chip; a photoresist layer surrounding the chip; a pad exposed to an outside of the photoresist layer; and an expansion pad disposed on the pad, having a larger surface area than the pad, and making contact with the probe pin, wherein a test signal for testing electrical and optical characteristics is applied to the sub-pixel CSP through the probe pin.

Description

A probe card, a test device and a method using the same, a method of manufacturing a display device, and a display device manufactured by the method. THAT METHOD}

The present invention relates to a probe card, a test device and method using the probe card, a method of manufacturing a display device, and a display device manufactured by the method.

Light Emitting Diode (LED) is one of light emitting devices that emit light when current is applied. Light-emitting diodes can emit high-efficiency light with low voltage, so they have excellent energy saving effects.

Recently, the problem of luminance of light emitting diodes has been greatly improved, and thus, it has been applied to various devices such as backlight units of liquid crystal display devices, electric signs, displays, and home appliances.

The size of a micro light emitting diode (μ-LED) is very small, ranging from 1 to 100 μm, and approximately 25 million or more pixels are required to implement a 40-inch display device.

Therefore, there is a problem in that it takes at least one month in time by a simple pick & place method to make one 40-inch display device.

Existing micro light-emitting diodes (μ-LEDs) are manufactured in plural on a sapphire substrate, and then, by a mechanical transfer method, pick & place, the micro light-emitting diodes are one by one on a glass or flexible substrate. Is transferred.

Since the micro light emitting diodes are picked up one by one and transferred, it is referred to as a 1:1 pick-and-place transfer method.

However, since the micro light emitting diode chip fabricated on the sapphire substrate is small in size and thin, the chip is damaged, the transfer fails, or the chip is aligned during the pick-and-place transfer process of transferring the micro light emitting diode chips one by one. There is a problem such as alignment failure or a chip tilt.

In addition, there is a problem that the time required for the transfer process takes too long.

Republic of Korea Patent Publication 10-2019-0096256

The present invention provides a probe card capable of testing electrical connection characteristics and optical characteristics of a sub-pixel CSP that is selectively transferred to a carrier substrate to extend a region and a pad, and a probe test apparatus and method using the same.

In addition, multiple RGB chips are selectively picked up using a carrier substrate, and the area is expanded by forming an RGB sub-pixel CSP, and the pad is expanded, and the electrical connection characteristics and optical characteristics of the pad-extended sub-pixel CSP are tested. Thus, a method of manufacturing a display device that can be selectively and sequentially transferred to a display panel, and a display device manufactured by the method are provided.

In addition, there is provided a method of manufacturing a display device capable of rapidly manufacturing a micro LED-based display device and minimizing a transfer error, and a display device manufactured by the method.

In addition, there is provided a method of manufacturing a display device capable of manufacturing a display device having various sizes and various pitches between pixels, and a display device manufactured by the method.

In addition, a method of manufacturing a display device capable of using a wafer having as many RGB pixels as possible on a limited area regardless of the resolution of the display device, and a display device manufactured by the method are provided.

In addition, there is provided a method of manufacturing a display device capable of rapidly manufacturing a large-area display device, and a display device manufactured by the method.

The problem to be solved of the present invention is not limited to the problems mentioned above, and other problems that are not mentioned can be clearly understood by those of ordinary skill in the technical field to which the present invention belongs from the following description. will be.

A probe card according to an embodiment of the present invention includes: a base substrate having a plurality of openings; At least two probe pins disposed in each of the openings and electrically connected to the base substrate, wherein the probe pins are electrically connected to expansion pads of a plurality of sub-pixels CSP transferred in a matrix to a carrier substrate.

In addition, a test apparatus using a probe card according to an embodiment of the present invention includes: a probe card including a base substrate having a plurality of openings, and at least two probe pins disposed in each of the openings and electrically connected to the base substrate; And a carrier substrate to which a plurality of sub-pixels CSPs corresponding to one-to-one corresponding to the plurality of openings are transferred, wherein each of the sub-pixels CSP includes an expansion pad in contact with the probe pin, and the sub-pixel CSP Test signals are applied to the pixel CSP for testing electrical and optical properties.

In addition, a test method using a probe card according to an embodiment of the present invention includes an area expansion step of expanding an area of each of a plurality of chips transferred to a carrier substrate through subpixel CSP formation; A pad expansion step of forming an expansion pad by transferring the region-extended subpixel CSPs to a carrier substrate for pad expansion; And a base substrate having a plurality of openings corresponding to the sub-pixel CSPs in a one-to-one manner, and the probe pins of a probe card including probe pins disposed in the openings to contact the expansion pads of the sub-pixel CSP, and the sub-pixel CSP. To test the electrical and optical properties of the, test measurement and evaluation steps; includes.

In addition, a method of manufacturing a display device according to an embodiment of the present invention includes an area expansion step of expanding an area of each of a plurality of chips transferred to a carrier substrate through subpixel CSP formation; A pad expansion step of forming an expansion pad by transferring the region-extended subpixel CSPs to a carrier substrate for pad expansion; A base substrate having a plurality of openings corresponding to the sub-pixel CSPs one-to-one and the probe pins of a probe card including probe pins disposed in the openings are brought into contact with the expansion pads of the sub-pixel CSP, and the sub-pixel CSP is Test measurement and evaluation steps to test electrical and optical properties; And a transfer step of sequentially transferring the sub-pixel CSPs from the pad expansion carrier substrate to the display panel based on a result of the test measurement step.

Further, the display device according to the present invention can be manufactured by the above-described manufacturing method of the display device.

If the probe card according to the embodiment and the probe test method and apparatus using the same are used, there is an advantage that it is possible to test electrical connection characteristics and optical characteristics of the subpixel CSP, which is selectively transferred to a carrier substrate and extended to a region and a pad. Therefore, the pad size can be scaled up as an expansion pad due to the area and pad expansion of the sub-pixel CSP, and thus there is an advantage in that a sufficient space can be measured with a probe card.

In addition, if the method of manufacturing a display device according to the embodiment and a display device manufactured by the method are used, chips are manufactured on each wafer, and primary selective sequential transfer using a carrier substrate is possible, and a carrier substrate Sufficient space that can be measured with a probe card is possible as each chip can be expanded and pads can be expanded by forming sub-pixel CSPs, and electrical connection characteristics and optical characteristics can be tested using a probe card for each sub-pixel CSP with a pad expansion. Can be obtained, and secondary selective sequential transfer of each sub-pixel CSP extended by the pad from the carrier substrate to the display panel is possible.

In addition, the manufacturing method of the display device according to the embodiment and the display device manufactured by the method do not control the micro-class light emitting devices one by one, and can quickly transfer a plurality of light emitting devices to the display panel at once, so the display device There is an advantage that can significantly reduce the manufacturing cost and time.

In addition, the manufacturing method of the display device according to the embodiment and the display device manufactured by the method use a large difference in adhesion between transfer media, not a method of controlling physical force or adhesion such as electrostatic attraction, so transfer success rate There is an advantage that can be maximized.

In addition, there is an advantage in that a display device having various sizes and various pitches between sub-pixels can be manufactured.

In addition, since each wafer in which as many RGB chips are formed on a limited area irrespective of the resolution of the display device is used, it is possible to reduce the cost of manufacturing a wafer and does not require a color conversion layer forming process.

In addition, when manufacturing a large-area display device, there is an advantage in that the transfer method can be rapidly manufactured by changing the position and repeatedly executing the transfer method.

1 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention.
2 is a diagram in which RGB chips are formed on each wafer according to an embodiment of the present invention.
3 is a process diagram of forming respective RGB chips on each wafer according to an embodiment of the present invention.
4 is a process diagram of dicing each RGB chip formed on each wafer according to an embodiment of the present invention in a chip unit.
5 is a front view showing that a chip array having a general pad is formed on a wafer.
6 to 8 are diagrams showing a structure of a carrier substrate for selectively transferring the chip array shown in FIG. 1 by a carrier substrate.
9 to 18 show that the R (Red) chip array is selectively transferred to the carrier substrate, and the R (Red) chip selectively transferred to the carrier substrate is expanded by forming a sub-pixel CSP to expand an area and a pad. These are drawings for explaining in detail the step of selectively sequentially transferring the R (Red) sub-pixel CSP having the pads to the display panel.
19 to 21 are diagrams for describing a probe test process in detail.
22 to 24 show that the G (Green) chip array is selectively transferred to the carrier substrate, and the G (Green) chip selectively transferred to the carrier substrate is expanded by forming a sub-pixel CSP to expand an area and a pad. These are drawings for explaining in detail a step of selectively sequentially transferring the G (Green) sub-pixel CSP having the pads to the display panel.
25 to 27 show that the B (Blue) chip array is selectively transferred to the carrier substrate, and the B (Blue) chip selectively transferred to the carrier substrate is expanded by forming a sub-pixel CSP to expand an area and a pad. These are drawings for explaining in detail the step of selectively sequentially transferring the B (Blue) sub-pixel CSP having the pads to the display panel.
28 is a view showing a comparison before and after movement of an electrode pad of a display panel.
FIG. 29 is a diagram for describing in detail a step of transferring a subpixel CSP array having an extended pad transferred to a carrier substrate to a display panel.
30 to 31 are exemplary diagrams of a process in which each RGB chip formed on each wafer is selectively transferred to a display panel in column units according to an embodiment of the present invention.

In the description of the embodiment, in the case of being described as being formed on the “top (top) or bottom (bottom)” of each component, the top (top) or bottom (bottom) of the two components directly contact each other Or one or more other components are disposed between the two components.

In addition, when expressed as "upper (upper) or lower (lower)", the meaning of not only an upward direction but also a downward direction based on one component may be included.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. Also, the size of each component does not fully reflect the actual size.

1 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention.

Referring to FIG. 1, a method of manufacturing a display device according to an embodiment of the present invention includes forming a plurality of RGB chips on each wafer (S110), and dicing each wafer for each chip ( S120), selectively transferring the RGB chip array to the carrier substrate (S150), forming an RGB sub-pixel CSP by expanding the area of the RGB chip selectively transferred to the carrier substrate and expanding the pad of each RGB sub-pixel CSP Step S160, measuring and evaluating electrical and optical characteristics through a probe card (S170), and sequentially transferring the RGB subpixel CSP array selectively transferred to the carrier substrate to the display panel (S180).

Steps S110, S120, S150, S160, S170, and S180 will be described in detail below with reference to the accompanying drawings.

2 is a diagram in which RGB chips are formed on each wafer according to an embodiment of the present invention.

As shown in FIG. 2, the embodiment of the present invention describes three wafers each formed with RGB chips as an example, but is not limited thereto.

Referring to FIG. 2, a plurality of light-emitting elements 11R, 11G, and 11B that emit light of the same wavelength band are formed on each of the wafers 10R, 10G, and 10B.

Here, the light emitting elements 11R, 11G, and 11B may be light emitting chips that emit red, green, and blue light.

The plurality of light emitting devices 11R, 11G, and 11B may be arranged at equal intervals along a plurality of rows and columns on each wafer 10R, 10G, and 10B.

Since the light-emitting elements 11R, 11G, and 11B arranged at equal intervals are transferred to the display panel later in the row or column direction, the manufacturing cost of the light-emitting element can be reduced by efficiently utilizing the entire area of a relatively expensive wafer.

Meanwhile, after forming a plurality of RGB chips on each of the wafers 10R, 10G, and 10B, the wafer may be diced for each RGB chip to separate each of the RGB chips.

It is preferable that the pitch W between the RGB chips formed on each of the wafers 10R, 10G, and 10B is equal to the pitch between the sub-pixels CSP formed on the display panel or as a multiple of a proportional constant of a predetermined value.

3 is a process diagram of forming respective RGB chips on each wafer according to an embodiment of the present invention.

Referring to FIG. 3, epis 11R, 11G, and 11B emitting predetermined light are grown on one surface of each of three wafers 10R, 10G, and 10B.

Here, the wafers 10R, 10G, and 10B may be a sapphire (Al2O3) substrate.

Protection by forming pads 14r, 14g, 14b on each of the grown epis 11R, 11G, 11B, and passivating the epis 11R, 11G, 11B and pads 14r, 14g, 14b A layer 13 is formed. Here, the pads 14r, 14g, and 14b are not expanded and may have the size and shape of a general pad.

When forming the protective layer 13, it is preferable to form the pads 14r, 14g, and 14b so as to be exposed to the outside of the protective layer 13 in order to expand the pad area thereafter.

In FIG. 3, the AA section and the BB section in FIG. 1 are respectively represented, and preferably, a pair of (+) and (-) electrodes per chip are formed under the Epi layer, based on the AA section. Of course, it can be formed up and down, and it is also possible to form it left and right as needed.

4 is a process diagram of dicing each of the RGB chips formed on each wafer according to an embodiment of the present invention in a single chip unit.

Referring to FIG. 4, as shown in FIG. 3, epitaxial (11R, 11G, 11B) and pads (14r, 14g, 14b) are formed on a wafer, and a plurality of RGB chips are diced for each RGB chip on which the protective layer 13 is formed. Chips 100R, 100G, and 100B are formed.

Here, there may be various methods of dicing for each of the RGB chips 100R, 100G, and 100B, but dicing may be performed using a laser as an example.

In the following drawings, one RGB chip (100R, 100G, 100B) is shown as the RGB chip (100R, 100G, 100B) formed in FIG. 4, but is not limited thereto, and dies in the row and column directions in FIG. It may also be an array of synchronized RGB chips 100R, 100G, 100B.

Each of the RGB chips 100R, 100G, and 100B may have a flip chip structure that does not require a wire.

Electrical connection is possible with pads (14r, 14g, 14b) instead of wires, and each of the RGB chips (100R, 100G, 100B) emits light of various colors according to external control signals through pads (14r, 14g, 14b) can do.

In addition, in the present invention, each of the RGB chips 100R, 100G, and 100B may be a small package of a new concept manufactured in a CSP form by configuring sub-pixels for R, G, and B.

The R chip 100R, the G chip 100G, and the B chip 100B may constitute one light emitting device.

A chip array can be formed by selectively transferring and arranging a plurality of RGB chips 100R, 100G, 100B on a carrier substrate in a row and column direction, and expanding the area of the chip array selectively transferred to the carrier substrate The pixel CSP may be formed, and the subpixel CSP array arranged on the carrier substrate by expanding the pad of the subpixel CSP may be selectively transferred to a display panel to be described later.

Next, as shown in FIG. 4, a selective sequential transfer process for transferring the diced chip arrays in the form of RGB chips 100R, 100G, and 100B on each wafer to a carrier substrate and a display panel will be described.

The following drawings are described in terms of row (horizontal) arrangement in a chip array arranged in a matrix on the wafer of FIG. 1.

The chip array formed on each wafer is primarily selectively transferred by the carrier substrate, and the area of the chip array selectively transferred to the carrier substrate is expanded to form a sub-pixel CSP, and the pad of the formed sub-pixel CSP is expanded. In addition, the sub-pixel CSP array, which is selectively first transferred and the pad-extended sub-pixel CSP array is secondarily transferred to the display panel, is selectively sequentially transferred to manufacture a display panel in which one pixel CSP is arrayed.

6 to 8 are diagrams showing a structure of a carrier substrate for selectively transferring the chip array shown in FIG. 1 by a carrier substrate.

6 is a structure of a carrier substrate 200R for primary selective transfer from an R wafer on which an R chip array is formed, and FIG. 7 is a structure of a carrier substrate 200G for primary selective transfer from a G wafer on which a G chip array is formed. 8 is a structure of a carrier substrate 200B for primary selective transfer from a B wafer on which a B chip array is formed.

6 to 8 show structures of respective carrier substrates 200R, 200G, and 200B for selectively transferring in a column order in an R, G, and B chip array formed on a wafer.

For example, in the case of sequentially selectively transferring rows of R wafers, G wafers, and B wafers first, the carrier substrate 200R has 1 row, 4 rows, 7 rows ?? Selective transfer is possible in order, and the carrier substrate (200G) has 2 rows, 5 rows, 8 rows ?? In this order, the carrier substrate 200B has 3 rows, 6 rows, 9 rows ?? In order, the chips formed on each wafer can be selectively transferred.

Second, when the same rows of R wafer, G wafer, and B wafer are selectively transferred, each of the carrier substrates 200R, 200G, 200B is 1 row, 4 row, 7 row ?? Selective transfer is possible in order, followed by 2nd, 5th, 8th row ?? In that order, then row 3, row 6, row 9 ?? In this order, the chips formed on the wafer may be selectively transferred without leaving until all the chips are transferred.

Assuming the first example case, the transfer method will be described below (from 1st to 6th rows of chips (1st RGB chip array, 2nd RGB chip array) as examples, and beyond (3rd, 4th,? ?, nth RGB chip array) is omitted).

6, (A) is a front view, (B) is an XX cross-sectional view of (A), and (C) is a drawing on which the adhesive material is applied in (B), and selectively transferred to the carrier substrate 200R. Opening holes 36 are formed in the remaining column portions except for the portions (row 1, row 4, ??) (35-SP1, 35-SP4, ??).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200R, and when the adhesive material 37 is applied to the surface of the carrier substrate 200R, the adhesive material is not applied to the opening hole 36. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area without the opening hole 36 so that only the corresponding heat can be picked up. The material of the carrier substrate 200R may be metal, ceramic, glass, plastic, polymer, or the like.

Referring to FIG. 7, (A) is a front view, (B) is an XX cross-sectional view of (A), and (C) is a drawing on which an adhesive material is applied in (B), and selectively transferred to the carrier substrate 200G. Opening holes 36 are formed in the remaining column portions except for the portions (2nd row, 5th row, ??) (35-SP2, 35-SP5, ??).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200G, and when the adhesive material 37 is applied to the surface of the carrier substrate 200G, the adhesive material is not applied to the opening hole 36. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area without the opening hole 36 so that only the corresponding heat can be picked up. The material of the carrier substrate 200G may be metal, ceramic, glass, plastic, polymer, or the like.

Referring to FIG. 8, (A) is a front view, (B) is an XX cross-sectional view of (A), and (C) is a drawing on which an adhesive material is applied in (B), and selectively transferred to the carrier substrate 200B. Opening holes 36 are formed in the remaining column portions except for the portions (3 rows, 6 rows, ??) (35-SP3, 35-SP6, ??).

Selective transfer is possible depending on the presence or absence of the opening hole 36 of the carrier substrate 200B, and when the adhesive material 37 is applied to the surface of the carrier substrate 200B, the adhesive material is not applied to the opening hole 36. Therefore, the chip cannot be picked up during transfer, and the adhesive material 37 is applied to the area without the opening hole 36 so that only the corresponding heat can be picked up. The material of the carrier substrate 200B may be metal, ceramic, glass, plastic, polymer, or the like.

Next, a primary transfer process of transferring a chip from the wafer to the carrier substrates 200R, 200G, 200B using the prepared carrier substrates 200R, 200G, and 200B of FIGS. 6 to 8, and expanding the area of the chip A process of forming a sub-pixel CSP, a process of expanding a pad of a sub-pixel CSP array, and a process of secondary transfer of transferring the sub-pixel CSP array to a display panel will be described.

9 to 18 illustrate selective transfer of an R (Red) chip array to a carrier substrate, formation of an R (Red) sub-pixel CSP array through area expansion of the R (Red) chip array, and the R (Red) sub-pixel CSP array. A step of selectively sequentially transferring the pad expansion and the pad expanded R (Red) subpixel CSP array to the display panel will be described. 22 to 24 illustrate selective transfer of a G (Green) chip array to a carrier substrate, formation of a G (Green) sub-pixel CSP array through region expansion of the G (Green) chip array, and a G (Green) sub-pixel CSP array. A step of selectively sequentially transferring the pad extension and the pad-extended green subpixel CSP array to the display panel will be described. In addition, FIGS. 25 to 27 show the selective transfer of the B (Blue) chip array to the carrier substrate, the formation of the B (Blue) sub-pixel CSP array through the area expansion of the B (Blue) chip array, and the B (Blue) sub-pixel CSP. A step of selectively sequentially transferring the pad expansion of the array and the expanded blue subpixel CSP array to the display panel will be described.

9 shows a process in which the R chip array is first transferred from the R wafer to the carrier substrate, where (A) is a front view of the R wafer 10R, and (B) is the R wafer ( 10R) is a front view obtained by primary transfer of the first and fourth columns, and (C) shows the XX cross-sectional view of (B).

Referring to FIG. 9, the R wafer 10R of (A) is in a state that has undergone the processes of FIGS. 3 and 4, and the carrier substrate 200R of FIG. 6 is aligned with the R wafer 10R to contact the carrier substrate. When (200R) is separated, the 1st and 4th row of R chip arrays of the R wafer 10R of (A) are picked up and transferred to become empty, and as shown in (B)/(C), the 1st and 4th row of R chip arrays (100R) -SP1, 100R-SP4) is transferred to the carrier substrate 200R.

The step of transferring the chip array to the carrier substrate (S150) may be referred to as'primary transfer'.

Here, the carrier substrate 200R may also be referred to as a'transfer adhesive member', and an adhesive or adhesive is applied to these materials such as PET, PP, PE, PS resin plates, or these materials have a thin thickness in the form of a tape. While having, an adhesive or adhesive may be applied to one side thereof.

The carrier substrate 200R may have a predetermined ductility, and the carrier substrate 200R having a predetermined ductility may be made of a material that can be easily bent by an external force.

If the carrier substrate 200R is a material that can be easily bent, the transfer efficiency can be further improved compared to the case where the carrier substrate 200R is a material that is not easily bent.

When the carrier substrate 200R is made of a material that is not easily bent, it is difficult to lift the carrier substrate at once after attaching the chips 100R-SP1, 100R-SP2, and 100R-SP3 to the carrier substrate. The reason is that the adhesion between the respective chips 100R-SP1, 100R-SP2, and 100R-SP3 and the carrier substrate 200R is significant.

However, if the carrier substrate 200R is a material that is easily bent, after attaching each chip 100R-SP1, 100R-SP2, 100R-SP3 to the carrier substrate 200R, one side of the carrier substrate 200R When the bay is raised, the number of pixel CSPs attached only to that portion is relatively small, so that the entire carrier substrate 200R can be easily lifted with a small force.

In addition, the carrier substrate 200R may be made of a transparent material. If the carrier substrate 200R is a transparent material, when transferring each chip (100R-SP1, 100R-SP2, 100R-SP3) to the carrier substrate 200R, a vision system ( There is an advantage that can be adjusted or controlled through (not shown).

Meanwhile, the carrier substrate 200R may also be referred to as a first transfer medium in a method of manufacturing a display device according to an embodiment of the present invention. A first adhesive force is formed between the first transfer medium and the pixel CSP array. Specifically, the first adhesive force may be 2,000 gf/25mm to 4,000 gf/25mm. More preferably, the first adhesive force may be 3,000 gf/25mm.

Referring to FIG. 9C, when transferring 1 row and 4 rows of R chip arrays 100R-SP1 and 100R-SP4 to a carrier substrate 200R, 1 row and 4 rows of R chip arrays 100R-SP1 and 100R -The pad 14r side of the SP4 is transferred to the carrier substrate 200R. This is for area expansion and pad expansion, which will be described later through FIGS. 10 to 15.

10 to 15 are views for explaining in detail a process of extending a region and extending a pad of an R chip array transferred to a carrier substrate.

FIG. 10 shows the photoresist layer 18 to cover the R chip arrays 100R-SP1 and 100R-SP4 on the carrier substrate 200R after (C) of FIG. 9 is turned over. Here, the photoresist layer 18 is an epoxy-based material, and may be SU-8.

Referring to FIG. 11, the photoresist layer 18 is patterned through a photo process and a development process. One R chip (100R-SP1 or 100R-SP4) is positioned inside the patterned photoresist layer 18R. The patterned photoresist layer 18R surrounds one R chip (100R-SP1 or 100R-SP4). One R sub-pixel CSP (100R-SP1 or 100R-SP4) may be formed by combining the patterned photoresist layer 18R to one R chip 100R-SP1 or 100R-SP4. One R sub-pixel CSP increases in volume more than one R chip, and as a result, an area of one R sub-pixel CSP (100R-SP1 or 100R-SP4) is expanded. In this way, the R sub-pixel CSP is a combination of the patterned photoresist layer 18R on the R chip, and the surface area is increased more than the surface area of the R chip, thereby securing an area in which the pad can be expanded. Since micro LEDs are in units of several microns, the size of the pad is inevitably small. However, by making each chip into a sub-pixel CSP in this way, an area in which the size of the pad can be increased can be secured.

As such, one sub-pixel CSP (Chip Scale Package) is a term that is distinct from a chip, and is a generic term for a small package close to the size of a chip, and there is no lead frame for protecting the outer shape of the chip and a wire for electrical connection. It may be a package size close to a bare chip that is not.

Referring to FIG. 12, the region-extended R sub-pixel arrays 100R-SP1 and 100R-SP4 are transferred from the carrier substrate 200R to another carrier substrate 210R. This is a process for exposing the pad 14r to the outside for pad expansion. After attaching another carrier substrate 210R on the patterned photoresist layer 18R of the region-extended R sub-pixel arrays 100R-SP1 and 100R-SP4, the carrier substrate 200R is attached to the region-extended R sub-pixel It can be removed from the arrays 100R-SP1 and 100R-SP4. Here, in order to compare the other carrier substrate 210R with the carrier substrate 200R, it may be referred to as a carrier substrate for area expansion or may be referred to as an additional carrier substrate.

Fig. 13 is a view in which Fig. 12 is turned over. Referring to FIG. 13, a patterned shadow mask 500 is formed on the region-extended R sub-pixel arrays 100R-SP1 and 100R-SP4.

Referring to FIG. 14, a pad expansion metal M is deposited to a predetermined thickness on the shadow mask 500 and the region-extended R sub-pixel arrays 100R-SP1 and 100R-SP4.

Referring to FIG. 15, when the deposition of the pad expansion metal M is completed, the shadow mask 500 is removed. By removing the shadow mask 500, an expansion pad 14R made of a pad expansion metal may be formed on the pad 14r of the region-extended R sub-pixel arrays 100R-SP1 and 100R-SP4. The pad 14r and the expansion pad 14R are in contact and electrically connected.

FIG. 16 is a cross-sectional view illustrating a chip having a general size pad 14r before pad expansion and a subpixel CSP having an expansion pad 14R. FIG. 16A is It is a side view showing one chip array, and FIG. 16B is a side view showing one sub-pixel CSP array after area expansion and pad expansion.

When comparing (a) and (b) of FIG. 16, the expansion pads 14R and 14R' may have an enlarged size compared to the general-sized pads 14r and 14r' and thus have an increased cross-sectional area.

In particular, in the case of micro-unit LED chips, the pixel unit is 30㎛ * 30㎛ to 100㎛ * 100㎛, so the width and length of the pads are also very fine, and electrical open occurs during the surface mounting process of these as the substrate of the display panel. As a result, the defective rate is inevitably increased.

On the other hand, by performing the surface mounting process in units of sub-pixel CSP that can be expanded on the display panel, the electrical connection process of micro LEDs in tens of um area is scaled up to the electrical connection process of pixel CSPs in hundreds of um area. Defects such as open can be minimized.

In addition, it is possible to minimize electrical defects by increasing an alignment margin between the sub-pixel CSP pad and the pad of the display panel during the surface mounting process on the display device, and to quickly manufacture a large-area display device.

17 shows a process of secondary transfer of an R sub-pixel CSP array pad-extended from a carrier substrate to a display panel.

Referring to FIG. 17, (A) shows the pads 31-SP1 ??31-SP6 of the display panel 300, and (B) shows the display panel 300 of FIG. 9B. This shows a state in which the R sub-pixel array in which the pads are expanded by aligning the carrier substrate 200R is secondarily transferred onto the display panel 300.

Pads 31-SP1 ??31-SP6 are formed in the first to sixth columns of the display panel 300, and solder pastes 33-SP1 and 33-SP4 are formed in the first and fourth rows, and the corresponding rows Each pad-extended R sub-pixel CSP (100R-SP1, 100R-SP4) is transferred to the position.

However, although it is shown that the solder paste is formed only in the first row and the fourth row on the pads of the display panel 300, the solder paste 33-SP1 to 33-SP6 may be formed in all rows. This is because the carrier substrate 200R has already selectively picked up and transferred the first row and the fourth row.

FIG. 18 is a cross-sectional view illustrating a process of transferring from another carrier substrate to a display panel in FIG. 17 in more detail.

Referring to FIG. 18A, a solder paste 33 is applied on a plurality of pads 31 of the display panel 300.

A TFT array substrate 400 may be disposed under the display panel 300.

Here, the solder paste 33 may be applied only on the first and fourth rows of the pads 31-SP1 and 31-SP4, but may be applied on the remaining pads.

One row of R sub-pixels CSP is selectively transferred to the first and fourth rows of pads (preferably pads arranged at intervals of the previous row + 3 rows), followed by the second and third row pads between rows 1 and 4 One row of the G sub-pixel CSP and one row of the B sub-pixel CSP are sequentially transferred to (the pads arranged at intervals of the previous column + 3 columns, respectively).

The solder paste 33 may be applied on the plurality of pads 31 of the display panel 300 through various methods such as screen printing, dispensing, and jetting.

Next, referring to (B) of FIG. 18, the R sub-pixels CSPs 100R-SP1 and 100R-SP4 attached to the other carrier substrate 210R manufactured in FIG. 15 and having an expansion pad 14R are displayed on the display panel. Solder pastes 33-SP1 and 33 applied on the pad 31 of the display panel 300 by placing the expansion pad 14R of the R sub-pixel CSP (100R-SP1, 100R-SP4) onto the 300 -SP4).

After the expansion pad 14R of some R sub-pixels CSP (100R-SP1, 100R-SP4) and the pad 31 of the display panel 300 are in contact with each other through solder paste (33-SP1, 33-SP4), yes For example, when a predetermined heat is applied using a self-aligning paste (SAP) soldering method, some of the solder particles contained in the solder pastes (33-SP1, 33-SP4) are partially R subpixels. It may be self-assembled between the expansion pads 14R of the CSPs 100R-SP1 and 100R-SP4 and the pads 31-SP1 and 31-SP4 of the display panel 300.

Meanwhile, the thermosetting resin included in the solder paste 33 may be cured by heat.

Next, referring to FIG. 18C, the expansion pads 14R of some R sub-pixels CSPs 100R-SP1 and 100R-SP4 and pads 31-SP1 and 31-SP4 of the display panel 300 When is soldered, the other carrier substrate 210R is separated.

Here, the carrier substrate 210R having different soldering adhesion between the expansion pad 14R of some R sub-pixels CSP (100R-SP1, 100R-SP4) and the pads 31-SP1 and 31-SP4 of the display panel 300 Since the adhesion between the and R sub-pixels CSP (100R-SP1, 100R-SP4) is much greater than that, it is possible to easily separate only the other carrier substrate (210R).

Meanwhile, before the process of transferring the R sub-pixel CSP shown in FIG. 18 from another carrier substrate 210R to the display panel, as shown in FIG. 1, the pads transferred to the other carrier substrate 210R are extended R subs. A probe test process (S170, S171, S173, S175) of the pixel CSP may be added. Hereinafter, a probe test process will be described in detail with reference to FIGS. 1 and 19 to 21.

19 is a front view of a probe card according to an embodiment of the present invention, and FIG. 20 is an R sub-pixel array 100R-SP1 arranged on another carrier substrate (or a pad expansion carrier substrate 210R) shown in FIG. 15 FIG. 21 is a front view showing that, and FIG. 21 is a state of performing inspection (or test) of the R sub-pixel CSP array 100R-SP1 transferred to another carrier substrate 210R using the probe card shown in FIG. 19 It is a side sectional view showing.

19 to 21, a probe card according to an embodiment of the present invention may test electrical and optical characteristics of R sub-pixel CSPs 100R-SP1 transferred to another carrier substrate 210R.

The probe card according to the embodiment of the present invention includes a base substrate 2000 having a plurality of openings 2500, and probe pins 2100a and 2100b disposed in each opening 2500 and electrically connected to the base substrate 2000. Include.

The size (width*length (Wp*Lp)) of the base substrate 2000 may correspond to the size (width*length (Wc*Lc)) of another carrier substrate 210R shown in FIG. 20. For example, the base substrate 2000 and the other carrier substrate 210R illustrated in FIG. 20 may have the same size. However, the present invention is not limited thereto, and the size or shape of the base substrate 2000 may be different from the size or shape of the other carrier substrate 210R according to design needs.

A plurality of openings 2500 of the base substrate 2000 may be formed in the base substrate 2000 along the row and column directions.

The number of the plurality of openings 2500 may correspond to the number of R sub-pixels CSPs 100R-SP1 transferred to the other carrier substrate 210R shown in FIG. 20. For example, the plurality of openings 2500 may correspond one-to-one with the R sub-pixel CSPs 100R-SP1 transferred to the other carrier substrate 210R.

The opening area of one opening 2500 may correspond to one surface of one R sub-pixel CSP 100R-SP1. Here, one surface of one R sub-pixel CSP 100R-SP1 may be a surface in which the first and second pads 14R and 14R' are formed in the R sub-pixel CSP 100R-SP1. In FIG. 21, the opening area of one opening 2500 is slightly smaller than that of one R sub-pixel CSP 100R-SP1, but the present invention is not limited thereto, and may be reversed according to design needs. May be the same.

The plurality of openings 2500 may be used to observe and adjust the contact position between each R sub-pixel CSP 100R-SP1 and the probe card. For example, the pad of the sub-pixel CSP 100R-SP1 is The light emitting surface of the probe card side and the sub-pixel CSP 100R-SP1 may be positioned toward the carrier substrate 210R. When the test signal is applied, the light does not go out toward the opening 2500 of the probe card covered by the pad, but is emitted toward the carrier substrate 210R. An optical characteristic detector (not shown) located below the carrier substrate 210R may detect the emitted light.

The probe pins 2100a and 2100b include a first probe pin 2100a and a second probe pin 2100b. The first probe pin 2100a and the second probe pin 2100b are used to test electrical and optical characteristics of each R sub-pixel CSP 100R-SP1. When the test of the electrical and optical properties is described as an example, as shown in FIG. 21, the base substrate 2000 and the other carrier substrate 210R are in close contact with each other so that the first probe pin 2100a is an R sub-pixel CSP. One pad 14R of the (100R-SP1) is contacted, and the second probe pin 2100b is brought into contact with the other pad 14R' of the R sub-pixel CSP 100R-SP1. Here, the one pad 14R ′ different from the one pad 14R may be an expansion pad.

By the contact, the R sub-pixel CSP 100R-SP1 and the first and second probe pins 2100a and 2100b may be electrically connected. When the electrical connection is completed, the test signal is transmitted to the R sub-pixel CSP (100R-SP1) through the first and second probe pins 2100a and 2100b to determine whether light is emitted from the R sub-pixel CSP (100R-SP1). Test (electrical property test), or even if light is emitted, it is possible to test whether there is a functional error such as whether light of a normal wavelength band is emitted or that light of an appropriate intensity is emitted (optical property test).

As described above, when the probe card according to the embodiment of the present invention shown in FIGS. 19 to 21 is used, the R sub-pixel CSP 100R- which is transferred to another carrier substrate 210R and has expansion pads 14R and 14R'. The electrical and optical properties of SP1) can be tested together.

In addition, the probe card according to the embodiment of the present invention shown in FIGS. 1 and 19 to 21 is a chip formed on each of the wafers 10R, 10G, and 10B shown in FIGS. 2A to 2C. And it is characterized in that it does not test the optical characteristics, but tests the electrical and optical characteristics of the pad-extended sub-pixel CSP on the other carrier substrates 210R, 210G, and 210B. When the chips formed on each wafer 10R, 10G, and 10B are mini or microchips, the pitch between the chips formed on the wafer is very narrow, and the general pads 14r, 14g, and 14r of each chip are also very small. Therefore, in order to test the electrical and optical characteristics of the chips formed on each wafer, the probe card must also be reduced according to the size of the chip. When the size of the probe card is reduced, the size of the probe pin must also be reduced. However, it is not easy to manufacture a probe card with a reduced size of the probe pin, and the reliability of the test result is lowered.

However, as in the embodiment of the present invention, when testing the electrical and optical characteristics of the pad-extended sub-pixel CSP during the transfer process, not on the wafer, the sub-pixel CSP has a larger area than the chip on the wafer and thus has a larger size. Since the surface area of the pad is also widened, it is possible to have sufficient space for measurement with the probe card. Therefore, it is not necessary to miniaturize the probe card according to the size of the chip, the reliability of the test result can be improved, and the test time can be drastically reduced.

A test apparatus using a probe card according to an embodiment of the present invention includes a base substrate 2000 having a plurality of openings 2500, and at least two or more disposed in each of the openings 2500 and electrically connected to the base substrate 2000. A probe card including probe pins 2100a and 2100b; And a carrier substrate 210 to which a plurality of sub-pixels CSPs corresponding to one-to-one corresponding to the plurality of openings 2500 are transferred, wherein each sub-pixel CSP includes an expansion pad 14R in contact with the probe pins 2100a and 2100b, 14R'), and a test signal for testing electrical and optical properties is applied to the sub-pixel CSP through the probe pins 2100a and 2100b.

Here, each of the sub-pixels CSP may include a photoresist layer surrounding the chip and an expansion pad exposed outside the photoresist layer.

Further, the probe pins 2100a and 2100b include first and second probe pins, the expansion pads 14R and 14R′ include first and second expansion pads, and each of the first and second expansion pads It is disposed on the pad of the sub-pixel CSP and has a larger surface area than the pad, and the distance between the first and second probe pins 2100a and 2100b is as large as the distance between the first and second expansion pads 14R and 14R'. Expands.

A method of manufacturing a display device according to an embodiment of the present invention includes between a primary transfer process and a secondary transfer process, and more specifically, between a pad expansion process (S160) and a secondary transfer process (S180) of the subpixel CSP. By adding the probe test process (S170, S171, S173, S175) to the display device, there is an advantage of saving the test time of the display device, improving the yield, and securing high reliability of the test.

Referring to FIG. 1 again, as shown in FIG. 21, after forming expansion pads 14R and 14R' on the sub-pixel CSP 100R-SP1 on another carrier substrate 210R, the base substrate of the probe card ( 2000) is brought close to the sub-pixel CSP 100R-SP1 array so that the probe pins 2100a and 2100b of the probe card contact the pads 14R and 14R' of each sub-pixel CSP 100R-SP1.

When the probe pins 2100a and 2100b contact the pads 14R and 14R' of each sub-pixel CSP 100R-SP1, a test signal is transmitted through the probe pins 2100a and 2100b to each sub-pixel CSP 100R-SP1. It is applied to measure the electrical and optical characteristic tests to determine whether it is normal (S171).

If the test measurement result is OK, the secondary transfer (S180) shown in FIG. 1 is performed. Meanwhile, if the test measurement result is an error (NG), the sub-pixel CSPs are repaired (S173). Here, the test measurement result may reflect an electrical characteristic test result and an optical characteristic test result. Even if it passes the electrical characteristic test result, if it does not pass the optical characteristic test result, it can be judged as an error. The opposite is also true. The method of repairing sub-pixel CSPs is a pickup place method in which an errored sub-pixel CSP among sub-pixel CSPs is picked up and removed from another carrier substrate 210R, and a new sub-pixel CSP is replaced at the place where it was picked up. You can use

When the repair of the sub-pixel CSPs is completed, it is checked whether the replaced sub-pixel CSP is normally operated (S175). As a result of checking, if it is normal (OK), the secondary transfer (S180) shown in FIG. 1 is performed, and if it is an error (NG), the above-described repair process (S173) may be repeated.

Next, FIGS. 22 to 24 show that the G (Green) chip array is selectively transferred to the carrier substrate, and the region of the G (Green) chip selectively transferred to the carrier substrate is expanded to form a G subpixel CSP. These are diagrams for explaining in detail a step of expanding the pad of the sub-pixel CSP and selectively sequentially transferring the G (green) sub-pixel CSP having the extended pad to the display panel.

Fig. 22 shows a process in which the G chip array is first transferred from the G wafer to the carrier substrate, where (A) is a front view of the G wafer 10G, and (B) is a G wafer using the carrier substrate 200G. 10G) is a front view obtained by primary transfer of the first and fourth rows, and (C) shows the XX cross-sectional view of (B).

Referring to FIG. 22, the G wafer 10G of (A) is a state that has undergone the processes of FIGS. 3 and 4, and the carrier substrate 200G of FIG. 7 is aligned with the G wafer 10G to contact the carrier substrate. When (200G) is separated, the 1st and 4th rows of G chip arrays of the G wafer (10G) of (A) are picked up and transferred to become empty, and as shown in (B)/(C), the 2nd and 5th row G chip arrays (100G) -SP1, 100G-SP4) is transferred to the carrier substrate 200G.

The carrier substrate 200G may have the same material and properties as the carrier substrate 200R.

Referring to FIG. 22C, when transferring the first and fourth rows of G chip arrays 100G-SP1 and 100G-SP4 to the carrier substrate 200G, the first and fourth rows of G chip arrays 100G-SP1 and 100G The pad 14g side of -SP4) is transferred to the carrier substrate 200G. This is for area expansion and pad expansion. Since the area expansion and pad expansion are the same as those of FIGS. 10 to 15 described above, a description thereof will be omitted.

23 shows a process of secondary transfer of a G sub-pixel CSP array pad-extended from a carrier substrate to a display panel.

Referring to FIG. 23, (A) shows the pads 31-SP1 ??31-SP6 of the display panel 300, and R subpixel arrays in columns 1 and 4 through the processes of FIGS. 17 to 18 Is in the transferred state, and (B) aligns the carrier substrate 200G of FIG. 14B on the display panel 300 to form a pad-extended G sub-pixel array on the display panel 300. It shows the transferred state.

Pads 31-SP1 ??31-SP6 are formed in rows 1 to 6 of the display panel 300, and solder pastes 33-SP2 and 33-SP5 are formed in rows 2 and 5, and the corresponding rows Each pad-extended G sub-pixel CSP (100G-SP1, 100G-SP4) is transferred to the position.

However, although it is shown that solder pastes are formed only in rows 2 and 5 on the pads of the display panel 300, solder pastes 33-SP3 and 33-SP6 may be formed in rows 3 and 6. This is because the carrier substrate 200G has already selectively picked up and transferred 2nd and 5th rows.

FIG. 24 is a cross-sectional view illustrating a process of transferring from another carrier substrate to a display panel in FIG. 23 in more detail.

Referring to (A) of FIG. 24, a solder paste 33 is applied on a plurality of pads 31 of the display panel 300, and R subpixels already expanded in the previous step in the first and fourth rows. The CSP arrays 100R-SP1 and 100R-SP4 are located in a transferred state.

Here, the solder paste 33 may be applied only on the second and fifth rows of the pads 31-SP2 and 31-SP5, but may be applied on the remaining pads.

Next, referring to FIG. 24B, a G sub-pixel CSP 100G attached to another carrier substrate 210G manufactured in the same manner as in FIGS. 10 to 15 and having an expansion pad 14G. -SP1, 100G-SP4) on the display panel 300, and the expansion pad 14G of the G sub-pixel CSP (100G-SP1, 100G-SP4) on the pad 31 of the display panel 300 Contact the applied solder paste (33-SP2, 33-SP5).

After the expansion pad 14G of the G sub-pixel CSP (100G-SP1, 100G-SP4) and the pad 31 of the display panel 300 are in contact with each other through the solder paste (33-SP2, 33-SP5), for example, For example, when a predetermined heat is applied using the self-aligning paste (SAP) soldering method, the solder particles contained in the solder pastes (33-SP2, 33-SP5) become G sub-pixel CSP ( It may be self-assembled between the expansion pad 14G of the 100G-SP1 and 100G-SP4 and the pads 31-SP2 and 31-SP5 of the display panel 300.

Next, referring to (C) of FIG. 24, the expansion pad 14G of the G sub-pixel CSP (100G-SP1, 100G-SP4) and the pads 31-SP2 and 31-SP5 of the display panel 300 are When soldered, the other carrier substrate 210G is separated.

Here, the carrier substrate 210G having a different soldering adhesion between the expansion pad 14G of the G sub-pixel CSP (100G-SP1, 100G-SP4) and the pads 31-SP2 and 31-SP5 of the display panel 300 Since the adhesion between the G sub-pixel CSP (100G-SP1, 100G-SP4) is much greater than that between, only the other carrier substrate 210G can be easily separated.

Meanwhile, before the process of transferring the G sub-pixel CSP shown in FIG. 24 from the other carrier substrate 210G to the display panel, a probe test process of the extended G sub-pixel CSP transferred to the other carrier substrate 210G is added. Can be. Since the probe card for the probe test process of the G sub-pixel CSP, and the test method and apparatus using the same are the same as those described above in FIGS. 19 to 21, specific details are replaced with the above description.

Next, FIGS. 25 to 28 show the B (Blue) chip array selectively transferred to the carrier substrate, and the B (Blue) chip region selectively transferred to the carrier substrate is expanded to form a B subpixel CSP, These are drawings for explaining in detail a step of expanding the pad of the B sub-pixel CSP and selectively sequentially transferring the blue sub-pixel CSP having the expanded pad to the display panel.

Fig. 25 shows a process in which the B chip array is first transferred from the B wafer to the carrier substrate, where (A) is a front view of the B wafer 10B, and (B) is a B wafer using the carrier substrate 200B. It is a front view of the 1st row and 4th row of 10B) primary transfer, and (C) shows the XX cross-sectional view of (B).

Referring to FIG. 25, the B wafer 10B of (A) is a state that has undergone the processes of FIGS. 3 and 4, and the carrier substrate 200B of FIG. 8 is aligned with the B wafer 10B to contact the carrier substrate. When (200B) is separated, the 1st and 4th row B chip arrays of the B wafer 10B of (A) are picked up and transferred to become empty, and as shown in (B)/(C), the B chip array 100B of rows 3 and 6 -SP1, 100B-SP4) is transferred to the carrier substrate 200B.

The carrier substrate 200B may have the same material and properties as the carrier substrates 200R and 200G.

Referring to FIG. 25C, when transferring the first and fourth rows of B chip arrays 100B-SP1 and 100B-SP4 to the carrier substrate 200B, the first and fourth rows of B chip arrays 100B-SP1 and 100B -The pad 14b side of SP4 is transferred to the carrier substrate 200B. This is for area expansion and pad expansion. Since the area expansion and pad expansion are the same as those of FIGS. 10 to 15 described above, a description thereof will be omitted.

26 shows a process of secondary transfer of the B subpixel CSP array, which is pad-extended from the carrier substrate to the display panel.

Referring to FIG. 26, (A) shows the pads 31-SP1 ??31-SP6 of the display panel 300, and 1 through the processes of FIGS. 17 to 18 and the processes of FIGS. 23 to 24 The R sub-pixel CSP array is transferred to columns and 4 columns, and the G sub-pixel CSP array is transferred to columns 2 and 5, and (B) is the carrier substrate 200B of FIG. 17B on the display panel 300. This shows a state in which the aligned and pad-extended B sub-pixel CSP array is secondarily transferred onto the display panel 300.

Pads 31-SP1 ??31-SP6 are formed in 1st to 6th rows of the display panel 300, and solder pastes 33-SP3 and 33-SP6 are formed in 3rd and 6th rows, and the corresponding row B sub-pixels CSPs 100B-SP1 and 100B-SP4, each of which are pad-extended, are transferred to the positions.

FIG. 27 is a cross-sectional view illustrating a process of transferring from another carrier substrate to a display panel in FIG. 26 in more detail.

Referring to (A) of FIG. 27, a solder paste 33 is applied on a plurality of pads 31 of the display panel 300, and each of the first and fourth rows, and the second and fifth rows is already in the previous step. The pad extended R sub-pixel CSP arrays 100R-SP1 and 100R-SP4 and the pad extended G sub-pixel CSP array 100G-SP1 and 100G-SP4 are transferred.

Next, referring to FIG. 27(B), the B sub-pixel CSP 100B attached to another carrier substrate 210B manufactured by the same method as the method illustrated in FIGS. 10 to 15 and having an expansion pad 14B. -SP1, 100B-SP4) are placed on the display panel 300, and the expansion pad 14B of the B sub-pixel CSP (100B-SP1, 100B-SP4) is placed on the pad 31 of the display panel 300. Contact with the applied solder paste (33-SP3, 33-SP6).

After the expansion pad 14B of the B sub-pixel CSP (100B-SP1, 100B-SP4) and the pad 31 of the display panel 300 are in contact with each other through the solder paste (33-SP3, 33-SP6), for example, For example, when a predetermined heat is applied using a self-aligning paste (SAP) soldering method, solder particles contained in the solder pastes (33-SP3, 33-SP6) become B sub-pixel CSP ( It may be self-assembled between the expansion pads 14B of the 100B-SP1 and 100B-SP4 and the pads 31-SP3 and 31-SP6 of the display panel 300.

Next, referring to FIG. 27C, the expansion pad 14B of the B sub-pixel CSP 100B-SP1 and 100B-SP4 and the pads 31-SP3 and 31-SP6 of the display panel 300 are When soldered, the other carrier substrate 210B is separated.

Here, the carrier substrate 210B having different soldering adhesive strength between the expansion pad 14B of the B sub-pixel CSP (100B-SP1, 100B-SP4) and the pads 31-SP3 and 31-SP6 of the display panel 300 Since the adhesion between the B sub-pixels CSP (100B-SP1, 100B-SP4) is much larger than that between, only the other carrier substrate 210B can be easily separated.

Meanwhile, before the process of transferring the B sub-pixel CSP shown in FIG. 27 from the other carrier substrate 210B to the display panel, a probe test process of the extended B sub-pixel CSP transferred to the other carrier substrate 210B is added. Can be. Since the probe card for the probe test process of the B sub-pixel CSP, and the test method and apparatus using the same are the same as those described above in FIGS. 19 to 21, specific details are replaced with the above description.

If the processes of FIGS. 9 to 18, 22 to 24, and 25 to 27 are sequentially applied, a display panel in which one completed RGB pixel CSP array is arranged can be manufactured, and FIGS. 9 and 22 25, each of the R, G, and B chip arrays formed on each of the R wafers 10R, G wafers 10G and B wafers 10B can be used sequentially and selectively from the first row to the last row. do.

Meanwhile, when a display or a device is configured by moving the pad area of the display panel, it is possible to solve the electrical connection problems (open and short defects) occurring in the conventional surface mounting process of a chip unit.

Specifically, by simultaneously introducing a sub-pixel CSP having expansion pads (14R, 14G, 14B) and a region-shifted pad (target substrate), the electrical connection process of the micro LED in the tens µm area is electrically connected to the pixel CSP in the hundreds µm area. It can be scaled up by the process.

Through this scale-up, it is possible to quickly manufacture a large-area display device by preventing an open/short defect between electrodes in a transfer process constituting a display device and increasing alignment margin.

Hereinafter, a concept of moving a pad on a display panel corresponding to an expansion pad of an extended subpixel CSP will be described in detail with reference to FIGS. 28 and 29.

28 are views comparing before and after movement of a pad of a display panel.

FIG. 28 shows a pad array of a display panel, which may have an arrangement corresponding to a plurality of pads of one chip 100R, 100G, and 100B shown in FIG. 4.

(A1), (B1), and (C1) of FIG. 28 are schematic diagrams of arrangement of pads on a conventional display panel, and (A2), (B2), and (C2) are arrangements of pads on a display panel according to an embodiment of the present invention. Yes.

In the case of the micro LED, since the size is very small, the spacing d1 between the pads of the display panel corresponding thereto is also very narrow. In the embodiment of the present invention, by increasing the spacing d2 between pads of the display panel, it is possible to prevent a short circuit due to solder paste between the pads in advance.

The relationship between the pads d1 <d2 is established, and d2 can be implemented by moving regions left and right from respective positions of the pads 140 and 140'.

Prerequisites for increasing the spacing of the pads 140 and 140' of the display panel are as follows.

An embodiment of the present invention proposes a first transfer and/or a second transfer as a method for simultaneously transferring a plurality of chips 100 shown in FIG. 4 to the display panel 300 at a high speed.

Here, for the second transfer, a transfer method using a difference in adhesion between the carrier substrate 200 and the solder paste 170 is adopted.

Therefore, in order to implement the second transfer, the solder paste 170 must be applied on the pad 140 of the display panel 300, and in this case, before the solder paste 170 is applied, the white ink ( White ink) is applied first.

Referring to (A1), (B1), and (C1) of Fig. 28, if the distance between the pads 14 and 14' of the display panel is very narrow (less than 100㎛) as in the related art, the pads 14 and 14' White ink (15) cannot be filled in between, and a step is formed between the pads 14 and 14 ′ not filled with white ink 15, and the solder paste 17 is trapped, resulting in residual solder paste. This may cause a short circuit.

Accordingly, as shown in (A2), (B2), and (C2) of FIG. 28, the embodiment of the present invention uses the pads 140 and 140 ′ of the display panel 300 to solve the above problem. The white ink dam can be formed by the white ink 150 by increasing the distance d2 between the pads 140 and 140' by moving the area left and right.

That is, the gap between the pads 140 and 140 ′ is widened, so that white ink may be filled between the pads.

The formation of the white ink dam may eliminate a step difference between the pads 140 and 140 ′, and a cause of a short circuit between electrodes may be eliminated because residual solder paste is not generated.

Next, as described above, if the electrode spacing is widened according to the precondition for increasing the spacing of the pads 140 and 140' of the display panel, the possible conditions for increasing the electrode spacing are as follows.

The possible condition for increasing the spacing of the pads 140 and 140 ′ of the display panel 300 is as described above with reference to FIGS. 10 to 15, to form a sub-pixel CSP by expanding the area of each chip 100 And, it is possible by forming the expansion pads 14R, 14G, and 14B in the extended area of the sub-pixel CSP.

29 is a diagram for explaining in detail a step of transferring a pixel CSP array having an expansion pad transferred to another carrier substrate to a display panel.

Referring to FIG. 29A, a solder paste 170 is applied on a plurality of pads 140 of the display panel 300.

The solder paste 170 may be applied on the plurality of pads 140 of the display panel 300 through various methods such as screen printing, dispensing, and jetting.

Next, referring to (B) of FIG. 29, the other carrier substrate 210 and the wafer layer 10 attached to the carrier substrate 210 are transferred onto the display panel 300, and each sub-pixel CSP is expanded. The pads 14R and 14R' are brought into contact with the solder pastes 170 and 170' applied on the pads 140 and 140' of the display panel 300.

After the expansion pads 14R and 14R' of each pixel CSP and the pads 140 and 140' of the display panel 300 are in contact with each other through the solder pastes 170 and 170', for example, a self-aligning paste (Self When a predetermined heat is applied using the Align Paste (SAP) soldering method, the solder particles contained in the solder pastes 170 and 170 ′ become the expansion pads 14R and 14R ′ of the pixel CSP and the display panel ( It may be self-assembled between the pads 140 and 140' of 300).

Meanwhile, the thermosetting resin included in the solder pastes 170 and 170 ′ may be cured by heat.

Next, referring to FIG. 29C, when the expansion pads 14R and 14R' of the sub-pixel CSP and the pads 140 and 140' of the display panel 300 are soldered, another carrier substrate 210 is It is removed from the wafer 10.

Here, since the soldering adhesive force between the expansion pads 14R and 14R' of the sub-pixel CSP and the pads 140 and 140' of the display panel 300 is much greater than that between the other carrier substrate 210 and the sub-pixel CSP , Only the other carrier substrate 210 can be easily separated.

Referring to FIG. 29, it is possible to widely adjust the spacing between the pads 140 and 140 ′ of the display panel 300 by the first and second expansion pads 14R and 14R ′ of the sub-pixel CSP. Area movement of (140, 140') is possible.

That is, it is possible to improve the contact margin between the electrodes between the pixel CSP and the display panel 300 during the transfer process by the expansion pads 14R and 14R' that are more extended than the conventional pads, and the pads of the display panel 300 ( 140, 140'), it is possible to move the same area as the spread of both sides, and thus it is possible to block the occurrence rate of a short between electrodes.

In particular, such contact margin and short-circuit prevention can improve the speed and accuracy of the transfer process when applied to a display device to which a micro-unit LED is applied.

Again, referring to FIG. 1, although not shown in FIG. 1, a rework step may be further included. In the rework step, a pixel CSP determined to be malfunctioning or defective among the pixel CSP array formed on the display panel is removed, and a new pixel CSP is placed in the position of the removed pixel CSP.

A new pixel CSP that is normally operating may be located using a pick and place device (not shown).

By further proceeding with the rework step, since the malfunction or defective pixel CSP is removed, and a new pixel CSP is filled in the position where the defective pixel CSP was to be located in the display panel, the display panel is compared with the manufacturing method of the display device shown in FIG. 1. There is an advantage that can significantly reduce the defect of the.

30 and 31 are exemplary views of a process in which each RGB chip formed on each wafer is selectively transferred to a display panel in a column unit according to an embodiment of the present invention.

30 and 31 are explanatory diagrams for explaining in what order the transfer is performed for each RGB chip array on a 1:1 corresponding wafer and a display panel, and in parallel with this order, the order in FIGS. 18, 24 and 27 A description of how to transfer each chip array is shown.

FIG. 30 shows an array of RGB chips formed on each wafer (preferably, a process of transferring to the carrier substrates 200R, 200G, 200B through a primary transfer process, a region expansion process, and a pad expansion process are included. ), FIG. 31 shows the display panel 300.

For convenience of explanation, FIGS. 30 and 31 illustrate three display panels (Panel-1, Panel-2, Panel-3) and three wafers (R-Sub Pixel, G-Sub Pixel, and B-Sub Pixel). It is described as

30 and 31 show examples of selectively transferring an RGB chip array in a column (vertical) arrangement, and the same applies to a row (horizontal) arrangement.

Fig. 30(A) shows a state in which all chips before transfer are arrayed, (B) shows a state in which one row of RGB chip arrays is transferred, and (C) shows a state in which two rows of RGB chip arrays are transferred.

Figure 30 (A) is a state in which one row of RGB chip arrays is transferred to the display panel, (B) is a state in which two rows of RGB chip arrays are transferred to the display panel, and (C) is a three-row RGB chip array for display. It shows the state transferred to the panel.

First, the R chip array (row 1, 4, 7 ?) formed on the wafer of FIG. 30 is transferred onto the first display panel (Panel-1) (row 1, 4, 7 ?) , The G chip array (row 1, row 4, row 7 ??) formed on the wafer is transferred onto the second display panel (Panel-2) (row 2, row 5, and row 8 ??), and The formed B-chip array (row 1, row 4, row 7 ??) is transferred onto the third display panel (Panel-3) (row 3, row 6, row 9 ??), and the transfer state up to this point is displayed on the display panel. 31(A) on the top, and FIG. 30(B) on the wafer.

Next, the G chip array (2nd, 5th, 8th row ??) formed on the wafer of FIG. 30 is transferred onto the first display panel (Panel-1) (2nd row, 5th row, 8th row ??). ), the B chip array formed on the wafer (2 rows, 5 rows, 8 rows ??) is transferred onto the second display panel (Panel-2) (2 rows, 5 rows, 8 rows ??), and The R-chip array (3rd, 6th, 9th row ??) formed in is transferred onto the third display panel (Panel-3) (1st row, 4th row, 7th row ??), and the transfer status up to this point is displayed. 31(B) on the panel, and FIG. 30(C) on the wafer.

Finally, the B-chip array (3 rows, 6 rows, 9 rows ??) formed on the wafer of FIG. 30 is transferred onto the first display panel (Panel-1) (3 rows, 6 rows, 9 rows ??). ), the R chip array (3 rows, 6 rows, 9 rows ??) formed on the wafer is transferred onto the second display panel (Panel-2) (1 row, 4 rows, 7 rows ??), and The G-chip array (3rd, 6th, 9th row ??) formed in is transferred onto the third display panel (Panel-3) (2nd row, 5th row, 8th row ??), and the transfer status up to this point is displayed. 31C is shown on the panel, and all sub-pixels are transferred on the wafer.

In this way, the RGB chip array can be selectively transferred in units of columns or rows, and when the RGB chip arrays are selectively and sequentially transferred in RGB order, LED chips are displayed in units of RGB pixels on the display panel as shown in FIG. 31C. All of these can be transferred.

Features, structures, effects, and the like described in the embodiments above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in each embodiment can be implemented by combining or modifying other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Accordingly, contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the embodiments have been described above, these are only examples and do not limit the present invention, and those of ordinary skill in the field to which the present invention pertains will not depart from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications not illustrated are possible. For example, each constituent element specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

10R, 10G, 10B: wafer
100R, 100G, 100B: chip
200R, 200G, 200B: carrier substrate
210R, 210G, 210B: other carrier substrates
14R, 14G, 14B: Expansion pad
300: display panel
400: TFT array substrate
2000: base substrate
2500: opening
2100a, 2100b: probe pin

Claims (12)

delete delete delete delete delete delete The sub-pixel CSP composed of the chip on which the photoresist layer is formed by forming a photoresist layer covering a plurality of chips transferred to a carrier substrate, and patterning the photoresist layer for each chip to form a plurality of sub-pixels CSP. An area expansion step in which the volume of the chip is increased than the volume of the chip before the photoresist layer is formed so that the area of each chip is expanded;
A pad expansion step of transferring the plurality of sub-pixels CSP to a carrier substrate for pad expansion to form expansion pads having a larger surface area than the pads on the pads of each of the sub-pixels CSP; And
The plurality of sub-pixels by contacting the probe pins of the probe card including the probe pins disposed in the openings and the base substrate having a plurality of openings corresponding to the sub-pixel CSPs one-to-one with the expansion pad of the sub-pixel CSP Including; test measurement and evaluation steps to test the electrical and optical properties of the CSP,
The test measurement and evaluation step,
A determination step of determining whether the electrical and optical characteristic test measurement result is normal or error; And
If the result of the determination step is an error, a replacement step of replacing the sub-pixel CSP determined to be an error among the plurality of sub-pixel CSP; and
The pad expansion step,
Forming a shadow mask on the plurality of sub-pixels CSP that are region-extended;
Depositing a pad extension metal on the shadow mask and the plurality of sub-pixels CSP; And
When the deposition of the pad expansion metal is completed, removing the shadow mask. A test method using a probe card.
The method of claim 7, wherein the test measurement and evaluation step,
A test method using a probe card further comprising; determining whether the replaced sub-pixel CSP operates normally or not.
A method of manufacturing a micro LED-based display device,
The sub-pixel CSP composed of the chip on which the photoresist layer is formed by forming a photoresist layer covering a plurality of chips transferred to a carrier substrate, and patterning the photoresist layer for each chip to form a plurality of sub-pixels CSP. An area expansion step in which the volume of the chip is increased than the volume of the chip before the photoresist layer is formed so that the area of each chip is expanded;
A pad expansion step of transferring the plurality of sub-pixels CSP to a pad expansion carrier substrate to form expansion pads having a larger surface area than the pads on the pads of each of the sub-pixels CSP;
The plurality of sub-pixels by contacting the probe pins of the probe card including the probe pins disposed in the openings and the base substrate having a plurality of openings corresponding to the sub-pixel CSPs one-to-one with the expansion pad of the sub-pixel CSP Testing the electrical and optical properties of the CSP, test measurement and evaluation steps; And
A transfer step of transferring the plurality of sub-pixels CSP transferred to the pad expansion carrier substrate to the display panel from the pad expansion carrier substrate based on the result of the test measurement step; and
The test measurement and evaluation step further includes a replacement step of replacing the sub-pixel CSP based on a test result,
The pad expansion step,
Forming a shadow mask on the plurality of sub-pixels CSP that are region-extended;
Depositing a pad extension metal on the shadow mask and the plurality of sub-pixels CSP; And
And removing the shadow mask when the deposition of the pad expansion metal is completed.
The method of claim 9,
The replacement step, if a result of the test measurement step is an error, replacing the sub-pixel CSP determined as an error among the sub-pixel CSP with a new sub-pixel CSP.
The method of claim 10,
The method of manufacturing a display device, further comprising a normal check step of checking whether the new sub-pixel CSP replaced in the replacement step is normally operated. delete

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