KR102091302B1 - 스큐가 있는 다중 레인 통신 링크에서의 타임스탬프 보정 - Google Patents
스큐가 있는 다중 레인 통신 링크에서의 타임스탬프 보정 Download PDFInfo
- Publication number
- KR102091302B1 KR102091302B1 KR1020157028983A KR20157028983A KR102091302B1 KR 102091302 B1 KR102091302 B1 KR 102091302B1 KR 1020157028983 A KR1020157028983 A KR 1020157028983A KR 20157028983 A KR20157028983 A KR 20157028983A KR 102091302 B1 KR102091302 B1 KR 102091302B1
- Authority
- KR
- South Korea
- Prior art keywords
- timestamp
- lane
- data packet
- lanes
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004891 communication Methods 0.000 title claims abstract description 44
- 238000012937 correction Methods 0.000 title claims description 22
- 238000000034 method Methods 0.000 claims abstract description 41
- 230000006870 function Effects 0.000 description 23
- 238000010586 diagram Methods 0.000 description 12
- 238000001514 detection method Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0697—Synchronisation in a packet node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/28—Timers or timing mechanisms used in protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
- H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/28—Flow control; Congestion control in relation to timing considerations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/34—Flow control; Congestion control ensuring sequence integrity, e.g. using sequence numbers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/41—Flow control; Congestion control by acting on aggregated flows or links
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/14—Multichannel or multilink protocols
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/846,683 US9167058B2 (en) | 2013-03-18 | 2013-03-18 | Timestamp correction in a multi-lane communication link with skew |
| US13/846,683 | 2013-03-18 | ||
| PCT/US2014/030774 WO2014153298A2 (en) | 2013-03-18 | 2014-03-17 | Timestamp correction in a multi-lane communication link with skew |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20150133220A KR20150133220A (ko) | 2015-11-27 |
| KR102091302B1 true KR102091302B1 (ko) | 2020-03-19 |
Family
ID=50694016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020157028983A Active KR102091302B1 (ko) | 2013-03-18 | 2014-03-17 | 스큐가 있는 다중 레인 통신 링크에서의 타임스탬프 보정 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9167058B2 (enExample) |
| EP (1) | EP2976866B1 (enExample) |
| JP (1) | JP6149150B2 (enExample) |
| KR (1) | KR102091302B1 (enExample) |
| CN (1) | CN105379220B (enExample) |
| WO (1) | WO2014153298A2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12204365B2 (en) | 2021-06-14 | 2025-01-21 | Samsung Display Co., Ltd. | Data receiver, display device including the same, and method of receiving data |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9619478B1 (en) * | 2013-12-18 | 2017-04-11 | EMC IP Holding Company LLC | Method and system for compressing logs |
| CN106126466B (zh) * | 2016-06-27 | 2019-10-11 | 哈尔滨明快机电科技有限公司 | 一种并行数据变串行数据的传输方法 |
| CN108880723B (zh) * | 2017-05-16 | 2020-12-11 | 深圳市中兴软件有限责任公司 | 一种时钟同步的方法和装置 |
| CN114944910B (zh) | 2017-10-30 | 2025-02-28 | 华为技术有限公司 | 时钟同步的方法和装置 |
| US11153191B2 (en) | 2018-01-19 | 2021-10-19 | Intel Corporation | Technologies for timestamping with error correction |
| US10686581B2 (en) * | 2018-02-20 | 2020-06-16 | Keysight Technologies, Inc. | Methods, systems, and computer readable media for transmit timestamp autocalibration |
| US10291247B1 (en) | 2018-03-07 | 2019-05-14 | Xilinx, Inc. | Chopping switch time-skew calibration in time-interleaved analog-to-digital converters |
| CN111355549B (zh) * | 2018-12-21 | 2023-05-02 | 深圳市中兴微电子技术有限公司 | 一种数据保护方法及装置 |
| US10956124B2 (en) * | 2019-03-18 | 2021-03-23 | Viavi Solutions Inc. | Slip detection on multi-lane serial datalinks |
| US11265096B2 (en) | 2019-05-13 | 2022-03-01 | Intel Corporation | High accuracy time stamping for multi-lane ports |
| JP7638537B2 (ja) * | 2019-08-08 | 2025-03-04 | デジェロ ラブス インコーポレイテッド | データパケット通信を管理するためのシステムおよび方法 |
| US11140097B2 (en) * | 2019-10-09 | 2021-10-05 | Arista Networks, Inc. | Cross point switch of network device for reordering lanes of network interfaces |
| US11637645B1 (en) | 2020-09-18 | 2023-04-25 | Xilinx, Inc. | Method for time stamping with increased accuracy |
| US12160495B2 (en) | 2020-12-26 | 2024-12-03 | Intel Corporation | Timestamp alignment for multiple nodes |
| US12309250B1 (en) * | 2021-10-26 | 2025-05-20 | Marvell Israel (M.I.S.L) Ltd. | Apparatus and method for preventing latency variation in timestamps of timing protocol packet transmitted through multi-lane ports |
| US12107945B2 (en) * | 2023-01-13 | 2024-10-01 | Raytheon Company | Electrical signal delay calibration system |
| US12381806B2 (en) * | 2023-09-05 | 2025-08-05 | Keysight Technologies, Inc. | Methods, systems, and computer readable media for testing ingress timestamping using lane skewing |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010016791A (ja) | 2008-06-03 | 2010-01-21 | Nippon Telegr & Teleph Corp <Ntt> | パラレル光伝送装置及び方法 |
| JP2010130574A (ja) | 2008-11-28 | 2010-06-10 | Nippon Telegr & Teleph Corp <Ntt> | パラレル伝送方法及びパラレル伝送装置 |
| US20120030438A1 (en) | 2010-07-29 | 2012-02-02 | Sarance Technologies Inc. | Method and Apparatus for Performing Skew Removal in the Receiver of a Multi-Lane Communication Link |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040213155A1 (en) * | 2001-03-29 | 2004-10-28 | Mitel Semiconductor V.N. Inc. | Multi-processor data traffic shaping and forwarding |
| US7668243B2 (en) | 2004-05-18 | 2010-02-23 | Texas Instruments Incorporated | Audio and video clock synchronization in a wireless network |
| US8194662B2 (en) * | 2006-06-08 | 2012-06-05 | Ilnickl Slawomir K | Inspection of data |
| US8135105B2 (en) * | 2008-06-17 | 2012-03-13 | Integraded Device Technologies, Inc. | Circuit for correcting an output clock frequency in a receiving device |
| CN101888292B (zh) * | 2009-05-13 | 2014-07-16 | 中兴通讯股份有限公司 | 基于包交换的时钟同步方法及装置 |
| US9065736B2 (en) * | 2009-06-08 | 2015-06-23 | Broadcom Corporation | Method and system for compensated time stamping for time-sensitive network communications |
| JP5544896B2 (ja) * | 2010-01-22 | 2014-07-09 | 富士通株式会社 | 受信回路、情報処理装置、およびバッファ制御方法 |
| JP5525942B2 (ja) * | 2010-07-06 | 2014-06-18 | アンリツ株式会社 | 先頭レーン検出回路及び方法並びにデスキュー回路及び方法 |
| US9356721B2 (en) * | 2012-06-26 | 2016-05-31 | Marvell World Trade Ltd. | Methods and apparatus for precision time stamping |
| WO2014052972A1 (en) * | 2012-09-28 | 2014-04-03 | Vitesse Semiconductor Corporation | High accuracy 1588 timestamping over high speed multi lane distribution physical code sublayers |
-
2013
- 2013-03-18 US US13/846,683 patent/US9167058B2/en active Active
-
2014
- 2014-03-17 JP JP2016504323A patent/JP6149150B2/ja active Active
- 2014-03-17 KR KR1020157028983A patent/KR102091302B1/ko active Active
- 2014-03-17 WO PCT/US2014/030774 patent/WO2014153298A2/en not_active Ceased
- 2014-03-17 CN CN201480016642.9A patent/CN105379220B/zh active Active
- 2014-03-17 EP EP14723591.5A patent/EP2976866B1/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010016791A (ja) | 2008-06-03 | 2010-01-21 | Nippon Telegr & Teleph Corp <Ntt> | パラレル光伝送装置及び方法 |
| JP2010130574A (ja) | 2008-11-28 | 2010-06-10 | Nippon Telegr & Teleph Corp <Ntt> | パラレル伝送方法及びパラレル伝送装置 |
| US20120030438A1 (en) | 2010-07-29 | 2012-02-02 | Sarance Technologies Inc. | Method and Apparatus for Performing Skew Removal in the Receiver of a Multi-Lane Communication Link |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12204365B2 (en) | 2021-06-14 | 2025-01-21 | Samsung Display Co., Ltd. | Data receiver, display device including the same, and method of receiving data |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2976866A2 (en) | 2016-01-27 |
| KR20150133220A (ko) | 2015-11-27 |
| CN105379220B (zh) | 2017-12-01 |
| US20140269769A1 (en) | 2014-09-18 |
| US9167058B2 (en) | 2015-10-20 |
| EP2976866B1 (en) | 2017-05-03 |
| JP2016517680A (ja) | 2016-06-16 |
| CN105379220A (zh) | 2016-03-02 |
| WO2014153298A3 (en) | 2014-12-04 |
| JP6149150B2 (ja) | 2017-06-14 |
| WO2014153298A2 (en) | 2014-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102091302B1 (ko) | 스큐가 있는 다중 레인 통신 링크에서의 타임스탬프 보정 | |
| EP3739775B1 (en) | High accuracy time stamping for multi-lane ports | |
| US9602271B2 (en) | Sub-nanosecond distributed clock synchronization using alignment marker in ethernet IEEE 1588 protocol | |
| TWI723006B (zh) | 使用經校準、單一時脈來源同步串列器-解串列器協定之高速資料傳輸 | |
| US20140269778A1 (en) | Methods to achieve accurate time stamp in ieee 1588 for system with fec encoder | |
| US11080158B2 (en) | Microcontroller and method for modifying a transmission signal | |
| US20170099101A1 (en) | Methods, systems, and computer readable media for providing traffic generation or forwarding device that compensates for skew between electrical lanes in a manner that allows coherent detection of transmitted data | |
| US7546494B2 (en) | Skew-correcting apparatus using dual loopback | |
| US20120317380A1 (en) | Device and method for a half-rate clock elasticity fifo | |
| US9111042B1 (en) | 1588 deterministic latency with gearbox | |
| US8295161B2 (en) | Network apparatus that determines whether data is written into buffer based on detection of a memory error | |
| US8995596B1 (en) | Techniques for calibrating a clock signal | |
| US20190306062A1 (en) | Methods and apparatus for providing deterministic latency for communications interfaces | |
| US8711018B2 (en) | Providing a feedback loop in a low latency serial interconnect architecture | |
| CN101257418B (zh) | 误码产生的方法和装置以及实现误码插入的系统 | |
| US10277432B2 (en) | Data processing method and device | |
| CN119182695A (zh) | 延迟检测方法和装置 | |
| US20250300753A1 (en) | Timestamping of multilane protocols | |
| US7180935B2 (en) | System and method for compensating for delay time fluctuations | |
| US9166775B2 (en) | Cross-channel data communication with data phase-locked loop | |
| CA2712865A1 (en) | Channel skew identification and notification | |
| JP2012244455A (ja) | 信号伝送装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20151013 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20190312 Comment text: Request for Examination of Application |
|
| PA0302 | Request for accelerated examination |
Patent event date: 20190426 Patent event code: PA03022R01D Comment text: Request for Accelerated Examination |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20190808 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20191226 |
|
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20200313 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20200313 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20240313 Start annual number: 5 End annual number: 5 |