JP6149150B2 - スキューのあるマルチレーン通信リンクにおけるタイムスタンプ補正 - Google Patents
スキューのあるマルチレーン通信リンクにおけるタイムスタンプ補正 Download PDFInfo
- Publication number
- JP6149150B2 JP6149150B2 JP2016504323A JP2016504323A JP6149150B2 JP 6149150 B2 JP6149150 B2 JP 6149150B2 JP 2016504323 A JP2016504323 A JP 2016504323A JP 2016504323 A JP2016504323 A JP 2016504323A JP 6149150 B2 JP6149150 B2 JP 6149150B2
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- JP
- Japan
- Prior art keywords
- fill level
- lane
- lanes
- data packet
- time stamp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0697—Synchronisation in a packet node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/28—Timers or timing mechanisms used in protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
- H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/28—Flow control; Congestion control in relation to timing considerations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/34—Flow control; Congestion control ensuring sequence integrity, e.g. using sequence numbers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/41—Flow control; Congestion control by acting on aggregated flows or links
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/846,683 US9167058B2 (en) | 2013-03-18 | 2013-03-18 | Timestamp correction in a multi-lane communication link with skew |
| US13/846,683 | 2013-03-18 | ||
| PCT/US2014/030774 WO2014153298A2 (en) | 2013-03-18 | 2014-03-17 | Timestamp correction in a multi-lane communication link with skew |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016517680A JP2016517680A (ja) | 2016-06-16 |
| JP2016517680A5 JP2016517680A5 (enExample) | 2017-06-08 |
| JP6149150B2 true JP6149150B2 (ja) | 2017-06-14 |
Family
ID=50694016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016504323A Active JP6149150B2 (ja) | 2013-03-18 | 2014-03-17 | スキューのあるマルチレーン通信リンクにおけるタイムスタンプ補正 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9167058B2 (enExample) |
| EP (1) | EP2976866B1 (enExample) |
| JP (1) | JP6149150B2 (enExample) |
| KR (1) | KR102091302B1 (enExample) |
| CN (1) | CN105379220B (enExample) |
| WO (1) | WO2014153298A2 (enExample) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9619478B1 (en) * | 2013-12-18 | 2017-04-11 | EMC IP Holding Company LLC | Method and system for compressing logs |
| CN106126466B (zh) * | 2016-06-27 | 2019-10-11 | 哈尔滨明快机电科技有限公司 | 一种并行数据变串行数据的传输方法 |
| CN108880723B (zh) * | 2017-05-16 | 2020-12-11 | 深圳市中兴软件有限责任公司 | 一种时钟同步的方法和装置 |
| CN114944910B (zh) | 2017-10-30 | 2025-02-28 | 华为技术有限公司 | 时钟同步的方法和装置 |
| US11153191B2 (en) | 2018-01-19 | 2021-10-19 | Intel Corporation | Technologies for timestamping with error correction |
| US10686581B2 (en) * | 2018-02-20 | 2020-06-16 | Keysight Technologies, Inc. | Methods, systems, and computer readable media for transmit timestamp autocalibration |
| US10291247B1 (en) | 2018-03-07 | 2019-05-14 | Xilinx, Inc. | Chopping switch time-skew calibration in time-interleaved analog-to-digital converters |
| CN111355549B (zh) * | 2018-12-21 | 2023-05-02 | 深圳市中兴微电子技术有限公司 | 一种数据保护方法及装置 |
| US10956124B2 (en) * | 2019-03-18 | 2021-03-23 | Viavi Solutions Inc. | Slip detection on multi-lane serial datalinks |
| US11265096B2 (en) | 2019-05-13 | 2022-03-01 | Intel Corporation | High accuracy time stamping for multi-lane ports |
| JP7638537B2 (ja) * | 2019-08-08 | 2025-03-04 | デジェロ ラブス インコーポレイテッド | データパケット通信を管理するためのシステムおよび方法 |
| US11140097B2 (en) * | 2019-10-09 | 2021-10-05 | Arista Networks, Inc. | Cross point switch of network device for reordering lanes of network interfaces |
| US11637645B1 (en) | 2020-09-18 | 2023-04-25 | Xilinx, Inc. | Method for time stamping with increased accuracy |
| US12160495B2 (en) | 2020-12-26 | 2024-12-03 | Intel Corporation | Timestamp alignment for multiple nodes |
| KR102833387B1 (ko) | 2021-06-14 | 2025-07-14 | 삼성디스플레이 주식회사 | 데이터 수신기, 이를 포함하는 표시 장치, 및 데이터 수신 방법 |
| US12309250B1 (en) * | 2021-10-26 | 2025-05-20 | Marvell Israel (M.I.S.L) Ltd. | Apparatus and method for preventing latency variation in timestamps of timing protocol packet transmitted through multi-lane ports |
| US12107945B2 (en) * | 2023-01-13 | 2024-10-01 | Raytheon Company | Electrical signal delay calibration system |
| US12381806B2 (en) * | 2023-09-05 | 2025-08-05 | Keysight Technologies, Inc. | Methods, systems, and computer readable media for testing ingress timestamping using lane skewing |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040213155A1 (en) * | 2001-03-29 | 2004-10-28 | Mitel Semiconductor V.N. Inc. | Multi-processor data traffic shaping and forwarding |
| US7668243B2 (en) | 2004-05-18 | 2010-02-23 | Texas Instruments Incorporated | Audio and video clock synchronization in a wireless network |
| US8194662B2 (en) * | 2006-06-08 | 2012-06-05 | Ilnickl Slawomir K | Inspection of data |
| JP5230367B2 (ja) | 2008-06-03 | 2013-07-10 | 日本電信電話株式会社 | パラレル光伝送装置及び方法 |
| US8135105B2 (en) * | 2008-06-17 | 2012-03-13 | Integraded Device Technologies, Inc. | Circuit for correcting an output clock frequency in a receiving device |
| JP5203153B2 (ja) | 2008-11-28 | 2013-06-05 | 日本電信電話株式会社 | パラレル伝送方法及びパラレル伝送装置 |
| CN101888292B (zh) * | 2009-05-13 | 2014-07-16 | 中兴通讯股份有限公司 | 基于包交换的时钟同步方法及装置 |
| US9065736B2 (en) * | 2009-06-08 | 2015-06-23 | Broadcom Corporation | Method and system for compensated time stamping for time-sensitive network communications |
| JP5544896B2 (ja) * | 2010-01-22 | 2014-07-09 | 富士通株式会社 | 受信回路、情報処理装置、およびバッファ制御方法 |
| JP5525942B2 (ja) * | 2010-07-06 | 2014-06-18 | アンリツ株式会社 | 先頭レーン検出回路及び方法並びにデスキュー回路及び方法 |
| US20120030438A1 (en) * | 2010-07-29 | 2012-02-02 | Sarance Technologies Inc. | Method and Apparatus for Performing Skew Removal in the Receiver of a Multi-Lane Communication Link |
| US9356721B2 (en) * | 2012-06-26 | 2016-05-31 | Marvell World Trade Ltd. | Methods and apparatus for precision time stamping |
| WO2014052972A1 (en) * | 2012-09-28 | 2014-04-03 | Vitesse Semiconductor Corporation | High accuracy 1588 timestamping over high speed multi lane distribution physical code sublayers |
-
2013
- 2013-03-18 US US13/846,683 patent/US9167058B2/en active Active
-
2014
- 2014-03-17 JP JP2016504323A patent/JP6149150B2/ja active Active
- 2014-03-17 KR KR1020157028983A patent/KR102091302B1/ko active Active
- 2014-03-17 WO PCT/US2014/030774 patent/WO2014153298A2/en not_active Ceased
- 2014-03-17 CN CN201480016642.9A patent/CN105379220B/zh active Active
- 2014-03-17 EP EP14723591.5A patent/EP2976866B1/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP2976866A2 (en) | 2016-01-27 |
| KR20150133220A (ko) | 2015-11-27 |
| CN105379220B (zh) | 2017-12-01 |
| US20140269769A1 (en) | 2014-09-18 |
| US9167058B2 (en) | 2015-10-20 |
| EP2976866B1 (en) | 2017-05-03 |
| JP2016517680A (ja) | 2016-06-16 |
| CN105379220A (zh) | 2016-03-02 |
| WO2014153298A3 (en) | 2014-12-04 |
| KR102091302B1 (ko) | 2020-03-19 |
| WO2014153298A2 (en) | 2014-09-25 |
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