KR102012443B1 - Fan-out semiconductor package - Google Patents

Abstract

The present disclosure provides a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a first encapsulation material for sealing at least a portion of the inactive surface of the semiconductor chip, and a first encapsulation material on the first encapsulation material. And a connecting member disposed on an active surface of the semiconductor chip, wherein the connecting member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, and includes a material of the first sealing material and the second sealing material. It relates to a fan-out semiconductor package with different stiffness.

Description

Fan-Out Semiconductor Packages {FAN-OUT SEMICONDUCTOR PACKAGE}

The present disclosure relates to a semiconductor package, for example, a fan-out semiconductor package that can extend the connection terminal beyond the region where the semiconductor chip is disposed.

One of the main trends in the recent development of technology for semiconductor chips is to reduce the size of components, and thus, in the field of packaging, it is required to implement a large number of pins with small sizes in response to the rapid increase in demand for small semiconductor chips. .

One of the proposed package technologies is a fan-out package. The fan-out package reroutes the connection terminals beyond the area where the semiconductor chip is placed, enabling a small number of pins.

One of the several objectives of the present disclosure is to provide a fan-out semiconductor package which is excellent in rigidity and which can be thinned and process simplified.

One of the various solutions proposed through the present disclosure is to introduce a connection member having a redistribution layer to place the semiconductor chip in the through-hole of the connection member, and to seal the semiconductor chip with a suture material of excellent rigidity, It is covered with a suture of material.

For example, a fan-out semiconductor package according to an example proposed through the present disclosure may be disposed in a first connection member having a through hole, an active surface in which a connection pad is disposed, and an opposite side of the active surface. A first encapsulant for sealing at least a portion of the inactive surface of the semiconductor chip, the first connecting member and the semiconductor chip, the second encapsulant disposed on the first encapsulant, and the first connecting member; A second connection member disposed on an active surface of the semiconductor chip, wherein the first connection member and the second connection member each include a redistribution layer electrically connected to a connection pad of the semiconductor chip, and the first encapsulant is an insulating resin. , Glass fibers, and an inorganic filler, and the second encapsulant may include an insulating resin and an inorganic filler.

Alternatively, a first connection member having a fan-out semiconductor through hole according to an example proposed through the present disclosure, an active surface disposed in the through hole of the first connection member and having a connection pad disposed thereon, and an inactive surface disposed opposite to the active surface. A semiconductor chip having a surface, a first sealing member for sealing at least a portion of an inactive surface of the first connecting member and the semiconductor chip, a second sealing material disposed on the first sealing material, and activation of the first connecting member and the semiconductor chip And a second connection member disposed on the surface, wherein the first connection member and the second connection member each include a redistribution layer electrically connected to the connection pad of the semiconductor chip, and the first sealing material is more elastic than the second sealing material. The modulus may be large.

One of several effects of the present disclosure may provide a fan-out semiconductor package having excellent rigidity and enabling thinning and process simplification.

1 is a block diagram schematically illustrating an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3 is a cross-sectional view schematically showing before and after packaging of a fan-in semiconductor package.
4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.
6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.
7 is a cross-sectional view illustrating a schematic view of a fan-out semiconductor package.
8 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.
9 is a schematic cross-sectional view of an example of a fan-out semiconductor package.
FIG. 10 is a schematic II ′ cut top view of the fan-out semiconductor package of FIG. 9.
FIG. 11 is an example of a schematic manufacturing process of the fan-out semiconductor package of FIG. 9.
12 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
13 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
14 schematically shows an example of a material that can be used as the material of the encapsulant and / or passivation layer of a fan-out semiconductor package.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. Shape and size of the elements in the drawings may be exaggerated or reduced for more clear description.

Electronics

1 is a block diagram schematically illustrating an example of an electronic device system.

Referring to the drawings, the electronic apparatus 1000 accommodates the main board 1010. The chip-related component 1020, the network-related component 1030, and the other component 1040 are physically and / or electrically connected to the main board 1010. These are also combined with other components described below to form various signal lines 1090.

The chip related component 1020 may include a memory chip such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPUs), graphics processors (eg, GPUs), digital signal processors, cryptographic processors, microprocessors, microcontrollers; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) may be included, but are not limited thereto. In addition, other types of chip-related components may be included. Of course, these components 1020 may be combined with each other.

Network-related components 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond. Any of the standards or protocols may be included. In addition, of course, the network related component 1030 may be combined with the chip related component 1020.

Other components 1040 include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electro magnetic interference (EMI) filters, multi-layer ceramic condenser (MLCC), and the like. However, the present invention is not limited thereto, and may include passive components used for various other purposes. In addition, other components 1040 may be combined with each other along with the chip-related component 1020 and / or the network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other components include camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass ( Not shown), accelerometer (not shown), gyroscope (not shown), speakers (not shown), mass storage (e.g., hard disk drive) (not shown), compact disk (not shown), and DVD (digital versatile disk) (not shown) and the like, but is not limited thereto. In addition, other components used for various purposes may be included according to the type of the electronic device 1000.

The electronic device 1000 may include a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer ( computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, and the like. However, the present invention is not limited thereto, and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, the semiconductor package is applied to various electronic devices as described above for various uses. For example, a main board 1110 is accommodated in the body 1101 of the smart phone 1100, and various components 1120 are physically and / or electrically connected to the main board 1110. In addition, other components, such as camera 1130, may or may not be physically and / or electrically connected to main board 1110, are housed in body 1101. Some of the components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor, but is not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

Semiconductor package

Generally, a semiconductor chip is integrated with a large number of fine electric circuits, but it cannot function as a finished semiconductor by itself, and there is a possibility of being damaged by an external physical or chemical impact. Therefore, instead of using the semiconductor chip itself, the semiconductor chip is packaged and used for electronic devices in a packaged state.

The need for semiconductor packaging is due to the difference in circuit width between the semiconductor chip and the mainboard of the electronics, in terms of electrical connections. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very small, whereas in the case of a main board used in electronic equipment, the size of the component mounting pad and the spacing of the component mounting pads are much larger than the scale of the semiconductor chip. . Therefore, it is difficult to directly mount a semiconductor chip on such a main board and a packaging technology that can buffer a difference in circuit width between each other is required.

The semiconductor package manufactured by the packaging technology may be classified into a fan-in semiconductor package and a fan-out semiconductor package according to structure and use.

Hereinafter, a fan-in semiconductor package and a fan-out semiconductor package will be described in more detail with reference to the accompanying drawings.

(Fan-in Semiconductor Package)

3 is a cross-sectional view schematically showing before and after packaging of a fan-in semiconductor package.

4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawing, the semiconductor chip 2220 may include a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like, such as aluminum (Al) formed on one surface of the body 2221. For example, including a connection pad 2222 including a conductive material, and a passivation film 2223 formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222, such as an oxide film or a nitride film. It may be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit IC may be hardly mounted on a middle level printed circuit board (PCB) as well as a main board of an electronic device.

Accordingly, in order to redistribute the connection pads 2222, the connection members 2240 are formed on the semiconductor chips 2220 in accordance with the size of the semiconductor chips 2220. The connecting member 2240 is formed on the semiconductor chip 2220, an insulating layer 2241 using an insulating material such as photosensitive insulating resin (PID), and after forming a via hole (2243h) for opening the connection pad 2222, The wiring patterns 2242 and the vias 2243 may be formed and formed. Thereafter, a passivation layer 2250 is formed to protect the connecting member 2240, an opening 2251 is formed, and an under bump metal layer 2260 is formed. That is, through a series of processes, for example, the fan-in semiconductor package 2200 including the semiconductor chip 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 is manufactured. do.

As described above, the fan-in semiconductor package is a package in which all connection pads of semiconductor chips, for example, I / O (Input / Output) terminals are arranged inside the device, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost. have. Therefore, many devices in a smart phone are manufactured in the form of a fan-in semiconductor package, and in particular, developments have been made to realize a small and fast signal transmission.

However, in the fan-in semiconductor package, all the I / O terminals must be disposed inside the semiconductor chip. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a small semiconductor chip. In addition, due to this vulnerability, a fan-in semiconductor package cannot be directly mounted and used on the main board of the electronic device. Even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have the size and spacing enough to be directly mounted on the main board of the electronic device.

5 is a cross-sectional view schematically illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222, that is, the I / O terminals of the semiconductor chip 2220 are redistributed again through the interposer substrate 2301. The electronic device may be mounted on the main board 2500 of the electronic device in a state where the fan-in semiconductor package 2200 is mounted on the interposer substrate 2301. In this case, the solder ball 2270 may be fixed with the underfill resin 2280, etc., and the outside may be covered with the molding material 2290. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads of the semiconductor chip 2220 may be embedded by the interposer substrate 2302 in the embedded state. 2222, that is, the I / O terminals may be redistributed once again and finally mounted on the motherboard 2500 of the electronic device.

As such, since the fan-in semiconductor package is difficult to be directly mounted on the main board of the electronic device, the fan-in semiconductor package is mounted on a separate interposer board and then again packaged and mounted on the main board of the electronic device, or the interposer It is mounted on an electronic main board while being embedded in a substrate.

(Fan-Out Semiconductor Package)

7 is a cross-sectional view illustrating a schematic view of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor chip 2120 is protected by the encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member. By 2140, the semiconductor chip 2120 is rearranged to the outside of the semiconductor chip 2120. In this case, the passivation layer 2150 may be further formed on the connection member 2140, and the under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. The solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2241, and a via 2143 for electrically connecting the connection pad 2122 and the redistribution layer 2142. Can be.

As described above, the fan-out semiconductor package is a form in which I / O terminals are rearranged to the outside of the semiconductor chip through a connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip, and as the device size becomes smaller, the ball size and pitch must be reduced, so that a standardized ball layout cannot be used. On the other hand, the fan-out semiconductor package is a type in which I / O terminals are rearranged to the outside of the semiconductor chip through a connection member formed on the semiconductor chip. Can be used as it is, it can be mounted on the main board of the electronic device without a separate interposer board as described below.

8 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.

Referring to the drawing, the fan-out semiconductor package 2100 may be mounted on the main board 2500 of the electronic device through the solder ball 2170. That is, as described above, the fan-out semiconductor package 2100 may connect the connection pads 2122 on the semiconductor chip 2120 to a fan-out area beyond the size of the semiconductor chip 2120. Since 2140 is formed, a standardized ball layout may be used as it is, and as a result, it may be mounted on the main board 2500 of the electronic device without a separate interposer substrate.

As such, since the fan-out semiconductor package can be mounted on the main board of the electronic device without a separate interposer board, the fan-out semiconductor package can be made thinner and thinner than the fan-in semiconductor package using the interposer board. Do. Its excellent thermal and electrical properties make it particularly suitable for mobile products. In addition, the present invention can be more compactly implemented than a typical package on package (POP) type using a printed circuit board (PCB), and solves a problem due to warpage.

Meanwhile, the fan-out semiconductor package refers to a package technology for mounting a semiconductor chip on a main board of an electronic device and the like, and protecting the semiconductor chip from external shocks. The concept is different from a printed circuit board (PCB) such as an interposer substrate in which a fan-in semiconductor package is embedded.

Hereinafter, a fan-out semiconductor package capable of maintaining rigidity and thinning and process simplification will be described with reference to the accompanying drawings.

9 is a schematic cross-sectional view of an example of a fan-out semiconductor package.

FIG. 10 is a schematic II ′ cut top view of the fan-out semiconductor package of FIG. 9.

Referring to the drawings, the fan-out semiconductor package 100A according to an example is disposed in the first connection member 110 having the through hole 110H, the through hole 110H of the first connection member 110, and a connection pad. A first sealing portion of the semiconductor chip 120, the first connection member 110, and at least a portion of the non-active surface of the semiconductor chip 120 having an active surface on which the 122 is disposed and an inactive surface disposed on an opposite side of the active surface The encapsulant 130, the second encapsulant 180 disposed on the first encapsulant 130, and the second connecting member disposed on the active surfaces of the first connecting member 110 and the semiconductor chip 120. 140. The first connection member 110 includes redistribution layers 112a, 112b and 112c electrically connected to the connection pads 122 of the semiconductor chip 120. The second connection member 140 also includes a redistribution layer 142 electrically connected to the connection pad 122 of the semiconductor chip 120. The first encapsulant 130 includes a resin 130a, a core 130b, and a filler 130c. The second encapsulant 180 may include a resin and a filler, but may not include a core material. The first encapsulant 130 may have a larger elastic modulus than the second encapsulant 180.

In general, a reinforcing layer is used to control warpage generated during the manufacturing process of the semiconductor package. The reinforcement layer may be attached separately on the encapsulant. The reinforcement layer may include a material having excellent rigidity, and thus, the rigidity of the package may be maintained by attaching the reinforcement layer. However, there is a problem that the manufacturing process of the package is complicated to be manufactured by attaching the reinforcing layer separately. In addition, there is a problem that a limitation occurs in thinning due to the attachment of the reinforcing layer. In addition, when attaching the reinforcing layer may be difficult to form an opening on the upper side of the package. Therefore, it may be difficult to form a mark or apply it to a package-on-package or the like.

On the other hand, the fan-out semiconductor package 100A according to an example uses a material having excellent rigidity including the resin 130a, the core 130b, and the filler 130c as the first encapsulant 130. The rigidity of the package 100A can be maintained without the reinforcing layer of. That is, it is possible to maintain sufficient rigidity of the package 100A without additional processing, and to be thin. In addition, cost reduction of raw materials is possible. In particular, a second encapsulant 180 having a different material from the first encapsulant 130 is disposed on the first encapsulant 130, wherein the second encapsulant 180 does not include a core material, and a resin and a filler. May contain only. Therefore, it may be easy to form an opening penetrating the first encapsulant 130 through the second encapsulant 180.

In addition, the fan-out semiconductor package 100A according to an example may include redistribution layers 112a, 112b and 112c through which the first connection member 110 may redistribute the connection pads 122. Therefore, it is possible to minimize the number of layers of the second connection member 140 as well as to increase the degree of design freedom, and to further reduce the thickness of the package 100A, and furthermore, the second connection member after the semiconductor chip 120 is disposed. It may be possible to improve the yield reduction problem due to the (140) poor formation.

Meanwhile, the fan-out semiconductor package 100A according to an example penetrates the backside redistribution layer 132 disposed on the second encapsulant 180, and the first encapsulant 130 and the second encapsulant 180. The backside redistribution layer 132 may further include a backside via 133 connecting the redistribution layer 112c of the first connection member 110. Therefore, of course, the degree of freedom of design can be further increased, and the thickness of the package 100A can be further reduced. In some cases, the backside redistribution layer 132 may include a panel-shaped ground pattern, wherein the ground pattern of the backside redistribution layer 132 covers the inactive surface of the semiconductor chip 120. The shielding and / or heat dissipation effect may be improved.

Meanwhile, the fan-out semiconductor package 100A according to an example is disposed on the second connection member 140 and the first opening 151 exposing at least a portion of the redistribution layer 142 of the second connection member 140. A second passivation layer 190 having a first passivation layer 150 having a second passivation layer 190 disposed on the second encapsulant 180 and exposing at least a portion of the backside redistribution layer 132. It may further include. By arranging these, the components inside the package 100A may be protected, and warpage improvement may also be performed. In this case, the first passivation layer 150 and the second passivation layer 190 may each include a resin and a filler, wherein the weight percentage of the filler included in the first passivation layer 150 is the second passivation layer 190. ) May be greater than the weight percent of the filler included in the). This further improves warpage and board level levels by adjusting the overall coefficient of thermal expansion (CTE).

Meanwhile, the fan-out semiconductor package 100A according to an example is formed on the first opening 151 and is under bump metal layer 160 connected to the redistribution layer 142 of the exposed second connection member 140, and under. It may further include a connection terminal 170 formed on the bump metal layer 160 and electrically connected to the redistribution layer 142 of the second connection member 140 exposed through the under bump metal layer 160. The board level reliability may be further improved by improving the connection reliability of the connection terminal 170 through the under bump metal layer 160. The package 100A may be electrically connected to the main board through the connection terminal 170.

Meanwhile, the fan-out semiconductor package 100A according to an example further includes passive components 125 disposed side-by-side with a predetermined distance from the connection terminal 170 on the first passivation layer 150. It may include. The passive component 125 may be a land side capacitor (LSC) or the like, and may be electrically connected to the connection pad 122 of the semiconductor chip 120 through the redistribution layer 142 of the second connection member 140. Can be. Since the passive component 125 is disposed on the first passivation layer 150, it does not particularly affect the thickness of the package 100A and may not affect the design of the redistribution layer 142.

Hereinafter, each configuration included in the fan-out semiconductor package 100A according to an example will be described in more detail.

The first connection member 110 includes redistribution layers 112a, 112b and 112c for redistributing the connection pads 122 of the semiconductor chip 120, thereby reducing the number of layers of the second connection member 140. . If necessary, the rigidity of the package 100A may be further improved according to a specific material, and the role of securing the thickness uniformity of the first encapsulant 130 may be performed. The fan-out semiconductor package 100A according to the example may be used as a package on package (POP) type by the first connection member 110. The first connection member 110 has a through hole 110H. The semiconductor chip 120 is disposed in the through hole 110H to be spaced apart from the first connection member 110 by a predetermined distance. The circumference of the side surface of the semiconductor chip 120 may be surrounded by the first connection member 110. However, this is only an example and may be variously modified in other forms, and other functions may be performed according to the form.

The first connection member 110 is in contact with the second connection member 140, the first insulating layer 111a, and the second connection member 140 is in contact with the first rewiring layer 112a embedded in the first insulating layer 111a. ), The second wiring layer 112b disposed on the side opposite to the side where the first wiring layer 112a of the first insulating layer 111a is buried, and the second wiring layer disposed on the first insulating layer 111a. The second insulating layer 111b covering the 112b and the third rewiring layer 112c disposed on the second insulating layer 111b are included. The first to third rewiring layers 112a, 112b, and 112c are electrically connected to the connection pads 122. The first and second wiring layers 112a and 112b and the second and third wiring layers 112b and 112c respectively pass through the first and second insulating layers 111a and 111b, respectively. Electrical connection via 113b).

When the first rewiring layer 112a is buried in the first insulating layer 111a, the step difference caused by the thickness of the first rewiring layer 112a is minimized, and the insulating distance of the second connection member 140 is reduced. Becomes constant. That is, the distance from the redistribution layer 142 of the second connection member 140 to the bottom surface of the first insulating layer 111a and the semiconductor chip 120 from the redistribution layer 142 of the second connection member 140. The difference in distance to the connection pad 122 may be smaller than the thickness of the first rewiring layer 112a. Therefore, the high density wiring design of the second connection member 140 may be easy.

The lower surface of the first rewiring layer 112a of the first connection member 110 may be located above the lower surface of the connection pad 122 of the semiconductor chip 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the redistribution layer 112a of the first connection member 110 may be equal to the redistribution layer 142 of the second connection member 140 and the semiconductor chip 120. It may be greater than the distance between the connection pad 122 of the). This is because the first rewiring layer 112a may be recessed into the insulating layer 111. As described above, when the first wiring layer 112a is recessed into the first insulating layer and the lower surface of the first insulating layer 111a and the lower surface of the first wiring layer 112a have a step, the first encapsulant ( 130, the forming material may be prevented from bleeding to contaminate the first rewiring layer 112a. The second rewiring layer 112b of the first connection member 110 may be located between the active surface and the inactive surface of the semiconductor chip 120. The first connection member 110 may be formed to a thickness corresponding to the thickness of the semiconductor chip 120, so that the second rewiring layer 112b formed inside the first connection member 110 may be formed of the semiconductor chip 120. It can be placed at a level between the active and inactive surfaces.

The thickness of the redistribution layers 112a, 112b and 112c of the first connection member 110 may be thicker than the thickness of the redistribution layer 142 of the second connection member 140. The first connection member 110 may have a thickness greater than or equal to that of the semiconductor chip 120, and the redistribution layers 112a, 112b, and 112c may also be formed in a larger size according to the scale. On the other hand, the redistribution layer 142 of the second connection member 140 can be formed in this relatively small size for thinning.

The material of the insulating layers 111a and 111b is not particularly limited. For example, an insulating material may be used, wherein the insulating material is a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or these resins together with an inorganic filler and glass fiber (Glass Fiber, Glass Cloth, Glass Fabric). Resin impregnated with a core material such as, for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bisaleimide Triazine (BT) and the like can be used. If necessary, Photo Imagable Dielectric (PID) resins may be used.

The redistribution layers 112a, 112b, and 112c may serve to rewire the connection pads 122 of the semiconductor chip 120. The material for forming the redistribution layers 112a, 112b, and 112c includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium. Conductive materials, such as (Ti) or these alloys, can be used. The redistribution layers 112a, 112b, and 112c may perform various functions according to the design design of the layer. For example, it may include a ground (GrouND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like. Here, the signal S pattern includes various signals except for a ground GND pattern, a power PWR pattern, and the like, for example, a data signal. Also, a via pad, a wire pad, a connection terminal pad, and the like may be included.

The vias 113a and 113b electrically connect the redistribution layers 112a, 112b and 112c formed on different layers, thereby forming an electrical path in the first connection member 110. The vias 113a and 113b may also be formed of a conductive material. The vias 113a and 113b may be completely filled with a conductive material, or the conductive material may be formed along the wall surface of the via hole. Moreover, not only a taper shape but all well-known shapes, such as a cylindrical shape, can be applied.

When forming a hole for the first via 113a, some pads of the first rewiring layer 112a may serve as a stopper. The first via 113a may have a width at an upper side thereof and a width at a lower side thereof. Larger tapered shapes may be advantageous in process. In this case, the first via 113a may be integrated with the pad pattern of the second rewiring layer 112b. In addition, when forming a hole for the second via 113b, some pads of the second wiring layer 112b may serve as a stopper, and the second via 113b may have a lower width at an upper surface thereof. It may be advantageous in process to have a tapered shape larger than the width of. In this case, the second via 113b may be integrated with the pad pattern of the third rewiring layer 112c.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions or more of devices are integrated in one chip. In this case, the integrated circuit may include, for example, a processor such as a central processor (eg, a CPU), a graphics processor (eg, a GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like. The chip may be an application processor (AP), but is not limited thereto. For example, a logic chip such as an analog-to-digital converter or an application-specific IC (ASIC), a volatile memory (eg, a DRAM), Memory chips such as volatile memory (eg, ROM), flash memory, and the like. Of course, they may be arranged in combination with each other.

The semiconductor chip 120 may be an integrated circuit (IC) formed based on an active wafer, and in this case, the base materials constituting the body 121 include silicon (Si), germanium (Ge), and gallium arsenide (GaAs). And the like can be used. Various circuits may be formed in the body 121. The connection pad 122 is used to electrically connect the semiconductor chip 120 with other components, and a conductive material such as aluminum (Al) may be used as a forming material without particular limitation. The passivation film 123 exposing the connection pad 122 may be formed on the body 121, and the passivation film 123 may be an oxide film, a nitride film, or the like, or a double layer of the oxide film and the nitride film. The lower surface of the connection pad 122 may have a step with the lower surface of the first encapsulant 130 through the passivation layer 123, and may prevent the first encapsulant 130 from bleeding to the lower surface of the connection pad 122. can do. An insulating film (not shown) or the like may be further disposed at other necessary positions.

The passive component 125 may be various kinds of passive components. For example, the passive component 125 may be a Multi Layer Ceramic Capacitor (MLCC), a Low Inductance Chip Capacitor (LICC), a Land Side Capacitor (LSC), an inductor, an Integrated Passive Device (IPD), or the like. In order to reduce the thickness, the passive component 125 may preferably use a Land Side Capacitor (LSC), and the LSC may be electrically connected to a power P pattern of the redistribution layer 142 of the second connection member 140. It is not limited to this. Passive components 125 may be provided in plurality, in which case they may be the same or different from each other. The passive component 125 may be attached to the first passivation layer 150 by using a solder or the like so as to be arranged side by side with a predetermined distance spaced apart from the connection terminal 170.

The first encapsulant 130 may protect the first connection member 110, the semiconductor chip 120, and the like. The encapsulation type is not particularly limited, and may include any type of encapsulating at least a portion of the first connection member 110 and the semiconductor chip 120. For example, the first encapsulant 130 may cover the inactive surface of the first connection member 110 and the semiconductor chip 120, and may be disposed between the wall surface of the through hole 110H and the side surface of the semiconductor chip 120. You can fill the space. In addition, the first encapsulant 130 may fill at least a portion of the space between the passivation film 123 and the second connection member 140 of the semiconductor chip 120. As the first encapsulant 130 fills the through hole 110H, the first encapsulant 130 may reduce the buckling while serving as an adhesive agent according to a specific material.

The first encapsulant 130 includes a resin 130a, a core 130b, and a filler 130c. The resin 130a may be an insulating resin, specifically, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, and the core material 130b may be glass fiber, glass cloth, glass fabric, or the like. 130c may be an inorganic filler such as silica or alumina, but is not limited thereto. For example, the first encapsulant 130 may be a prepreg, an unclad copper clad laminate, or a GC material described below, but is not limited thereto. As such, the first encapsulant 130 includes the core material 130b to maintain rigidity of the package 100A. In addition, since the first encapsulant 130 includes the filler 130c, it is possible to adjust the thermal expansion coefficient, thus improving warpage generation due to mismatch of the thermal expansion coefficient.

The first encapsulant 130 may form and seal the first connection member 110 and the semiconductor chip 120 in an uncured state. Thus, the resin 130a and the filler 130c may form the first connection member 110. ) And on the inactive surface of the semiconductor chip 120 as well as in the space between the wall surface of the through hole 110H and the side surface of the semiconductor chip 120. On the other hand, the core material 130b may be disposed only on the inactive surfaces of the first connection member 110 and the semiconductor chip 120. On the other hand, since the core material 130b is disposed above, the rigidity can be maintained at the upper portion of the package 100A.

The second encapsulant 180 includes a resin and a filler. The second encapsulant 180 may not include a core material. The resin may be an insulating resin, specifically, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide, and the filler may be an inorganic filler such as silica or alumina, but is not limited thereto. For example, the second encapsulant 180 may be ABF, but is not limited thereto. As such, by introducing the second encapsulant 180, the opening may be easily formed in the first encapsulant 130, which is difficult to form the opening in itself. In addition, the symmetry with the first passivation layer 150 may be more effective for overall warpage control of the package 100A. The first encapsulant 130 may use a GCP material, which will be described later, and thus, at least a part of the surface of the first encapsulant 130 which contacts the second encapsulant 180 may contact the second encapsulant 180. Layers (not shown) may be disposed.

The first encapsulant 130 may have a larger elastic modulus than the second encapsulant 180. That is, the first encapsulant 130 includes a core material 130a, and thus may have superior rigidity as compared with the second encapsulant 180. As such, the elastic modulus may maintain rigidity with the first encapsulant 130 having a relatively large elastic modulus, and complement the limitation of the material of the first encapsulant 130 with the second encapsulant 180 having a relatively small elastic modulus. . Elastic Modulus refers to the ratio of stress and strain, and is measured by, for example, standard tensile tests specified in JIS C-6481, KS M 3001, KS M 527-3, ASTM D882, etc. can do.

The backside redistribution layer 132 may serve to redistribute the connection pads 122, and if necessary, cover the upper side of the semiconductor chip 120 to shield and / or radiate heat. Materials for forming the backside redistribution layer 132 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). Or conductive materials such as alloys thereof can be used. The backside redistribution layer 132 may perform various functions according to the design design of the layer. For example, it may include a ground (GrouND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like. Here, the signal S pattern includes various signals except for a ground GND pattern, a power PWR pattern, and the like, for example, a data signal. Also, a via pad, a connection terminal pad, and the like may be included.

The backside via 133 connects the backside redistribution layer 132 and the third rewiring layer 112c of the first connection member 110. This enables electrical connection to the upper side of the package 100A. Materials for forming the backside vias 133 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Or conductive materials, such as these alloys, can be used. The backside via 133 may be completely filled with a conductive material, or the conductive material may be formed along a wall of the via. In addition, all shapes known in the art may be applied.

The second connection member 140 may redistribute the connection pads 122 of the semiconductor chip 120. Through the second connection member 140, the connection pads 122 of the hundreds or hundreds of semiconductor chips 120 having various functions may be redistributed, and physically and / or externally connected to the function through the connection terminal 170. Or electrically connected. The second connection member 140 passes through the insulating layer 141, the redistribution layer 142 disposed on the insulating layer 141, and the via 143 through the insulating layer 141 and connecting the redistribution layer 142. It includes. The second connection member 140 may be composed of a single layer, or may be composed of a plurality of layers having a larger number of layers depending on the design.

An insulating material may be used as the material of the insulating layer 141. In this case, a photosensitive insulating material such as PID resin may be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has a photosensitive property, the insulating layer 141 may be formed thinner, and the fine pitch of the via 143 may be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layer 141 is a multilayer, these materials may be identical to each other, and may be different from each other as necessary. In the case where the insulating layer 141 is a multilayer, they may be integrated according to the process and the boundary may be unclear.

The redistribution layer 142 may serve to substantially redistribute the connection pads 122, and the forming materials may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), and gold ( Conductive materials such as Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used. The redistribution layer 142 may perform various functions according to the design design of the layer. For example, it may include a ground (GrouND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like. Here, the signal S pattern includes various signals except for a ground GND pattern, a power PWR pattern, and the like, for example, a data signal. Also, a via pad, a connection terminal pad, and the like may be included.

The via 143 electrically connects the redistribution layer 142 and the connection pad 122 formed on different layers, thereby forming an electrical path in the package 100B. The material for forming the via 143 may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Conductive materials, such as these alloys, can be used. Via 143 may be completely filled with a conductive material, or the conductive material may be formed along a wall of the via. In addition, all shapes known in the art, such as tapered shape and cylindrical shape, can be applied.

The first passivation layer 150 may protect the second connection member 140 from external physical and chemical damage. The first passivation layer 150 may have an opening 151 exposing at least a portion of the redistribution layer 142 of the second connection member 140. Tens to thousands of such openings 151 may be formed in the first passivation layer 150. The first passivation layer 150 may include a resin and a filler, but may not include a core material. That is, the first passivation layer 150 may be, for example, ABF, including the insulating resin and the inorganic filler as described above, and in this case, the first passivation layer 150 may have a symmetrical effect with the second encapsulant 180, thereby forming the entire package 100A. It may be easier to warp control.

The under bump metal layer 160 is an additional configuration, which improves the connection reliability of the connection terminal 170, and as a result, improves the board level reliability of the package 100A. The under bump metal layer 160 is connected to the redistribution layer 142 of the second connection member 140 exposed through the opening 151 of the first passivation layer 150. The under bump metal layer 160 may be formed in the opening 151 of the first passivation layer 150 by a known metallization method using a known conductive material, that is, a metal, but is not limited thereto.

The connection terminal 170 is an additional configuration for physically and / or electrically connecting the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A may be mounted on the main board of the electronic device through the connection terminal 170. The connection terminal 170 may be formed of a conductive material, for example, solder, but this is only an example and the material is not particularly limited thereto. The connection terminal 170 may be a land, a ball, a pin, or the like. The connection terminal 170 may be formed of multiple layers or a single layer. If formed in a multi-layer may include a copper pillar (pillar) and solder, when formed in a single layer may include tin-silver solder or copper, but this is also merely an example and not limited thereto. .

The number, spacing, arrangement, etc. of the connection terminals 170 are not particularly limited, and can be sufficiently modified according to design matters by a person skilled in the art. For example, the number of connection terminals 170 may be several tens to thousands, depending on the number of connection pads 122, the number of the connection terminal 170 may be more or less. When the connection terminal 170 is a solder ball, the connection terminal 170 may cover a side surface formed by extending on one surface of the first passivation layer 150 of the under bump metal layer 160, and the connection reliability may be more excellent. have.

At least one of the connection terminals 170 is disposed in the fan-out area. The fan-out area refers to an area outside the area where the semiconductor chip 120 is disposed. Fan-out packages are more reliable than fan-in packages, enable multiple I / O terminals, and facilitate 3D interconnection. In addition, compared to a ball grid array (BGA) package and a land grid array (LGA) package, the package thickness can be manufactured thinner, and the price is excellent.

The second passivation layer 190 may protect the backside redistribution layer 132 and the like from external physical and chemical damage. The second passivation layer 190 may be a photosensitive material including a filler and a resin, for example, a solder resist, but is not limited thereto. The second passivation layer 190 may have an opening 191 exposing at least a portion of the backside redistribution layer 132. The surface treatment layer P may be disposed on a surface of the backside redistribution layer 132 exposed through the opening 191. The surface treatment layer P may be, for example, Ni / Au, Ni / Pd / Au, or the like, but is not limited thereto. Meanwhile, the weight percentage of the filler included in the first passivation layer 150, specifically, the inorganic filler, may be greater than the weight percentage of the filler included in the second passivation layer 190, specifically, the inorganic filler. The warpage control can be more effectively performed by adjusting the thermal expansion coefficient of the package 100A.

Although not shown in the drawings, a metal thin film may be formed on the wall surface of the through hole 110H for the purpose of heat radiation and / or electromagnetic shielding if necessary. If necessary, a plurality of semiconductor chips 120 that perform the same or different functions may be disposed in the through hole 110H. If necessary, a separate passive component such as an inductor or a capacitor may be disposed in the through hole 110H. In addition, if necessary, a separate surface mounting component may be mounted on the surface of the first passivation layer 150.

FIG. 11 is an example of a schematic manufacturing process of the fan-out semiconductor package of FIG. 9.

Referring to FIG. 11A, a first connection member 110 is prepared. The first connection member 110 forms a first wiring layer 112a on a carrier film having metal films formed on both surfaces thereof, and sequentially the first insulating layer 111a, the second wiring layer 112b, and the first via ( 113a), the second insulating layer 111b, the third wiring layer 112c, and the second via 113b are formed, and then, they are separated from the carrier film, and the metal film remaining on the first wiring layer 112a is etched. Can be formed. Next, a through hole 110H penetrating the first connection member 110 is formed. The through hole 110H may be formed by a mechanical drill and / or a laser drill. However, the present invention is not limited thereto, and may be performed by a sand blast method using abrasive particles, a dry etching method using plasma, or the like. When formed using a mechanical drill and / or a laser drill, the desmear process, such as a permanganate method, can be performed and the resin smear in the hole 110H can be removed. Next, the adhesive film 200 is attached to the lower side of the first connection member 110. The adhesive film 200 can be used as long as it can fix the first connection member 110, a known tape or the like can be used as an example that is not limited. As an example of a well-known tape, the heat-hardenable adhesive tape which weakens an adhesive force by heat processing, the ultraviolet curable adhesive tape which weakens an adhesive force by ultraviolet irradiation, etc. are mentioned. Next, the semiconductor chip 120 is disposed in the through hole 110H of the first connection member 110. For example, the semiconductor chip 120 is disposed on the adhesive film 200 in the through hole 110H. The semiconductor chip 120 may be disposed in a face-down form such that the connection pad 122 is attached to the adhesive film 200.

Referring to FIG. 11B, the semiconductor chip 120 is sealed using the first encapsulant 130. The first encapsulant 130 covers the inactive surface of the first connecting member 110 and the semiconductor chip 120, and fills a space in the through hole 110H. The first encapsulant 130 may be formed by laminating an uncured material including the resin 130a, the core 130b, and the filler 130c on the adhesive film 200, and then curing the material. It is preferable to use the GC material mentioned later as a material of the 1st sealing material 130. FIG. After sealing with the first encapsulant 130 is attached to the carrier film 250 on the first encapsulant 130. In the drawings, the unfinished package structure is disposed below and the carrier film 250 is disposed above, but in practice, the unfinished package structure may be attached to the carrier film 250 while being rotated 180 degrees as shown. have. The carrier film 250 may be, for example, a copper clad laminate (CCL) having metal films formed on both surfaces of a core layer such as a prepreg, but is not limited thereto. Next, the adhesive film 200 is peeled off. The peeling method is not particularly limited, and, for example, in the case of using a heat-curable adhesive tape whose adhesive force is weakened by heat treatment, an ultraviolet curable adhesive tape which weakens the adhesive force by ultraviolet irradiation, or the like, the adhesive film 200 Heat treatment of the 200 may be performed after weakening the adhesive force, or may be performed after the adhesive force is irradiated to the adhesive film 200 to weaken the adhesive force.

Referring to FIG. 11C, the second connection member 140 is formed on the first connection member 110 from which the adhesive film 200 is removed and the active surface of the semiconductor chip 120. The second connection member 140 forms the insulating layer 141 by a lamination method or a coating method, and the redistribution layer 142 using a patterning process and a plating process using a dry film or the like on the insulating layer 141. And vias 143 may be formed. The hole penetrating the insulating layer 141 for forming the via 143 may be formed using photolithography or the like. The redistribution layer 142 and the via 143 may be formed by forming a Ti / Cu seed layer by sputtering, forming a Cu plating layer by electroplating, and then etching a Ti / Cu seed layer other than the pattern. This may be repeated to form the second connection member 140 composed of a plurality of layers.

Referring to FIG. 11D, the carrier film 250 is peeled off. The peeling method of the carrier film 250 is not specifically limited. After peeling, the metal film 251 of the carrier film 250 may remain on the first encapsulant 130. Next, the dry film 280 is attached to the second connection member 140, and the metal film 251 remaining on the first encapsulant 130 is removed by etching. Meanwhile, the dry film 280 may protect the redistribution layer 142 of the second connection member 140 in the process of etching the metal film 251.

Referring to FIG. 11E, the dry film 280 is stripped. Next, the first passivation layer 150 is formed on the second connection member 140. In addition, the second encapsulant 180 is formed on the first encapsulant 130. The first passivation layer 150 and the second encapsulant 180 may be formed by laminating and curing a material including a resin and a filler, for example, ABF. Introducing layers of the same or similar material on the top of the package 100A and on the -G side can be effective for warpage control.

Referring to FIG. 11F, after the openings 151 are formed in the first passivation layer 150, an under bump metal layer 160 is formed in the openings 151. In addition, after forming holes penetrating the first encapsulant 130 and the second encapsulant 180, the backside redistribution layer 132 and the backside via 133 are formed. More specifically, the under bump metal layer 160 forms an opening 151 in the first passivation layer 150 through via processing and desmear processing, and then known plating and patterning methods such as seed layer formation and dry film patterning. And pattern fill plating, dry film peeling, seed layer etching, and the like. The backside redistribution layer 132 and the backside via 133 also form openings that penetrate the first encapsulant 130 and the second encapsulant 180 through via processing and desmearing, and then known plating and patterning methods. For example, it may be formed through a process such as seed layer formation, dry film patterning, pattern peel plating, dry film peeling, seed layer etching, and the like. Next, a second passivation layer 190 having an opening 191 exposing at least a portion of the backside redistribution layer 132 is formed on the second encapsulant 180. The second passivation layer 190 may be formed by, for example, a method of applying and curing a solder resist, and the opening 191 may be formed by photolithography or the like. The surface treatment layer P is formed on the exposed backside redistribution layer 132. The surface treatment layer P may be formed by, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / substituting plating, DIG plating, HASL, or the like. It is not limited. In addition, the connection terminal 170 and the passive component 125 are formed as necessary. The connection terminal 170 may be fixed by reflow, and part of the connection terminal 170 is buried in the first passivation layer 150 and the remaining part is exposed to the outside to enhance the fixing force, thereby improving reliability. Can be. The passive component 125 may be attached using Surface Mounting Technology (SMT), and soldering or micro sized solder balls may be used.

On the other hand, a series of processes to prepare a large capacity size of the first connecting member 110 to facilitate mass production, using this to manufacture a plurality of fan-out semiconductor package (100A), and then through the sawing (Sawing) process It may also be singulation into the individual fan-out semiconductor package 100A. In this case, there is an advantage that the productivity is excellent.

12 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

Referring to the drawings, the fan-out semiconductor package 100B according to another example includes not only the first encapsulant 130 but also the first passivation layer 150 as well as the resin 150a, the core 150b, and the filler 150c. It includes. The resin 150a may be an insulating resin, for example, a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as polyimide, and the core material 150b may be a glass fiber, glass cloth, glass fabric, or the like. Likewise, 150c may be an inorganic filler such as silica and alumina, but is not limited thereto. As such, the first passivation layer 150 also includes a core material 150b, and the first encapsulant 130 having excellent rigidity is disposed on the upper side of the package 100A, and the lower side of the package 100B has excellent rigidity. The first passivation layer 150 may be disposed to improve warpage spread. In addition, since the passivation layer 150 also includes a filler 150c, the thermal expansion coefficient can be adjusted, and thus, warpage generation due to mismatch of the thermal expansion coefficient can be improved.

Meanwhile, a primer layer (not shown) in contact with the under bump metal layer 160 may be disposed on at least a portion of the surface on which the first passivation layer 150 needs to be formed, that is, the surface on which the under bump metal layer 160 is formed. . The primer layer (not shown) may be a metal thin film including copper (Cu), but is not limited thereto. The primer layer (not shown) may be used as the base seed layer when forming the under bump metal layer 160. The primer layer (not shown) may have a rougher surface by a desmear treatment or the like, and thus may have excellent connection reliability with the under bump metal layer 160.

Other configurations and manufacturing methods are omitted in the fan-out semiconductor package 100A according to the above-described example.

13 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

Referring to the drawings, the fan-out semiconductor package 100C according to another example includes a first rewiring layer in which the first connection member 110 is disposed on both surfaces of the first insulating layer 111a and the first insulating layer 111a. Disposed on the second insulating layer 111b and the second insulating layer 112b and the first insulating layer 112a and covering the first insulating layer 112a. The third wiring layer 111c, the third insulating layer 111c disposed on the first insulating layer 111a to cover the second wiring layer 112b, and the third insulating layer 111c. Four rewiring layer 112d is included. The first to fourth rewiring layers 112a, 112b, 112c, and 112d are electrically connected to the connection pads 122. Since the first connection member 110 includes a greater number of redistribution layers 112a, 112b, 112c, and 112d, the second connection member 140 may be further simplified. Therefore, a decrease in yield due to defects occurring in the process of forming the second connection member 140 may be improved. Meanwhile, the first to fourth redistribution layers 112a, 112b, 112c, and 112d respectively pass through the first to third vias 113a, 113b, and 113c passing through the first to third insulating layers 111a, 111b, and 111c, respectively. It can be electrically connected through.

The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may basically be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may form a larger number of redistribution layers 112c and 112d. It may be introduced for. The first insulating layer 111a may include an insulating material different from the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second insulating layer 111c and the third insulating layer 111c may be a filler and an insulating material. It may be an ABF film or a PID film including a resin, but is not limited thereto. In a similar sense, the first via 113a penetrating the first insulating layer 111a has a diameter larger than the second and third vias 113b and 113c penetrating the second and third insulating layers 111b and 111c. Can be large.

The lower surface of the third rewiring layer 112c of the first connection member 110 may be located below the lower surface of the connection pad 122 of the semiconductor chip 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the third redistribution layer 112c of the first connection member 110 is greater than the redistribution layer 142 of the second connection member 140 and the semiconductor chip. It may be smaller than the distance between the connection pads 122 of the (120). This is because the third rewiring layer 112c may be disposed to protrude on the second insulating layer 111b, and as a result, may be in contact with the second connection member 140. The first and second rewiring layers 112a and 112b of the first connection member 110 may be located between the active and inactive surfaces of the semiconductor chip 120. The first connection member 110 may be formed to correspond to the thickness of the semiconductor chip 120, and the first and second rewiring layers 112a and 112b formed in the first connection member 110 are formed. The semiconductor chip 120 may be disposed at a level between an active surface and an inactive surface.

The thickness of the redistribution layers 112a, 112b, 112c and 112d of the first connection member 110 may be thicker than the thickness of the redistribution layer 142 of the second connection member 140. The first connection member 110 may have a thickness greater than or equal to that of the semiconductor chip 120, and the redistribution layers 112a, 112b, 112c, and 112d may also have a larger size. On the other hand, the redistribution layer 142 of the second connection member 140 can be formed in this relatively small size for thinning.

Other configurations and manufacturing methods are omitted in the fan-out semiconductor package 100A according to the above-described example. Meanwhile, as in the fan-out semiconductor package 100B according to another example, the material of the first passivation layer 150 of the fan-out semiconductor package 100C according to another example may be a material having excellent rigidity. to be.

14 schematically shows an example of a material that can be used as the material of the encapsulant and / or passivation layer of a fan-out semiconductor package.

Referring to the drawings, (a) schematically shows an example of a material in which circuit formation is unnecessary, for example, a GC material, and (b) shows a material in which circuit formation or a separate layer requires lamination. For example, an example of GCP material is shown schematically. In the case of GC material, an insulating layer 210 including an insulating resin, a core material, a filler, etc., a cover film 220 such as an OPP covering one surface of the insulating layer 210, a PET covering the other surface of the insulating layer 210, etc. It may include a base film 230. The insulating layer 210 may be cured after being laminated to the base substrate 240 in an uncured state and used as the cured insulating layer 210 ′. In the case of GCP material, an insulating layer 310 including an insulating resin, a core material, a filler, etc., a cover film 320 such as an OPP covering one surface of the insulating layer 310, a metal thin film covering the other surface of the insulating layer 310, etc. The primer layer 311 and the primer layer 311 may include a base film 330 such as PET covering one surface thereof. The insulating layer 310 may be cured after being laminated to the base substrate 340 in an uncured state and used as the cured insulating layer 310 ′. The primer layer 311 may be used in a state 311 ′ processed by a desmear process or the like in order to form a circuit or to deposit a separate layer. The GC material may be used when forming the first encapsulant 130, and the GCP material may be used when forming the first passivation layer 150, but is not limited thereto. That is, when forming the first encapsulant 130, GCP may be used to achieve additional purposes.

In the present disclosure, the lower side, the lower side, the lower side, and the like are used to mean the direction toward the mounting surface of the fan-out semiconductor package based on the cross section of the figure for convenience, and the upper side, the upper side, the upper side, and the like are used in the opposite direction. However, this is defined for convenience of description, and the scope of the claims is not specifically limited by the description of these directions.

In the present disclosure, the term "connected" is a concept including not only directly connected but also indirectly connected through an adhesive layer or the like. In addition, electrically connected means a concept that includes both a physical connection and a non-connection case. In addition, the first and second expressions are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component without departing from the scope of the right.

The expression example used in the present disclosure does not mean the same embodiment, but is provided to emphasize different unique features. However, the examples presented above do not exclude implementations in combination with the features of other examples. For example, although a matter described in one particular example is not described in another example, it may be understood as a description related to another example unless otherwise described or contradicted with the matter in another example.

The terms used in the present disclosure are merely used to describe examples and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" include plural forms unless the context clearly indicates otherwise.

1000: electronic device 1010: mainboard
1020: chip-related parts 1030: network-related parts
1040: other components 1050: camera
1060: antenna 1070: display
1080: battery 1090: signal line
1100: smartphone 1101: smartphone body
1110: smartphone motherboard 1111: motherboard insulation layer
1112: motherboard wiring 1120: components
1130: smartphone camera 2200: fan-in semiconductor package
2220: semiconductor chip 2221: body
2222: connection pad 2223: passivation film
2240: connecting member 2241: insulating layer
2242: redistribution layer 2243: vias
2250: passivation layer 2260: under bump metal layer
2270: solder ball 2280: underfill resin
2290: molding material 2500: main board
2301: interposer substrate 2302: interposer substrate
2100: fan-out semiconductor package 2120: semiconductor chip
2121: body 2122: connection pad
2140: connecting member 2141: insulating layer
2142: redistribution layer 2143: via
2150: passivation layer 2160: under bump metal layer
2170: solder ball 100: semiconductor package
100A to 100C: Fan-Out Semiconductor Package
110: first connecting member 111, 112a, 112b, 112c: insulating layer
112a, 112b, 112c, 112d: Redistribution layer 113: Via
120: semiconductor chip 121: body
122: connection pad 123: passivation film
125: passive component 130: encapsulant
131: opening 140: second connecting member
141: insulating layer 142: redistribution layer
143: Via 150: passivation layer
151: opening 160: under bump metal layer
170: connection terminal 180: encapsulant
190: passivation layer 191: opening
210: insulating layer 220: cover film
230: base film 240: base substrate
310: insulating layer 311: primer layer
330: base film 340: base substrate

Claims (32)

A core member having a through hole;
A semiconductor chip disposed in the through hole and having a first surface on which a connection pad is disposed and a second surface opposite to the first surface;
A first encapsulant covering at least a portion of each of the core member and the second surface of the semiconductor chip and filling at least a portion of the through hole; And
A connection member disposed on the core member and the first surface of the semiconductor chip; Including;
The connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip.
The first encapsulant includes an insulating resin, glass fiber, and an inorganic filler,
The glass fiber of the first encapsulant is disposed on the core member and the second surface of the semiconductor chip,
The inorganic filler of the first encapsulant is disposed on the core member and the second surface of the semiconductor chip, and in a space between the wall surface of the through hole and the side surface of the semiconductor chip.
Fan-out semiconductor package.
The method of claim 1,
A second encapsulant disposed on the first encapsulant; More,
The second encapsulant includes an insulating resin and an inorganic filler,
At least a portion of the surface on which the second encapsulant of the first encapsulant is disposed is disposed a primer layer in contact with the second encapsulant,
Fan-out semiconductor package.
Claim 3 has been abandoned upon payment of a set-up fee. The method of claim 1,
A passivation layer disposed on the connection member and having an opening exposing at least a portion of the redistribution layer of the connection member; And
An under bump metal layer formed on the opening and connected to the redistribution layer of the exposed connection member; More,
The passivation layer includes an insulating resin, glass fiber, and an inorganic filler,
Fan-out semiconductor package.
Claim 4 has been abandoned upon payment of a setup registration fee. The method of claim 3, wherein
At least a portion of the surface on which the under bump metal layer of the passivation layer is formed is disposed a primer layer in contact with the under bump metal layer,
Fan-out semiconductor package.
delete delete delete Claim 8 has been abandoned upon payment of a set-up fee. The method of claim 1,
The core member is disposed on a side opposite to a side in which a first insulating layer, a first wiring layer buried in the first insulating layer and in contact with the connection member, and the first wiring layer of the first insulating layer are embedded. A second wiring layer,
The first and second rewiring layer is electrically connected to the connection pad of the semiconductor chip,
Fan-out semiconductor package.
Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8,
The core member further includes a second insulating layer disposed on the first insulating layer and covering the second wiring layer, and a third wiring layer disposed on the second insulating layer,
The third rewiring layer is electrically connected to the connection pad of the semiconductor chip,
Fan-out semiconductor package.
Claim 10 has been abandoned upon payment of a setup registration fee. The method of claim 9,
A passivation layer disposed on the connection member and having an opening exposing at least a portion of the redistribution layer of the connection member; And
An under bump metal layer formed on the opening and connected to the redistribution layer of the exposed connection member; More,
The passivation layer includes an insulating resin, glass fiber, and an inorganic filler,
Fan-out semiconductor package.
A semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposite to the first surface;
A first encapsulation material sealing at least a portion of a second surface of the semiconductor chip;
A second encapsulant disposed on the first encapsulant;
A first connection member disposed on the first surface of the semiconductor chip; And
A second connecting member having a through hole; Including;
The semiconductor chip is disposed in the through hole of the second connection member,
The first and second connection members each include a redistribution layer electrically connected to the connection pad of the semiconductor chip.
The first encapsulant includes an insulating resin, glass fiber, and an inorganic filler,
The second encapsulant includes an insulating resin and an inorganic filler,
The backside redistribution layer is disposed on the second encapsulant,
The backside redistribution layer and the redistribution layer of the second connection member are electrically connected to each other through backside vias passing through the first and second encapsulant.
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The method of claim 11,
A first passivation layer disposed on the first connection member and having a first opening that exposes at least a portion of the redistribution layer of the first connection member; And
A second passivation layer disposed on the second encapsulant and having a second opening that exposes at least a portion of the backside redistribution layer; Including more;
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Claim 13 was abandoned upon payment of a set-up fee. The method of claim 12,
The first passivation layer includes an insulating resin, glass fiber, and an inorganic filler,
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The method of claim 12,
The first and second passivation layers each include an insulating resin and an inorganic filler,
The weight percentage of the inorganic filler included in the first passivation layer is greater than the weight percentage of the inorganic filler included in the second passivation layer,
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Claim 15 was abandoned upon payment of a set-up fee. The method of claim 9,
The distance between the redistribution layer of the connection member and the first rewiring layer is greater than the distance between the redistribution layer of the connection member and the connection pad of the semiconductor chip.
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Claim 16 was abandoned upon payment of a set-up fee. The method of claim 1,
The core member includes a first insulating layer and a first wiring layer and a second wiring layer disposed on both surfaces of the first insulating layer,
The first and second rewiring layer is electrically connected to the connection pad of the semiconductor chip,
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Claim 17 was abandoned upon payment of a set-up fee. The method of claim 16,
The core member further includes a second insulating layer disposed on the first insulating layer and covering the first wiring layer, and a third wiring layer disposed on the second insulating layer,
The third rewiring layer is electrically connected to the connection pad of the semiconductor chip,
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Claim 18 was abandoned when the set registration fee was paid. The method of claim 17,
The core member further includes a third insulating layer disposed on the first insulating layer to cover the second wiring layer, and a fourth wiring layer disposed on the third insulating layer,
The fourth wiring layer is electrically connected to the connection pad of the semiconductor chip,
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Claim 19 was abandoned upon payment of a set-up fee. The method of claim 18,
A passivation layer disposed on the connection member and having an opening exposing at least a portion of the redistribution layer of the connection member; And
An under bump metal layer formed on the opening and connected to the redistribution layer of the exposed connection member; More,
The passivation layer includes an insulating resin, glass fiber, and an inorganic filler,
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delete delete delete Claim 23 has been abandoned upon payment of a set-up fee. The method of claim 17,
The first insulating layer is thicker than the second insulating layer,
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The method of claim 1,
A second encapsulant disposed on the first encapsulant; More,
The second encapsulant includes an insulating resin and an inorganic filler,
The first encapsulant has a larger elastic modulus than the second encapsulant,
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A core member having a through hole and having a first side and a second side opposite to the first side;
A semiconductor chip disposed in the through hole and having a first surface on which a connection pad is disposed and a second surface opposite to the first surface;
An encapsulant covering at least a portion of each of the second side of the core member and the second surface of the semiconductor chip and filling at least a portion between the wall surface of the through hole and the side surface of the semiconductor chip;
A connection member disposed on the first side of the core member and the first surface of the semiconductor chip; And
A passivation layer disposed on an opposite side of the side of the connection member where the core member and the semiconductor chip are disposed; Including;
The core member and the connection member each include a redistribution layer electrically connected to the connection pad of the semiconductor chip.
The passivation layer includes an insulating resin, glass fiber, and an inorganic filler,
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The method of claim 25,
The passivation layer has an opening that exposes at least a portion of the redistribution layer of the connection member,
On the opening is formed an under bump metal layer connected to the redistribution layer of the exposed connection member,
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The method of claim 26,
At least a portion of the surface on which the under bump metal layer of the passivation layer is formed is disposed a primer layer in contact with the under bump metal layer,
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delete Claim 29 was abandoned upon payment of a set-up fee. The method of claim 25,
The core member may include a first insulating layer in contact with the first insulating layer and the connection member and disposed on an opposite side of the side in which the first insulating layer of the first insulating layer is embedded. A second wiring layer, a second insulating layer disposed on the first insulating layer and covering the second wiring layer, and a third wiring layer disposed on the second insulating layer,
The first to third rewiring layer is electrically connected to the connection pad of the semiconductor chip,
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A semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposite to the first surface;
An encapsulant sealing at least a portion of the second surface of the semiconductor chip;
A first connection member disposed on the first surface of the semiconductor chip;
A first passivation layer disposed on the first connection member; And
A second connecting member having a through hole; Including;
The semiconductor chip is disposed in the through hole of the second connection member,
The first and second connection members each include a redistribution layer electrically connected to the connection pad of the semiconductor chip.
The first passivation layer includes an insulating resin, glass fiber, and an inorganic filler,
The backside redistribution layer is disposed on the encapsulant,
The backside redistribution layer and the redistribution layer of the second connection member are electrically connected to each other through a backside via penetrating the encapsulant.
Fan-out semiconductor package.
Claim 31 was abandoned upon payment of a set-up fee. The method of claim 25,
The core member may include a first insulating layer, a first wiring layer and a second wiring layer disposed on both surfaces of the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering the first wiring layer. A third wiring layer disposed on the second insulating layer, a third insulating layer disposed on the first insulating layer to cover the second wiring layer, and a fourth wiring layer disposed on the third insulating layer. ,,
The first to fourth rewiring layer is electrically connected to the connection pad of the semiconductor chip,
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Claim 32 was abandoned when the setup registration fee was paid. The method of claim 30,
A second passivation layer disposed on the encapsulant and having a second opening that exposes at least a portion of the backside redistribution layer; Including more;
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