KR101945334B1 - 창이 없는 와이어 본드 어셈블리를 위한 스터브 최소화 - Google Patents

창이 없는 와이어 본드 어셈블리를 위한 스터브 최소화 Download PDF

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KR101945334B1
KR101945334B1 KR1020147012045A KR20147012045A KR101945334B1 KR 101945334 B1 KR101945334 B1 KR 101945334B1 KR 1020147012045 A KR1020147012045 A KR 1020147012045A KR 20147012045 A KR20147012045 A KR 20147012045A KR 101945334 B1 KR101945334 B1 KR 101945334B1
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terminal
microelectronic
package
substrate
terminals
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KR20140085489A (ko
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리차드 드윗 크리스프
와엘 조니
벨가셈 하바
프랭크 람브레히트
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인벤사스 코포레이션
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
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    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
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    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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KR1020147012045A 2011-10-03 2012-10-01 창이 없는 와이어 본드 어셈블리를 위한 스터브 최소화 Active KR101945334B1 (ko)

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US201161542488P 2011-10-03 2011-10-03
US201161542553P 2011-10-03 2011-10-03
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US201261600271P 2012-02-17 2012-02-17
US61/600,271 2012-02-17
US13/440,313 US8405207B1 (en) 2011-10-03 2012-04-05 Stub minimization for wirebond assemblies without windows
US13/440,313 2012-04-05
PCT/US2012/058273 WO2013052411A1 (en) 2011-10-03 2012-10-01 Stub minimization for wirebond assemblies without windows

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WO2013052448A1 (en) 2013-04-11
EP2764545B1 (en) 2018-07-04
TWI491015B (zh) 2015-07-01
JP2015501532A (ja) 2015-01-15
EP2764545A1 (en) 2014-08-13
WO2013052411A4 (en) 2013-07-04
EP2766931A1 (en) 2014-08-20
JP5857129B2 (ja) 2016-02-10
TW201322415A (zh) 2013-06-01
TW201322417A (zh) 2013-06-01
TWI511264B (zh) 2015-12-01
JP5857130B2 (ja) 2016-02-10
KR101895017B1 (ko) 2018-10-04
EP2766931B1 (en) 2021-12-01
KR20140085489A (ko) 2014-07-07
JP2014534625A (ja) 2014-12-18
WO2013052411A1 (en) 2013-04-11
WO2013052441A2 (en) 2013-04-11
TW201324734A (zh) 2013-06-16
KR20140085490A (ko) 2014-07-07
TWI459537B (zh) 2014-11-01

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