KR101920770B1 - Organic light emitting display device and method of manufacturing the same - Google Patents

Abstract

In a display device according to the present invention, at least one of a data line, a low-voltage supply line, and a first high-voltage supply line is formed in the same mask process as the light-shielding layer , The storage upper electrode, and the source and drain electrodes are formed in the same mask process as the pad cover electrode, thereby simplifying the structure and manufacturing process.

Description

Technical Field [0001] The present invention relates to an organic light emitting diode (OLED) display device and a method of manufacturing the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display and a method of manufacturing the same, and more particularly, to an organic light emitting display and a method of manufacturing the same.

The image display device that realizes various information on the screen is a core technology of the information communication age and it is becoming thinner, lighter, more portable and higher performance. Examples of such display devices include a liquid crystal display (LCD) device, an organic light emitting diode (OLED) display device, and the like.

In order to manufacture such a display device, a mask process using a photomask is performed many times. Each mask process involves associated processes such as cleaning, exposure, development, and etching. Accordingly, every time one mask process is added, there is a problem that the manufacturing time and manufacturing cost for manufacturing the organic light emitting display device are increased, the defect incidence is increased, and the manufacturing yield is lowered. Therefore, it is required to simplify the structure and manufacturing process in order to reduce the production cost, improve the production yield and production efficiency.

It is an object of the present invention to provide an organic light emitting display device and a method of manufacturing the same that can simplify a structure and a manufacturing process.

In order to achieve the above object, at least one of a data line, a low-voltage supply line, and a first high-voltage supply line is formed by one mask process identical to the light-shielding layer in the organic light- The upper electrode, the source electrode, and the drain electrode are formed by the same mask process as the pad cover electrode, thereby simplifying the structure and manufacturing process.

An organic light emitting display according to the present invention includes a horizontal line including a gate line and a second high voltage supply line, and a vertical line including a data line, a low voltage supply line, and a first high voltage supply line. At this time, at least one of the data line, the low-voltage supply line, and the first high-voltage supply line included in the vertical line is formed by the same mask process as the light-shielding layer. The storage upper electrode, the source and drain electrodes are formed by the same mask process as the pad cover electrode. Accordingly, the organic light emitting diode display according to the present invention can reduce the number of mask processes at least once compared with the conventional one, thereby simplifying the structure and the manufacturing process, thereby improving the productivity.

1 is a plan view showing an organic light emitting diode display according to the present invention.
FIG. 2 is a cross-sectional view illustrating an organic light emitting display device taken along lines I-I ', II-II', III-III ', and IV-IV' in FIG.
3A and 3B are a plan view and a sectional view for explaining a first mask process according to the present invention.
4A and 4B are a plan view and a cross-sectional view for explaining a second mask process according to the present invention.
5A and 5B are a plan view and a cross-sectional view for explaining a third mask process according to the present invention.
6A and 6B are a plan view and a cross-sectional view for explaining a fourth mask process according to the present invention.
7A and 7B are a plan view and a cross-sectional view for explaining the fifth mask process according to the present invention.
8A and 8B are a plan view and a sectional view for explaining a sixth mask process according to the present invention.
9A and 9B are a plan view and a sectional view for explaining a seventh mask process according to the present invention.
10A and 10B are a plan view and a sectional view for explaining an eighth mask process according to the present invention.
11A and 11B are a plan view and a cross-sectional view for explaining the ninth mask process according to the present invention.
12A and 12B are a plan view and a cross-sectional view for illustrating a tenth mask process according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described.

FIG. 1 is a plan view showing an organic light emitting display according to the present invention, and FIG. 2 is a cross-sectional view illustrating the organic light emitting display shown in FIG.

The organic light emitting display shown in FIGS. 1 and 2 has an active region and a pad region.

The pad region is provided with a plurality of gate lines GL, a data line DL, a high voltage VDD supply lines VDL1 and VDL2, and a low voltage (VSS) supply line VSL, Pads 150 are formed.

Each of the plurality of pads 150 includes a pad electrode 152 and a pad cover electrode 154.

The pad electrode 152 is formed of the same material as the gate electrode 106 on the gate insulating pattern 112 having the same shape as the pad electrode 152.

The pad cover electrode 154 is electrically connected to the pad electrode 152 exposed through the first pad contact hole 156 passing through the interlayer insulating film 116. In addition, the pad cover electrode 154 is exposed to the outside and is in contact with the circuit transfer film connected to the driving circuit. At this time, the pad cover electrode 154 is made of a metal having high corrosion resistance and acid resistance on the interlayer insulating film 116 and can be prevented from being corroded by external moisture or the like even when exposed to the outside. For example, the pad cover electrode 154 is formed of the same material on the same plane as the source and drain electrodes 108 and 110. That is, the pad cover electrode 154 is made of a transparent conductive film such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) having high corrosion resistance and acid resistance.

The active area is an area where a plurality of sub-pixels are arranged in a matrix form to display an image. Each of the sub-pixels arranged in the active area has a pixel driving circuit arranged in the circuit area and a light emitting element 130 connected to the pixel driving circuit.

The pixel driving circuit includes a switching transistor T1, a driving transistor T2, and a storage capacitor Cst.

The switching transistor Tl is turned on when a scan pulse is supplied to the gate line GL to supply a data signal supplied to the data line DL to the gate electrode of the storage capacitor Cst and the driving transistor T2. The driving transistor T2 controls the current I supplied from the high voltage supply lines VDL1 and VDL2 to the light emitting element 130 in response to the data signal supplied to the gate electrode of the driving transistor T2, 130). Even if the switching transistor Tl is turned off, the driving transistor T2 supplies a constant current I until the data signal of the next frame is supplied by the voltage charged in the storage capacitor Cst, 130) maintains light emission.

To this end, the switching transistor T1 includes a first gate electrode 106, a first source electrode 108, a first drain electrode 110 and a first active layer 114 as shown in FIG. 1 . The driving transistor T2 includes a second gate electrode 206, a second source electrode 208, a second drain electrode 210, and a second active layer 214 as shown in FIGS. 1 and 2 . The switching transistor T1 and the driving transistor T2 have the same or different cross-sections. In the present invention, the switching transistor T1 and the driving transistor T2 have the same cross-sectional structure.

The first and second gate electrodes 106 and 206 are formed on the gate insulating pattern 112 in the same pattern as the gate electrodes 106 and 206. [ The gate electrodes 106 and 206 overlap the channel regions of the active layers 114 and 214 with the gate insulating pattern 112 therebetween. The gate electrodes 106 and 206 may be formed of any one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, But may be a single layer or a multilayer of these alloys, but is not limited thereto.

The first and second source electrodes 108 and 208 are connected to the source regions of the active layers 114 and 214 through the source contact holes 124S and 224S penetrating the interlayer insulating film 116. [ The first source electrode 108 of the switching transistor Tl is electrically connected to the data line DL exposed through the data contact hole 102 penetrating the buffer film 104 and the interlayer insulating film 116 .

The first and second drain electrodes 110 and 210 are connected to the drain regions of the active layers 114 and 214 through drain contact holes 124D and 224D penetrating the interlayer insulating layer 116. [ The second drain electrode 210 of the driving transistor is exposed through the pixel contact hole 120 formed to pass through the passivation layer 118 and the planarization layer 126 and is connected to the anode electrode 132.

The source electrodes 108 and 208 and the drain electrodes 110 and 210 are made of a transparent conductive film such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

The first and second active layers 114 and 214 have a source region and a drain region facing each other with a channel region therebetween. The channel region overlaps the gate electrodes 106 and 206 with the gate insulating pattern 112 interposed therebetween. The source region is connected to the source electrode 108 through the source contact holes 124S and 224S and the drain region is connected to the drain electrode 110 through the drain contact holes 124D and 224D. Each of the source region and the drain region is formed of a semiconductor material into which an n-type or p-type impurity is implanted, and the channel region is formed of a semiconductor material into which no n-type or p-type impurity is implanted.

A buffer film 104 and a light shielding layer 142 are formed between the active layers 114 and 214 and the substrate 101. A light shielding layer 142 is formed on the substrate 101 so as to overlap the channel region of the active layers 114 and 214. [ Since the light-shielding layer 142 absorbs or reflects light incident from the outside, the light incident on the channel region can be minimized. Here, the light-shielding layer 142 may be exposed through the light-shielding contact hole 146 and electrically connected to the second active layer 214 through the second drain electrode 210.

The light shielding layer 142 is formed by the same mask process as the data line DL, the low voltage supply line VSL, and the first high voltage supply line VDL1. That is, the light shielding layer 142 is formed of the same material on the same plane as the data line DL, the low voltage supply line VSL, and the first high voltage supply line VDL1. For example, the light-shielding layer 142 is formed of an opaque metal such as Mo, Ti, Al, Cu, Cr, Co, W, Ta, or Ni.

The buffer film 104 is formed as a single layer or a multilayer structure of silicon oxide or silicon nitride on a substrate 101 formed of a plastic resin such as glass or polyimide (PI). The buffer layer 104 functions to prevent the diffusion of moisture or impurities generated in the substrate 101 or to control the transfer rate of heat during crystallization so that the crystallization of the active layers 114 and 214 can be performed well.

Even if the switching transistor Tl is turned off by the voltage charged in the storage capacitor Cst, the driving transistor T2 supplies a constant current until the data signal of the next frame is supplied so that the light emission of the light emitting element 130 . The storage capacitor Cst is formed by overlapping the storage lower electrode 144 and the storage upper electrode 184 with the interlayer insulating film 116 interposed therebetween. The storage lower electrode 144 is made of an active layer doped with impurities and the storage upper electrode 184 is made of the same material as the second drain electrode 210 of the driving transistor.

The light emitting device 130 includes an anode electrode 132 connected to the drain electrode 210 of the driving transistor T2, an organic light emitting layer 134 formed on the anode electrode 132, And a cathode electrode 136.

The anode electrode 132 is disposed on the planarization layer 126 so as to overlap the light emitting region provided by the bank 138 and the circuit region in which the pixel driving circuit is disposed.

The anode electrode 132 is in contact with the second drain electrode 210 through the pixel contact hole 120 passing through the planarization layer 126 and the passivation layer 118.

The organic light-emitting layer 134 is formed on the anode electrode 132 in the order of the hole-related layer, the light-emitting layer, and the electron-related layer in the reverse order. When the organic light emitting layer 134 is applied to the organic light emitting display device of the top emission type, since the organic light emitting layer 134 is formed on the anode electrode 132 disposed in the light emitting region as well as the circuit region, the aperture ratio is improved.

The bank 138 is formed on the anode electrode 132 to provide a light emitting region. These banks 138 may be formed of an opaque material (e.g., black) to prevent optical interference between adjacent sub-pixels. In this case, the bank 138 includes a light shielding material made of at least one of color pigment, organic black, and carbon.

The organic light emitting layer 134 is separated from the organic light emitting layer 134 through barrier ribs 148, which are disposed in adjacent sub-pixels that emit different colors from the organic light emitting layer 134. That is, the barrier ribs 148 are disposed in the bank holes 174 overlapping the third auxiliary connection electrodes 168 in a reverse tapered shape whose width gradually increases from the lower surface to the upper surface. Accordingly, since the organic emission layer 134 formed in a straight line is not formed on the third auxiliary connection electrode 168 overlapping the barrier ribs 148, the barrier ribs 148 prevent the adjacent sub- The organic light emitting layers 134 are separated in the bank holes 174. In this case, the organic light emitting layer 134 is formed on the remaining region except for the third auxiliary connection electrode 168 exposed by the bank hole 174, so that the organic light emitting layer 134 is electrically connected to the anode 138 exposed by the bank 138, The upper surface of the electrode 132, the upper surface of the barrier ribs 148, and the upper surface and side surfaces of the banks 138. On the other hand, since the cathode electrode 136 having a better step coverage than the organic light emitting layer 134 is formed on the upper surface and the side surface of the barrier rib 148 and on the side surface of the bank 138 disposed under the barrier rib 148, Contact with the auxiliary connecting electrode 168 is facilitated.

The cathode electrode 136 is formed on the upper surface and side surfaces of the organic light emitting layer 134 and the bank 138 so as to face the anode electrode 132 with the organic light emitting layer 134 therebetween. The cathode electrode 136 is formed of a transparent conductive film such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) when applied to a top emission type OLED display.

The cathode electrode 136 is connected to the low voltage supply line 160 through the first to third auxiliary connection electrodes 162, 164 and 168 in the bank hole 174 where the barrier rib 148 is located. The first auxiliary connecting electrode 162 is formed of the same material as the low voltage supply line VSL on the substrate 101 and is formed extending from the low voltage supply line VSL.

The second auxiliary connection electrode 164 is electrically connected to the first auxiliary connection electrode 162 exposed through the first auxiliary contact hole 166 passing through the buffer film 104 and the interlayer insulating film 116. The second auxiliary connection electrode 164 is made of the same material on the same plane as the source and drain electrodes 108, 208, 110 and 210.

The third auxiliary connection electrode 168 is electrically connected to the second auxiliary connection electrode 164 exposed through the protective film 118 and the second auxiliary contact hole 170 penetrating the planarization layer 128. The third auxiliary connection electrode 168 is made of the same material on the same plane as the anode electrode 132.

Since the first and third auxiliary connection electrodes 162 and 168 and the low voltage supply line VSL are formed of a metal having a conductivity higher than that of the cathode electrode 136, the high and low voltage of the cathode electrode 136 formed of ITO or IZO, The resistance component may be compensated.

As described above, the OLED display according to the present invention includes a horizontal line including a gate line GL and a second high-voltage supply line VDL2, a data line DL, a low-voltage supply line VSL, and a first high- And a vertical line including a line VDL1. At this time, at least one of the data line DL, the low-voltage supply line VSL and the first high-voltage supply line VDL1 included in the vertical line is formed by the same mask process as the light-shielding layer 142. The storage upper electrode 184 and the source and drain electrodes 108, 208, 110 and 210 are formed by the same mask process as the pad cover electrode 154. Accordingly, the organic light emitting diode display according to the present invention can reduce the number of mask processes at least once compared with the conventional one, thereby simplifying the structure and the manufacturing process, thereby improving the productivity.

FIGS. 3A to 12B are plan views and sectional views for explaining a method of manufacturing the organic light emitting display shown in FIGS. 1 and 2. FIG.

3A and 3B, a light shielding layer 142, a first auxiliary connection electrode 162, a data line DL, a first high voltage supply line VDL1, and a low voltage supply line VSL Is formed.

Specifically, an opaque first conductive layer is formed on the substrate 101 through a deposition process. Then, the opaque first conductive layer is patterned through the photolithography process and the etching process using the first mask to form the light shielding layer 142, the first auxiliary connecting electrode 162, the data line DL, the first high- A line VDL1 and a low-voltage supply line VSL are formed.

4A and 4B, a substrate 101 having a light shielding layer 142, a first auxiliary connection electrode 162, a data line DL, a first high voltage supply line VDL1, and a low voltage supply line VSL is formed. The buffer layer 104 is formed on the buffer layer 104 and the first and second active layers 114 and 214 and the storage lower electrode 144 are formed.

Specifically, an inorganic insulating material such as SiOx or SiNx is entirely deposited on the substrate 101 to form a single-layer or multi-layered buffer film 104. [ Then, an amorphous silicon thin film is formed on the substrate 101 on which the buffer film 104 is formed by a method such as LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition). Then, the amorphous silicon thin film is crystallized to form a polysilicon thin film. Then, the first and second active layers 114 and 214 and the storage lower electrode 144 are formed by patterning the polysilicon thin film by a photolithography process and an etching process using a second mask.

5A and 5B, a gate insulating pattern 112 and a gate insulating pattern 112 are formed on a buffer film 104 on which first and second active layers 114 and 214 and a storage lower electrode 144 are formed. A gate line GL, a second high-voltage supply line VDL2, first and second gate electrodes 106 and 206, and a pad electrode 152 are formed.

Specifically, a gate insulating film is formed on the buffer film 104 on which the active layers 114 and 214 and the storage lower electrode 144 are formed, and a second conductive layer is formed thereon by a deposition method such as sputtering. As the gate insulating film, an inorganic insulating material such as SiOx or SiNx is used. As the second conductive layer, a metal material such as Mo, Ti, Cu, AlNd, Al, or Cr or an alloy thereof may be used as a single layer, or may be used in a multi-layer structure using them. Then, the second conductive layer and the gate insulating film are simultaneously patterned through the photolithography process and the etching process using the third mask to form the gate line GL, the second high-voltage supply line VDL2, the first and second gate electrodes 106, and 206, and the pad electrode 152, and a gate insulator pattern 112 are formed in the lower part of the pad electrode 152 in the same pattern.

The active layers 114 and 214 are formed by implanting n + -type or p + -type impurities into the storage lower electrode 144 and the first and second active layers 114 and 214 using the first and second gate electrodes 106 and 206 as masks. The source regions 114S and 214S and the drain regions 114D and 214D are formed.

6A and 6B, on the substrate 101 on which the gate line GL, the second high voltage supply line VDL2, the first and second gate electrodes 106 and 206 and the pad electrode 152 are formed, An interlayer insulating film 116 having drain contact holes 124S, 124D, 224S, and 224D, a data contact hole 102, a light shielding contact hole 146, a first auxiliary contact hole 166, and a first pad contact hole 156 Is formed.

Specifically, an interlayer insulating film 116 is formed on the substrate 101 on which the gate electrode 106, the storage lower electrode 144, and the first pad electrode 152 are formed by a deposition method such as PECVD. Then, the interlayer insulating film 116 and the buffer film 104 are selectively patterned through the photolithography process and the etching process using the third mask, thereby forming the source and drain contact holes 124S, 224S, 124D, and 224D, A first auxiliary contact hole 146, a first auxiliary contact hole 166, and a first pad contact hole 156 are formed. Each of the source and drain contact holes 124S, 224S, 124D and 224D and the first pad contact hole 156 is formed to penetrate the interlayer insulating layer 116 to form the source electrode 108, the drain electrode 110, The electrode 152 is exposed. The data contact hole 102, the light shielding contact hole 146 and the first auxiliary contact hole 166 are formed to penetrate the buffer film 104 and the interlayer insulating film 116, respectively, so that the light shielding layer 142 and the first auxiliary connection The electrode 162 is exposed. The source and drain contact holes 124S, 224S, 124D and 224D, the data contact hole 102, the light shield contact hole 146, the first auxiliary contact hole 166 and the first pad contact hole 156 are the same Although the mask process is described as an example, other mask processes may be used. That is, the source and drain contact holes 124S, 224S, 124D, and 224D and the first pad contact hole 156 that penetrate the interlayer insulating layer 116 are formed first, and then the interlayer insulating layer 116 and the buffer The data contact hole 102, the light shielding contact hole 146, and the first auxiliary contact hole 166, which pass through the film 104, may be formed.

7A and 7B, the source and drain contact holes 124S, 224S, 124D and 224D, the light shielding contact hole 146, the first auxiliary contact hole 166 and the first pad contact hole 156 The first and second source electrodes 108 and 208, the first and second drain electrodes 110 and 210, the storage upper electrode 148, the pad cover electrode 154, the second auxiliary connection electrode 164 Is formed.

Specifically, a third conductive layer is formed on the interlayer insulating film 116 by a deposition method such as sputtering. As the third conductive layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof may be used as a single layer, or may be used in a multi-layer structure using them. Then, the third conductive layer is patterned through a photolithography process and an etching process to form first and second source electrodes 108 and 208, first and second drain electrodes 110 and 210, A pad cover electrode 154, and a second auxiliary connection electrode 164 are formed.

8A and 8B, the first and second source electrodes 108 and 208, the first and second drain electrodes 110 and 210, the storage upper electrode 148, the pad cover electrode 154, A passivation layer 118 having a pixel contact hole 120 and a second auxiliary contact hole 170 and a planarization layer 126 are formed on a substrate 101 on which a first insulating layer 164 is formed.

More specifically, a substrate having the first and second source electrodes 108 and 208, the first and second drain electrodes 110 and 210, the storage upper electrode 148, the pad cover electrode 154, An inorganic insulating material such as SiOx, SiNx, or the like is deposited on the entire surface of the substrate 101 to form the protective film 118. Then, the planarization layer 126 is formed by entirely stacking an organic insulating material such as an acrylic resin on the protective film 118. Then, the pixel contact hole 120 and the second auxiliary contact hole 170 are formed by patterning the passivation layer 118 and the planarization layer 126 through the photolithography process and the etching process.

9A and 9B, an anode electrode 132 and a third auxiliary connection electrode 140 are formed on a substrate 101 on which a planarization layer 126 having a pixel contact hole 120 and a second auxiliary contact hole 170 is formed. (Not shown).

Specifically, the fourth conductive layer is entirely deposited on the substrate 101 on which the planarization layer 126 having the pixel contact hole 120 and the second auxiliary contact hole 170 is formed. As the fourth conductive layer, a transparent conductive film and an opaque conductive film are used. Then, the fourth conductive layer is patterned through the photolithography process and the etching process, thereby forming the anode electrode 132 and the third auxiliary connecting electrode 168. The pad cover electrode 154 having the same etching characteristic as that of the fourth conductive layer during the etching of the fourth conductive layer is protected by the protective film 118 and the planarization layer 126 so that the pad cover electrode 154 is prevented from being damaged can do.

10A and 10B, a bank 138 is formed on a substrate 101 on which an anode electrode 132 and a third auxiliary connection electrode 168 are formed.

Specifically, the photoresist film for the bank is entirely coated on the substrate 101 on which the anode electrode 132 and the third auxiliary connection electrode 168 are formed. Then, the photoresist film for the bank is patterned through the photolithography process, thereby forming the bank 138 exposing the anode electrode 132 and the third auxiliary connection electrode 168.

11A and 11B, a second pad contact hole 158 exposing the pad cover electrode 154 is formed on the substrate 101 on which the bank 138 is formed.

Specifically, a photoresist pattern (not shown) is formed on the substrate 101 on which the banks 138 are formed through a photolithography process. A second pad contact hole 158 exposing the pad cover electrode 154 by removing the planarization layer 126 and the protection film 118 on the pad cover electrode 154 through the etching process using the template resist pattern as a mask .

12A and 12B, a barrier rib 148, an organic light emitting stack 134, and a cathode electrode 136 are sequentially formed on a substrate 101 on which a second pad contact hole 158 is formed.

Specifically, the barrier ribs 148 are formed by coating the entire surface of the substrate 101 on which the second pad contact holes 158 are formed, and then patterning the photosensitive film for the barrier ribs through a photolithography process. Then, a light emitting stack 134 and a cathode electrode 136 are sequentially formed in an active region except a pad region through a deposition process using a shadow mask.

The signal line including the data line DL, the low-voltage supply line VSL and the high-voltage supply line VDL1 is formed in the same mask process as the light-shielding layer 142, and the storage upper electrode 184 and the source and drain electrodes 108, 208, 110, and 210 are formed in the same mask process as the pad cover electrode 154. Accordingly, the organic light emitting diode display according to the present invention can reduce the number of mask processes at least once compared with the conventional one, thereby simplifying the structure and the manufacturing process, thereby improving the productivity.

In the present invention, each pixel driving circuit includes a switching transistor and a driving transistor. Alternatively, the pixel driving circuit may further include a sensing transistor for sensing a threshold voltage of the driving transistor TD. In this case, since the reference line connected to the source electrode of the sensing transistor is also formed by the same mask process as that of the light shielding layer 142, the reference line is made of the same material on the same plane as the light shielding layer 142. This reference line is connected to a source electrode of a sensing transistor made of a transparent conductive film through a contact hole passing through the buffer film 104 and the interlayer insulating film 116.

In addition, when the organic light emitting diode display according to the present invention is a front light emitting structure, the color filter array may further include a color filter array formed on the second substrate. In this case, the white light generated by the light emitting device is emitted to the front surface of the second substrate through the color filter, thereby realizing an image.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

101: substrate 126: planarization layer
132: anode electrode 134: light emitting layer
136: cathode electrode 138: bank
142: Shading layer 152: Pad electrode
154: pad cover electrode

Claims (12)

A plurality of signal lines disposed on the substrate;
An organic light emitting diode disposed in a pixel region provided at an intersection of the plurality of signal lines;
A pixel driving circuit including a driving transistor connected to the organic light emitting element and a switching transistor connected to the driving transistor;
A light shielding layer overlapping the driving transistor and the switching transistor;
A pad electrode connected to each of the plurality of signal lines;
A pad cover electrode connected to the pad electrode on the pad electrode;
And an auxiliary connection electrode electrically connected to the cathode electrode of the organic light emitting diode,
At least one signal line among the plurality of signal lines is made of the same material on the same plane as the light-shielding layer,
Wherein the auxiliary connection electrode is disposed on the same plane as the pad cover electrode and the source and drain electrodes of the driving transistor. The method according to claim 1,
The plurality of signal lines
A data line connected to a source electrode of the switching transistor;
A high voltage supply line connected to a source electrode of the driving transistor;
And a low voltage supply line connected to the organic light emitting element,
Wherein at least one of the data line, the high-voltage supply line, and the low-voltage supply line is disposed on the substrate with the same material as the light-shielding layer. delete The method according to claim 1,
Wherein the pad cover electrode is made of ITO or IZO. 3. The method of claim 2,
A plurality of insulating layers disposed on the data lines;
Further comprising data contact holes passing through the plurality of insulating layers,
And the data line is connected to the source electrode through the data contact hole. Forming a light-shielding layer, a plurality of signal lines, and a pad electrode connected to each of the plurality of signal lines on the substrate;
A pixel driving circuit including a driving transistor and a switching transistor which are overlapped with the light shielding layer, a pad cover electrode connected to the pad electrode on the pad electrode, and an auxiliary connection electrode;
Forming an organic light emitting element connected to the pixel driving circuit,
At least one signal line among the plurality of signal lines is made of the same material on the same plane as the light-shielding layer,
Wherein the auxiliary connection electrode electrically connected to the cathode electrode of the organic light emitting diode is disposed on the same plane as the source electrode and the drain electrode of the pad cover electrode and the driving transistor. The method according to claim 6,
The step of forming the plurality of signal lines
A data line connected to a source electrode of the switching transistor; a high voltage supply line connected to a source electrode of the driving transistor; and a low voltage supply line connected to the organic light emitting element,
Wherein at least one of the data line, the high-voltage supply line, and the low-voltage supply line is disposed on the substrate with the same material as the light-shielding layer. delete The method according to claim 6,
Wherein the pad cover electrode is made of ITO or IZO. 8. The method of claim 7,
Forming a plurality of insulating layers disposed on the data lines;
Further comprising forming a data contact hole through the plurality of insulating layers,
And the data line is connected to the source electrode through the data contact hole. The method according to claim 1,
A storage lower electrode disposed on the same plane as the active layer of the driving transistor;
And a storage upper electrode disposed on the same plane as the source and drain electrodes of the driving transistor. The method according to claim 6,
Forming a storage lower electrode disposed on the same plane as the active layer of the driving transistor;
Further comprising forming a storage upper electrode disposed on the same plane as the source and drain electrodes of the driving transistor.

Images