KR102178471B1 - Large Area Transparent Organic Light Emitting Diode Display - Google Patents

Abstract

The present invention relates to a large area and/or a transparent transparent organic light emitting diode display. The organic light emitting diode display according to the present invention includes a light blocking layer and an auxiliary cathode electrode, a thin film transistor, a planarization film, an anode electrode, a connection terminal, a bank, an organic light emitting layer, and a cathode electrode disposed on a substrate. The thin film transistor is disposed over the light blocking layer. The planarization film covers the thin film transistor and the auxiliary cathode. The anode electrode is connected to the thin film transistor on the planarization film. The connection terminal is connected to the auxiliary cathode on the planarization film. The bank exposes the central surface of the anode electrode and the entire connection terminal. The organic light emitting layer is stacked on the central surface of the anode electrode and the upper surface of the connection terminal, and exposes the etched sidewall of the connection terminal. In addition, the cathode electrode is stacked on the organic light emitting layer and contacts the etched sidewall of the connection terminal.

Description

Large Area Transparent Organic Light Emitting Diode Display

The present invention relates to a large area and/or a transparent transparent organic light emitting diode display. In particular, the present invention relates to a transparent organic light emitting diode display having an auxiliary cathode electrode for lowering the surface resistance of the cathode electrode, and a partition wall configured to directly connect the auxiliary cathode electrode and the cathode electrode.

Recently, various flat panel display devices capable of reducing the weight and volume, which are the disadvantages of a cathode ray tube, have been developed. Such flat panel displays include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Electro-Luminescence device (EL). Etc.

1 is a plan view showing the structure of an organic light emitting diode display (OLED) using a thin film transistor as an active device according to the prior art. FIG. 2 is a cross-sectional view taken along line I-I' in FIG. 1 and is a cross-sectional view illustrating the structure of an organic light emitting diode display according to the prior art.

Referring to FIGS. 1 and 2, a typical organic light emitting diode display is a thin film transistor substrate, a thin film transistor substrate on which an organic light emitting diode (OLED) driven by being connected to a thin film transistor (ST, DT) and a thin film transistor (ST, DT) is formed. It includes a cap (TS) facing and bonding the organic bonding layer (FS) therebetween. The thin film transistor substrate includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor ST, and an organic light emitting diode OLE connected to the driving thin film transistor DT.

The switching thin film transistor ST is formed on a transparent substrate SUB such as glass at a portion where the scan line SL and the data line DL intersect. The switching thin film transistor ST serves to select a pixel. The switching thin film transistor ST includes a gate electrode SG branching from the scan line SL, a semiconductor layer SA, a source electrode SS, and a drain electrode SD. In addition, the driving thin film transistor DT serves to drive the anode electrode ANO of the pixel selected by the switching thin film transistor ST. The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DA, a source electrode DS connected to the driving current line VDD, and a drain. It includes an electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE.

In FIG. 2, as an example, a thin film transistor having a top gate structure is shown. In this case, the semiconductor layer SA of the switching thin film transistor ST and the semiconductor layer DA of the driving thin film transistor DT are first formed on the substrate SUB, and the gate electrode is formed on the gate insulating layer GI covering the substrate SUB. The fields SG and DG are formed by overlapping the centers of the semiconductor layers SA and DA. In addition, source electrodes SS and DS and drain electrodes SD and DD are connected to both side surfaces of the semiconductor layers SA and DA through contact holes. The source electrodes SS and DS and the drain electrodes SD and DD are formed on the insulating layer IN covering the gate electrodes SG and DG.

In addition, on the outer periphery of the display area in which the pixel area is arranged, a gate pad GP formed at one end of each scan line SL, a data pad DP formed at one end of each data line DL, and each drive A driving current pad VDP formed at one end of the current line VDD is disposed. A protective film PAS is entirely coated on the substrate SUB on which the switching thin film transistor ST and the driving thin film transistor DT are formed. In addition, contact holes exposing the gate pad GP, the data pad DP, the driving current pad VDP, and the drain electrode DD of the driving thin film transistor DT are formed. In addition, a planarization layer PL is applied on the display area of the substrate SUB. The planarization film PL functions to make the roughness of the substrate surface uniform in order to apply the organic material constituting the organic light emitting diode OLE in a smooth plane state.

An anode electrode ANO contacting the drain electrode DD of the driving thin film transistor DT is formed on the planarization layer PL through a contact hole. In addition, even at the outer periphery of the display area where the planarization layer PL is not formed, the gate pad GP, the data pad DP, and the gate formed on the driving current pad VDP exposed through the contact holes formed in the passivation layer PAS. A pad terminal GPT, a data pad terminal DPT, and a driving current pad terminal VDPT are formed, respectively. In the display area, in particular, the bank BA is formed on the substrate SUB excluding the pixel area.

An organic light emitting layer OL is applied on the bank BA and the anode electrode ANO exposed through the bank BA. In addition, the cathode electrode CAT is applied on the organic light emitting layer OL. As a result, an organic light emitting diode OLE having a structure in which the anode electrode ANO, the organic light emitting layer OL, and the cathode electrode CAT are stacked is completed.

A cap TS maintaining a predetermined distance is attached to the thin film transistor substrate SUB having the above structure. In this case, it is preferable that the thin film transistor substrate SUB and the cap TS have an organic bonding layer FS interposed therebetween so that the thin film transistor substrate SUB and the cap TS are completely sealed and bonded while maintaining a constant distance. The organic bonding layer FS faces and seals the thin film transistor substrate SUB and the cap TS to each other to prevent moisture and gas from penetrating from the outside. The gate pad GP, the gate pad terminal GPT, the data pad DP and the data pad terminal DPT are exposed to the outside of the cap TS, and are connected to external devices through various connection means.

Also, a black matrix BM formed in a non-emission area and a color filter CF formed in the emission area may be further included on the inner surface of the cap TS. In particular, when the organic light-emitting layer OL emits white light, red (R)-green (G)-blue (B) colors may be implemented using a color filter CF.

In the organic light emitting diode display having such a structure, a cathode electrode CAT having a basic voltage is applied over the entire surface of a substrate of the display panel. When the cathode electrode CAT is formed of a metal material having a low specific resistance value, there is no problem, but when the cathode electrode CAT is formed of a transparent conductive material to secure transmittance, a problem may occur in image quality due to increased surface resistance.

For example, when a transparent conductive material or indium-tin oxide or indium-zinc oxide, which is a material having a higher specific resistance than a metal, is included in the cathode electrode CAT, the sheet resistance increases. Then, a problem occurs in that the cathode electrode CAT does not have a constant voltage value over the entire area of the display panel. In particular, when developing a large-area organic light-emitting diode display, a phenomenon in which the luminance of the display device is uneven across the entire screen may emerge as a more important problem.

Further, in the case of the top emission type, an auxiliary cathode electrode may be further provided to lower the sheet resistance of the cathode electrode CAT. The auxiliary cathode electrode is preferably formed of a metal material having a low specific resistance value. Since the organic light emitting layer OL is first applied under the cathode electrode CAT, it is not easy to directly connect the cathode electrode CAT and the auxiliary cathode electrode. In the related art, a part of the organic light-emitting layer OL is removed by further using a mask process, or a screen mask is used to prevent the organic light-emitting layer OL from being applied to a partial area on the auxiliary cathode electrode. However, in this prior art, the number of mask processes is further increased. Accordingly, there is a need to develop a manufacturing process for forming an auxiliary cathode electrode for lowering the resistance of the cathode electrode without increasing the number of mask processes, and a structure of an organic light emitting diode display device using the process.

An object of the present invention is an invention conceived to solve the problems of the prior art, and a transparent and/or large area organic light emitting diode display device having high quality display quality by lowering the surface resistance by directly contacting the cathode electrode and the auxiliary cathode electrode To provide. Another object of the present invention is to provide a large-area transparent and/or large-area organic light-emitting diode display that can simplify a manufacturing process while having an auxiliary cathode electrode.

In order to achieve the above object, the organic light emitting diode display device according to the present invention includes a light blocking layer and an auxiliary cathode electrode, a thin film transistor, a planarization film, an anode electrode, a connection terminal, a bank, an organic light emitting layer, and a cathode electrode disposed on a substrate. Includes. The thin film transistor is disposed over the light blocking layer. The planarization film covers the thin film transistor and the auxiliary cathode. The anode electrode is connected to the thin film transistor on the planarization film. The connection terminal is connected to the auxiliary cathode on the planarization film. The bank exposes the central surface of the anode electrode and the entire connection terminal. The organic light emitting layer is stacked on the central surface of the anode electrode and the upper surface of the connection terminal, and exposes the etched sidewall of the connection terminal. In addition, the cathode electrode is stacked on the organic light emitting layer and contacts the etched sidewall of the connection terminal.

As an example, the anode electrode and the connection terminal include a first transparent layer and a second transparent layer. The first transparent layer is disposed on the lower layer and the upper layer, respectively. And the second transparent layer is disposed in the center layer between the lower layer and the upper layer.

For example, the second transparent layer is over-etched than the first transparent layer, so that the center layer is concave and the lower and upper layers are convex.

For example, the lower layer has a positive taper shape with an etch taper angle of less than 30 degrees, and the upper layer has an inverse taper shape with an etch taper angle of less than 30 degrees.

For example, the first transparent layer and the second transparent layer include any one of indium oxide, zinc oxide, and tin oxide, and an etch rate of the second transparent layer includes a material that is faster than that of the first transparent layer.

The organic light-emitting diode display according to the present invention provides a transparent and/or large-area organic light-emitting diode display in which an auxiliary cathode electrode is formed by using a blocking layer for protecting a metal oxide semiconductor material from external light. Have. Therefore, it is possible to form the auxiliary cathode electrode without an additional mask process. In addition, the connection terminal connecting the auxiliary cathode electrode and the cathode electrode has a failure shape in which the central portion of the etching cross-section is concave, so that the organic light-emitting layer exposes the side surface of the connection terminal and the cathode electrode is formed to contact the side surface of the connection terminal. . Accordingly, it is possible to electrically connect the auxiliary cathode electrode and the cathode electrode without an additional mask process. The present invention has a structure capable of reducing the resistance of a cathode electrode, thereby providing a large area and/or a transparent organic light emitting diode display. In addition, by reducing the number of mask processes, manufacturing time can be shortened and manufacturing cost can be reduced.

1 is a plan view showing the structure of an organic light emitting diode display using a thin film transistor as an active device according to the prior art.
FIG. 2 is a cross-sectional view showing the structure of an organic light emitting diode display according to the prior art, taken along line I-I' in FIG. 1;
3 is a plan view showing the structure of an organic light emitting diode display according to the present invention.
4 is a cross-sectional view taken along line II-II' in FIG. 3 and showing the structure of an organic light emitting diode display according to the present invention.
5A to 5J are cross-sectional views illustrating a manufacturing process of the organic light emitting diode display device according to the present invention, cut by a cut line II-II' in FIG. 3

Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of preparation of the specification, and may be different from the names of parts of an actual product.

Hereinafter, the overall structure of the organic light emitting diode display according to the present invention will be described with reference to FIGS. 3 and 4. 3 is a plan view showing the structure of an organic light emitting diode display according to the present invention. 4 is a cross-sectional view taken along line II-II' in FIG. 3, and is a cross-sectional view showing the structure of an organic light emitting diode display according to the present invention.

Referring to FIG. 3, a thin film transistor substrate of an organic light emitting diode display according to the present invention includes a plurality of scan lines SL arranged on a substrate SUB in a horizontal direction, and a plurality of data lines DL arranged in a vertical direction. ) And a driving current line VDD arranged parallel to the data line DL. A plurality of pixel areas having a quadrangular shape are defined by a structure in which the scan line SL, the data line DL, and the driving current line VDD intersect.

An organic light emitting diode OLE is disposed in the pixel area to define a light emitting area through which light is emitted. The emission area is determined by the anode electrode ANO of the organic light emitting diode OLE. A thin film transistor region TA in which thin film transistors ST and DT for driving the anode electrode ANO are disposed is defined on one side of the pixel region. A portion of the pixel area excluding the emission area is defined as a non-emission area. For example, a portion of the anode electrode ANO in which the organic light emitting diode OLE is formed may be defined as an emission area, and all other areas may be defined as a non-emission area.

The organic light emitting diode display according to the present invention is mainly related to the top emission type, and further includes an auxiliary cathode electrode AC for lowering the surface resistance of the cathode electrode CAT. For example, it is first formed on the substrate SUB and is disposed under the thin film transistors ST and DT, and is disposed in the non-emission area using the light-shielding layer LS to protect semiconductor elements from inflow of external light. And further includes an auxiliary cathode electrode AC disposed over the entire substrate SUB.

The cathode electrode CAT is connected to the auxiliary cathode electrode AC through the connection terminal CT. In addition, since the auxiliary cathode electrode AC is formed on the lowermost layer and the connection terminal CT is formed at the same time when the anode electrode ANO is formed, the connection may not be smooth. In order to compensate for this case, the connection terminal CT may be connected to the auxiliary cathode electrode AC through the intermediate connection terminal CC. Hereinafter, the structure of the organic light emitting diode display device according to the present invention will be described in more detail with reference to FIG. 5 showing a cross-sectional structure.

3 and 4, the organic light emitting diode display device according to the present invention includes a thin film transistor substrate on which an organic light emitting diode (OLE) driven by being connected to the thin film transistors ST and DT and the thin film transistors ST and DT is formed. SUB) and a cap TS that faces the thin film transistor substrate SUB and bonds the organic junction layer FS therebetween. The thin film transistor substrate SUB includes a pixel region defined by a scan line SL, a data line DL, and a driving current line VDD.

In the pixel region defined on the thin film transistor substrate SUB, the switching thin film transistor ST, the driving thin film transistor DT connected to the switching thin film transistor ST, and the organic light emitting diode OLE connected to the driving thin film transistor DT. ). Although the description of the present invention focuses on the top-gate structure, all other structures of thin film transistors can be applied.

The switching thin film transistor ST serves to select a pixel. The driving thin film transistor DT serves to drive the anode electrode ANO allocated to the pixel region selected by the switching thin film transistor ST. The driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE.

The light blocking layer LS is formed on the substrate SUB. The light blocking layer LS is formed in advance at positions where the thin film transistors ST and DT are to be formed, and prevents the channel regions of the thin film transistors ST and DT from deteriorating due to penetration of external light. The light blocking layer LS can be used for other purposes in addition to the light blocking function.

In the present invention, it will be described as a case where it is formed of an opaque metal material and used as an auxiliary cathode electrode (AC). Accordingly, the light blocking layer LS may be formed over most of the non-emission area in addition to the area overlapping the thin film transistors ST and DT, thereby forming a body with the auxiliary cathode electrode AC. In FIG. 3, for convenience, the auxiliary cathode electrode AC is illustrated in the form of a wiring arranged parallel to the data line DL on the outer side of the substrate SUB. However, the auxiliary cathode electrode AC and the light blocking layer LS forming one body also perform the function of the auxiliary cathode AC.

A buffer layer BUF is formed on the light blocking layer LS and the auxiliary cathode electrode AC. In the present invention, the buffer layer BUF does not cover the entire substrate SUB, and is formed in the same shape as the light blocking layer LS and the auxiliary cathode electrode AC. This is a manufacturing process that reduces the number of mask processes, and the detailed description will be further described when describing the manufacturing method.

Several constituent elements for a display function are formed on the light blocking layer LS. For example, a switching thin film transistor ST, a driving thin film transistor DT, a data line DL, a driving current line VDD, a scan line SL, and the like are formed. A planarization film PAC is applied on the thin film transistor substrate SUB on which these components are formed.

An anode electrode ANO and a connection terminal CT are formed on the planarization layer PL. The anode electrode ANO is connected to the driving thin film transistor DT through a pixel contact hole PH penetrating through the planarization layer PL. The connection terminal CT is formed of the same material as the anode electrode ANO on the same layer, but is electrically and physically separated. The connection terminal CT is connected to the auxiliary cathode AC through the cathode contact hole CH. More specifically, the auxiliary cathode electrode AC may be first connected to the intermediate connection terminal CC. In this case, the connection terminal CT is connected to the intermediate connection terminal CC through the cathode contact hole CH.

A bank BA having an opening area exposing a light emitting area is formed on the anode electrode ANO and the connection terminal CT. At the same time, it is preferable that the bank BA further has an opening area exposing the entire connection terminal CT. For example, the bank BA is formed to have a smaller size than the anode electrode ANO so as to expose most of the central portion of the anode electrode ANO. On the other hand, the opening area exposing the connection terminal CT is formed to have a larger size than the connection terminal CT. In FIG. 3, the boundary of the bank is indicated by a dotted line.

The organic light-emitting layer OL is coated on the bank BN, the anode electrode ANO, and the connection terminal CT so as to cover the entire substrate SUB. An organic light emitting layer OL is deposited on the upper surface exposed by the bank BN in the anode electrode ANO. In addition, an organic light emitting layer OL is also stacked on the upper surface of the connection terminal CT. However, the sidewall of the connection terminal CT does not contact the organic emission layer OL.

In more detail, the organic light-emitting layer OL is applied inside the opening area of the bank BN where the connection terminal CT is exposed, but the planarization layer PAC is separated by a predetermined distance from the edge of the connection terminal CT. It is applied only to the surface. That is, the sidewalls etched from the edge of the connection terminal CT are exposed by the organic light emitting layer OL, without being covered or contacted.

The cathode electrode CAT is applied on the organic light-emitting layer OL to cover the entire surface of the substrate SUB. In the opening area exposing the light-emitting area, the cathode electrode CAT overlaps the anode electrode ANO with the organic light-emitting layer OL interposed therebetween. Accordingly, the organic light emitting diode OLE in which the organic light emitting layer OL emits light due to the voltage difference between the anode electrode ANO and the cathode electrode CAT is completed.

Meanwhile, in the opening region in which the connection terminal CT is formed, the cathode electrode CAT has a structure in which the cathode electrode CAT contacts the sidewall etched from the edge of the connection terminal CT. Accordingly, the cathode electrode CAT and the connection terminal CT are electrically and physically connected. Accordingly, the cathode electrode CAT is electrically connected to the auxiliary cathode electrode AC through the connection terminal CT. More specifically, the cathode electrode CAT is electrically connected to the auxiliary cathode electrode AC through the connection terminal CT and the intermediate connection terminal CC.

In this way, the etched sidewall of the connection terminal CT selectively does not contact the organic light-emitting layer OL and can contact the cathode electrode CAT due to the shape structure of the connection terminal CT. will be. In detail, the connection terminal CT has a structure in which three transparent conductive layers are stacked. For example, a first transparent layer IT, a second transparent layer IG, and a first transparent layer IT may be sequentially stacked. Here, it is preferable that the first transparent layer IT and the second transparent layer IT have different etch rates for the same etchant.

Specifically, the first transparent layer IT may be Indium-Tin Oxide (ITO), and the second transparent layer IG may be Indium-Galium Oxide (IGO). The first transparent layer IT and the second transparent layer IG have similar properties and react to the same etching solution, but there is a difference in etch rate. In particular, it is preferable that the second transparent layer IG has a faster etch rate than the first transparent layer IT. That is, it is preferable to stack the second transparent layer IG having a fast etch rate as a sacrificial layer so as to be interposed between the two first transparent layers IT having a slow etch rate.

After the connection terminal CT is coated in a structure in which the first transparent layer IT, the second transparent layer IG, and the first transparent layer IT are stacked, when etching is performed, the second transparent layer IG becomes the first transparent layer. It is over-etched than those of (IT). As a result, the width of the second transparent layer IG positioned in the middle has a shape of a bobbin or a gear having a width narrower than that of the first transparent layers IT positioned above and below.

When the organic light-emitting layer OL is applied on the connection terminal CT having the shape of a spool or long tool, the organic light-emitting layer OL is applied only to a position separated by a predetermined distance from the sidewall of the connection terminal CT. That is, the etching sidewalls of the connection terminal CT on which the first transparent layer IT, the second transparent layer IG, and the first transparent layer IT are stacked are exposed as it is. Thereafter, when the cathode electrode CAT is applied, the cathode electrode CAT contacts the sidewall of the connection terminal CT.

Here, the connection terminal CT may be formed in a two-layer structure in which the second transparent layer IG and the first transparent layer IT are sequentially stacked. In this case, the second transparent layer IG located in the lower layer is over-etched than the first transparent layer IT located in the upper layer to form a reverse tapered shape. Even in this case, when the organic light-emitting layer OL is applied, the second transparent layer IG and the first transparent layer IT are applied only to a position separated by a predetermined distance from the laminated etch sidewall. Accordingly, transparent layers having different etch rates may be stacked to configure the connection terminal CT.

When the connection terminal CT is formed only in a double-layer structure, the organic light-emitting layer OL is partially applied adjacent to the second transparent layer IG, which is a lower layer, or a portion applied to the upper surface of the first transparent layer IT, which is an upper layer. Can flow down. In this case, when the cathode electrode CAT is applied, the cathode electrode CAT may not be in smooth contact with the connection terminal CT.

In consideration of this problem, if a connection terminal (CT) is composed of three layers and the etched shape is over-etched than the upper and lower layers, the central layer is concave, and the lower and upper layers have a convex failure or long ball shape, The second transparent layer IG as the intermediate layer and the first transparent layer IT as the upper layer may be reliably exposed. As a result, the contact between the cathode electrode CAT and the connection terminal CT can be secured more reliably.

As described above, there are various factors that cause the deposition profile of the organic light emitting layer OL and the deposition profile of the cathode electrode CAT to appear differently in the opening area where the connection terminal CT is exposed. First, it is because the material to be deposited is different. Second, it is possible to induce different deposition profiles by artificially different deposition conditions. Since the deposition conditions are different depending on the deposition equipment and environment used, the best results can be obtained by repeatedly performing several times. As a more important factor, the shape of the connection terminal (CT) is reverse-tapered, and more preferably, the central layer proposed in the present invention is over-etched than the lower and upper layers, so that the central layer is concave and the lower and upper layers are convex. By forming to have a composite tapered structure having a, it is possible to obtain a result in which the deposition profile is more effectively different.

In order to better obtain the advantages of the present invention, it is preferable to apply the thickness of the second transparent layer IG positioned in the middle to about twice the thickness of the first transparent layer IT positioned in the upper and lower portions. For example, it is recommended to deposit the first transparent layer IT of the lower layer to a thickness of 1,000 Å, the second transparent layer IG of the intermediate layer to a thickness of 2,000 Å, and the first transparent layer IT of the upper layer to a thickness of 800 Å. desirable. In the case of such a thickness structure, after forming the connection terminal CT, the first transparent layer IT has a width greater than 0.5 to 0.8 μm on one side than the second transparent layer IG. In addition, the first transparent layer IT has an etch taper angle of 30 degrees or less. Therefore, the connection terminal CT may have an ideal shape of a failure (bobbin) or a long tool.

In addition, in the present invention, since it is always considered to simplify the manufacturing process, it is preferable to form the connection terminal CT at the same time when the anode electrode ANO is formed. Therefore, it is preferable to use the same transparent conductive material as the anode electrode ANO for the connection terminal CT. For example, indium oxide, tin oxide, or zinc oxide-based indium-tin oxide, Indium-Zinc Oxide, Indium-Galium-Zinc Oxide And/or Indium-Tin-Zinc Oxide.

A cap TS maintaining a predetermined distance is attached to the thin film transistor substrate SUB having the above structure. In this case, it is preferable that the thin film transistor substrate SUB and the cap TS have an organic bonding layer FS interposed therebetween so that the thin film transistor substrate SUB and the cap TS are completely sealed and bonded while maintaining a constant distance. The organic bonding layer FS faces and seals the thin film transistor substrate and the cap TS to each other to prevent moisture and gas from penetrating from the outside.

In addition, a color filter CF formed to correspond to the light emitting area may be further included on the inner surface of the cap TS. In particular, when the organic light-emitting layer OL emits white light, red (R)-green (G)-blue (B) colors may be implemented using a color filter CF. If necessary, a black matrix BM may be further disposed between the color filters CF. The black matrix BM may be formed in a position corresponding to the non-emission area excluding the emission area on the thin film transistor substrate SUB.

In the organic light emitting diode display having such a structure, the cathode electrode CAT having a basic voltage is applied over the entire surface of the substrate SUB of the display panel. In the top emission type, a transparent conductive material must be formed in order to secure transmittance. Since the transparent conductive material has a considerably higher surface resistance than a metal material, a problem may occur in image quality.

However, in the organic light emitting diode display according to the present invention, the cathode electrode CAT is in electrical contact with the auxiliary cathode electrode AC formed by using the light blocking layer LS. Therefore, when the present invention is applied to the top emission type, the surface resistance of the cathode electrode CAT can be lowered by the auxiliary cathode electrode AC, which is advantageous for implementing a transparent and/or large area organic light emitting diode display. Do.

Hereinafter, a method of manufacturing an organic light emitting diode display according to the present invention will be described with reference to FIGS. 5A to 5J. For convenience, only the process of manufacturing the thin film transistor substrate will be described. 5A to 5J are cross-sectional views illustrating a manufacturing process of the organic light emitting diode display device according to the present invention, taken along the line II-II' in FIG. 3.

An opaque metal material, an insulating material, and a metal oxide semiconductor material are continuously applied on the substrate SUB. The three materials are simultaneously patterned by the first mask process to form the light blocking layer LS, the auxiliary cathode electrode AC, the buffer layer BUF, and the semiconductor material layer SE. The semiconductor material layer SE is a portion to be further etched to have a size smaller than that of the light blocking layer LS to form a thin film transistor. Therefore, it is preferable to use a half-tone mask for the first mask process. For example, it is recommended to use a full-tone in the portion where the semiconductor layers SA and DA of the thin film transistor are to be formed, and use a half-tone in the portion of the light-shielding layer LS excluding the semiconductor layers SA and DA. desirable. (Fig. 5a)

The photoresist PR is ashed to leave the photoresist PR only at the portion where the semiconductor layers SA and DA are to be formed. The semiconductor material layer SE is patterned using the photoresist PR as a mask to form the switching semiconductor layer SA and the driving semiconductor layer DA. At this time, the semiconductor material layer SE on the auxiliary cathode electrode AC is also removed. (Fig. 5b)

A gate insulating material and a gate metal material are successively coated on the substrate SUB on which the semiconductor layers SA and DA are formed. By patterning by a second mask process, a gate insulating layer GI and gate elements are formed. The gate elements include a switching gate electrode SG, a driving gate electrode DG, a first storage capacitor electrode ST1, a scan line SL, and a gate pad GP. The switching gate electrode SG overlaps the channel region of the switching semiconductor layer SA, and the driving gate electrode DG overlaps the channel region of the driving semiconductor layer DA. (Fig. 5c)

An intermediate insulating layer IN is applied on the substrate SUB on which the gate elements are formed. The intermediate insulating layer IN is patterned by a third mask process to form contact holes. In the contact holes, contact holes opening the source and drain regions in the semiconductor layers SA and DA, the gate contact hole GH exposing a part of the driving gate electrode DG, and the auxiliary cathode electrode AC. It includes a first cathode contact hole CH1 exposing a portion. (Fig. 5d)

A source metal material is applied on the substrate SUB in which the contact holes are formed. A source metal material is patterned by a fourth mask process to form a source-drain element. The source-drain elements include a data line DL, a switching source electrode SS and a switching drain electrode SD, a driving source electrode DS and a driving drain electrode DD, a second storage capacitor electrode ST2, and an intermediate. A connection terminal CC, a driving current line VDD, a gate intermediate pad GP2, and a data pad DP are included. The switching drain electrode SD is connected to the driving drain electrode DG through the gate contact hole GH. The intermediate connection terminal CC is connected to the auxiliary cathode electrode AC through the first cathode contact hole CH1. The second storage capacitor electrode ST2 extends from the driving drain electrode DD and overlaps the first storage capacitor electrode ST1 and the intermediate insulating layer IN to form the storage capacitor STG. (Fig. 5e)

A planarization film PAC is applied on the substrate SUB on which the source-drain elements are formed. Contact holes are formed by patterning the planarization layer PAC in a fifth mask process. Here, when patterning the planarization layer PAC, it is preferable to form the gate intermediate pad GP2 and the data pad DP to be exposed. In the contact holes, a pixel contact hole PH exposing a part of the driving drain electrode DD and a cathode contact hole CH exposing the connection intermediate terminal CC are formed. (Fig. 5f)

A first transparent layer IT, a second transparent layer IG, and a first transparent layer IT are sequentially applied on the substrate SUB in which the contact holes are formed. That is, in the triple layer, the first transparent layer IT is disposed on the lower and upper layers, and the second transparent layer IG is disposed on the center layer. The triple layers are patterned by a sixth mask process to form an anode electrode ANO, a connection terminal CT, a data pad terminal DPT, and a gate pad terminal GPT. Here, when a material having an etch rate of the second transparent layer IG higher than that of the first transparent layer IT is selected, the central layer is etched faster than the lower and upper layers. So, the lower layer is patterned in a positive taper shape and the upper layer is patterned in an inverse tapered shape. That is, the anode electrode ANO, the connection terminal CT, the data pad terminal DPT, and the gate pad terminal GPT are formed such that the etched sidewalls of the edges have a failure (bobbin) or long ball shape. (Fig. 5g)

An organic insulating material is coated on the substrate SUB on which the anode electrode ANO and the connection terminal CT are formed. An organic insulating material is patterned with a seventh mask to form a bank BN. The bank BN is patterned to have an opening area. Particularly, in the anode electrode ANO, the pattern is made to have opening regions that expose the central region and cover the rim. Meanwhile, in the connection terminal CT, opening regions are formed such that the sidewall of the bank BN is positioned at a predetermined distance away from the edge of the connection terminal CT so as to expose all the connection terminals CT. That is, the anode electrode ANO has an etched sidewall covered by the bank BN, but the connection terminal CT has an etched sidewall exposed. Meanwhile, it is preferable to form the bank BN so that all of the pads GP2 and DP are exposed. (Fig. 5h)

The organic light emitting layer OL is applied to all regions of the substrate SUB in which the banks BN are formed. The organic light emitting layer OL covers the upper surface of the bank BN and covers the upper surfaces of the anode electrode ANO and the connection terminal CT exposed in the opening area. However, the etching side of the connection terminal CT is exposed. (Figure 5i)

The cathode electrode CAT is applied on the substrate SUB on which the organic light emitting layer OL is applied. The anode electrode ANO, the organic light-emitting layer OL, and the cathode electrode CAT are stacked to complete the organic light-emitting diode OLE. In addition, the cathode electrode CAT is in contact with the exposed etching side of the connection terminal CT. Accordingly, the cathode electrode CAT is connected to the auxiliary cathode electrode AC through the connection terminal CT and the intermediate connection terminal CC. (Fig. 5j)

As described above, the method of manufacturing the organic light emitting diode display according to the present invention can be completed in seven mask steps. Compared to using 12 or more mask processes in the existing manufacturing process, the number of processes can be significantly reduced. This is because the auxiliary cathode electrode CAT could not be formed by a separate process, but could be performed in one mask process of forming a semiconductor layer. Moreover, since the auxiliary cathode electrode AC is formed simultaneously with the light blocking layer LS, which is the lowermost layer, the auxiliary cathode electrode AC has a structure in which parasitic capacitance is not generated. Therefore, since it is not necessary to use a double insulating film structure for suppressing parasitic capacitance, the number of mask processes can be further reduced. In addition, even in a structure connecting the cathode electrode CAT and the auxiliary cathode AC, it is possible to achieve a mask process of forming the bank BN without using a separate mask process.

An important feature of the present invention is that in forming the connection terminal (CT) and the anode electrode (ANO) as a triple layer, all three layers use a material of a similar series, but the material of the intermediate layer has different properties from the upper and lower layers. It is in use. In particular, indium oxide, tin oxide, or zinc oxide-based materials are used to react to the same etchant, but there is a difference in etch rate, specifically, the material of the intermediate layer is characterized by a faster etch rate than the upper and lower layers. . Although the embodiment is not presented, if necessary, the upper layer and the lower layer may also react to the same etching solution using a similar transparent conductive material, but there may be a slight difference in the etching rate. For example, the upper layer may have a slightly faster etch rate than the lower layer, and the intermediate layer may have a faster etch rate than the upper layer.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the spirit of the present invention. Accordingly, the present invention should not be limited to the content described in the detailed description, but should be defined by the claims.

ST: switching thin film transistor DT: driving thin film transistor
SL: Scan wiring DL: Data wiring
VDD: drive current wiring SUB: (thin film transistor) substrate
GI: gate insulating film IN: insulating film
PAS: protective film PAC: planarizing film
OL: organic light emitting layer OLE: organic light emitting diode
FS: organic cementation film TS: cap
CH: cathode contact hole AC: auxiliary cathode electrode
CH1: first cathode contact hole CT: connection terminal
CC: intermediate connection terminal IT: first transparent layer
IG: second transparent layer BN: bank

Claims (5)

A light blocking layer and an auxiliary cathode electrode disposed on the substrate;
A thin film transistor disposed on the light blocking layer;
A planarization layer covering the thin film transistor and the auxiliary cathode electrode;
An anode electrode connected to the thin film transistor on the planarization layer;
A connection terminal connected to the auxiliary cathode electrode on the planarization layer;
A bank exposing the central surface of the anode electrode and the entire connection terminal;
An organic light-emitting layer stacked on a central surface of the anode electrode and an upper surface of the connection terminal, and exposing an etched side surface of the connection terminal; And
An organic light-emitting diode display comprising a cathode electrode stacked on the organic light-emitting layer and in contact with the etched side of the connection terminal.
The method of claim 1,
The anode electrode and the connection terminal,
A first transparent layer disposed on the lower and upper layers, respectively; And
An organic light emitting diode display comprising a second transparent layer interposed in a central layer between the lower layer and the upper layer.
The method of claim 2,
The second transparent layer is over-etched than the first transparent layer, so that the central layer is concave and the lower layer and the upper layer are convex.
The method of claim 3,
The lower layer has a positive taper shape having an etch taper angle of less than 30 degrees,
The upper layer is an organic light emitting diode display having an inverse taper shape having an etch taper angle of less than 30 degrees.
The method of claim 2,
The first transparent layer and the second transparent layer include any one of indium oxide, zinc oxide, and tin oxide,
An organic light emitting diode display comprising a material having an etch rate of the second transparent layer faster than that of the first transparent layer.

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