KR101820813B1 - Soc 장치 및 soc 장치를 동작시키는 방법 - Google Patents

Soc 장치 및 soc 장치를 동작시키는 방법 Download PDF

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KR101820813B1
KR101820813B1 KR1020167003858A KR20167003858A KR101820813B1 KR 101820813 B1 KR101820813 B1 KR 101820813B1 KR 1020167003858 A KR1020167003858 A KR 1020167003858A KR 20167003858 A KR20167003858 A KR 20167003858A KR 101820813 B1 KR101820813 B1 KR 101820813B1
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South Korea
Prior art keywords
interconnects
pitch
metal
gate
metal layer
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Expired - Fee Related
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KR1020167003858A
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English (en)
Korean (ko)
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KR20160034338A (ko
Inventor
시앙동 첸
오상 권
에신 터지오글루
하디 번나림
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퀄컴 인코포레이티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H01L23/5226—
    • H01L21/76813—
    • H01L21/76816—
    • H01L21/76838—
    • H01L23/498—
    • H01L23/528—
    • H01L25/072—
    • H01L27/0207—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020167003858A 2013-07-25 2014-07-23 Soc 장치 및 soc 장치를 동작시키는 방법 Expired - Fee Related KR101820813B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361858567P 2013-07-25 2013-07-25
US61/858,567 2013-07-25
US14/338,229 2014-07-22
US14/338,229 US9331016B2 (en) 2013-07-25 2014-07-22 SOC design with critical technology pitch alignment
PCT/US2014/047834 WO2015013415A1 (en) 2013-07-25 2014-07-23 A soc design with critical technology pitch alignment

Publications (2)

Publication Number Publication Date
KR20160034338A KR20160034338A (ko) 2016-03-29
KR101820813B1 true KR101820813B1 (ko) 2018-01-22

Family

ID=52389817

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Application Number Title Priority Date Filing Date
KR1020167003858A Expired - Fee Related KR101820813B1 (ko) 2013-07-25 2014-07-23 Soc 장치 및 soc 장치를 동작시키는 방법

Country Status (7)

Country Link
US (1) US9331016B2 (https=)
EP (1) EP3025370B1 (https=)
JP (1) JP6208350B2 (https=)
KR (1) KR101820813B1 (https=)
CN (1) CN105453263B (https=)
CA (1) CA2917642A1 (https=)
WO (1) WO2015013415A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9391056B2 (en) * 2013-08-16 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Mask optimization for multi-layer contacts
US9786663B2 (en) 2013-08-23 2017-10-10 Qualcomm Incorporated Layout construction for addressing electromigration
US9972624B2 (en) 2013-08-23 2018-05-15 Qualcomm Incorporated Layout construction for addressing electromigration
EP4514088A3 (en) 2017-06-20 2025-05-07 INTEL Corporation Internal node jumper for memory bit cells
DE102018118053A1 (de) 2017-07-28 2019-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte Schaltungsvorrichtung mit verbessertem Layout
US10903239B2 (en) 2017-07-28 2021-01-26 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device with improved layout
US10916498B2 (en) 2018-03-28 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for logic circuit
KR102842752B1 (ko) 2019-12-04 2025-08-04 삼성전자주식회사 반도체 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030051217A1 (en) 2001-08-31 2003-03-13 Cheng Chih-Liang Estimating capacitance effects in integrated circuits using congestion estimations
US20060289861A1 (en) 2005-06-27 2006-12-28 Correale Anthony Jr Systems and arrangements to interconnect components of a semiconductor device
US20130072020A1 (en) 2011-09-19 2013-03-21 Texas Instruments Incorporated Method For Ensuring DPT Compliance for Auto-Routed Via Layers
US20130175631A1 (en) 2012-01-06 2013-07-11 International Business Machines Corporation Layout to minimize fet variation in small dimension photolithography

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JP3241106B2 (ja) * 1992-07-17 2001-12-25 株式会社東芝 ダイナミック型半導体記憶装置及びその製造方法
US5508938A (en) 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
US5471093A (en) 1994-10-28 1995-11-28 Advanced Micro Devices, Inc. Pseudo-low dielectric constant technology
US6207479B1 (en) * 1999-06-14 2001-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Place and route method for integrated circuit design
US7398498B2 (en) * 2001-08-23 2008-07-08 Cadence Design Systems, Inc. Method and apparatus for storing routes for groups of related net configurations
US6735753B2 (en) 2002-10-04 2004-05-11 Oki Electric Industry Co., Ltd. Method of fabricating a semiconductor device having a multilevel interconnections
US7084476B2 (en) * 2004-02-26 2006-08-01 International Business Machines Corp. Integrated circuit logic with self compensating block delays
US7414275B2 (en) * 2005-06-24 2008-08-19 International Business Machines Corporation Multi-level interconnections for an integrated circuit chip
JP4791855B2 (ja) * 2006-02-28 2011-10-12 株式会社東芝 半導体記憶装置
US7446352B2 (en) * 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US7917879B2 (en) * 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US7557449B2 (en) 2006-09-07 2009-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Flexible via design to improve reliability
JP2008171977A (ja) * 2007-01-11 2008-07-24 Matsushita Electric Ind Co Ltd 半導体集積回路のレイアウト構造
US7737554B2 (en) * 2007-06-25 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Pitch by splitting bottom metallization layer
US7852114B2 (en) 2008-08-14 2010-12-14 Nantero, Inc. Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same
US8198655B1 (en) * 2009-04-27 2012-06-12 Carnegie Mellon University Regular pattern arrays for memory and logic on a semiconductor substrate
US8174868B2 (en) 2009-09-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Embedded SRAM structure and chip
JP5655086B2 (ja) * 2010-10-21 2015-01-14 パナソニック株式会社 半導体装置
JP6066542B2 (ja) 2010-11-18 2017-01-25 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US8863048B1 (en) * 2013-03-15 2014-10-14 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030051217A1 (en) 2001-08-31 2003-03-13 Cheng Chih-Liang Estimating capacitance effects in integrated circuits using congestion estimations
US20060289861A1 (en) 2005-06-27 2006-12-28 Correale Anthony Jr Systems and arrangements to interconnect components of a semiconductor device
US20130072020A1 (en) 2011-09-19 2013-03-21 Texas Instruments Incorporated Method For Ensuring DPT Compliance for Auto-Routed Via Layers
US20130175631A1 (en) 2012-01-06 2013-07-11 International Business Machines Corporation Layout to minimize fet variation in small dimension photolithography

Also Published As

Publication number Publication date
CN105453263A (zh) 2016-03-30
EP3025370A1 (en) 2016-06-01
EP3025370B1 (en) 2017-02-01
WO2015013415A1 (en) 2015-01-29
CA2917642A1 (en) 2015-01-29
KR20160034338A (ko) 2016-03-29
JP6208350B2 (ja) 2017-10-04
CN105453263B (zh) 2021-03-12
US20150028495A1 (en) 2015-01-29
US9331016B2 (en) 2016-05-03
JP2016527724A (ja) 2016-09-08

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