KR101810711B1 - 반도체 소자를 성장시키기 위한 복합 성장 기판 - Google Patents

반도체 소자를 성장시키기 위한 복합 성장 기판 Download PDF

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KR101810711B1
KR101810711B1 KR1020127033066A KR20127033066A KR101810711B1 KR 101810711 B1 KR101810711 B1 KR 101810711B1 KR 1020127033066 A KR1020127033066 A KR 1020127033066A KR 20127033066 A KR20127033066 A KR 20127033066A KR 101810711 B1 KR101810711 B1 KR 101810711B1
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layer
donor
substrate
relax
strained
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KR20130113337A (ko
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앤드류 와이. 김
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코닌클리케 필립스 엔.브이.
루미레즈 엘엘씨
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Led Devices (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
KR1020127033066A 2010-05-19 2011-04-27 반도체 소자를 성장시키기 위한 복합 성장 기판 Active KR101810711B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/783,354 2010-05-19
US12/783,354 US8536022B2 (en) 2010-05-19 2010-05-19 Method of growing composite substrate using a relaxed strained layer
PCT/IB2011/051844 WO2011145012A1 (en) 2010-05-19 2011-04-27 Composite growth substrate for growing a semiconductor device

Publications (2)

Publication Number Publication Date
KR20130113337A KR20130113337A (ko) 2013-10-15
KR101810711B1 true KR101810711B1 (ko) 2017-12-19

Family

ID=44120315

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020127033066A Active KR101810711B1 (ko) 2010-05-19 2011-04-27 반도체 소자를 성장시키기 위한 복합 성장 기판

Country Status (7)

Country Link
US (1) US8536022B2 (enExample)
EP (1) EP2572370A1 (enExample)
JP (1) JP5848334B2 (enExample)
KR (1) KR101810711B1 (enExample)
CN (1) CN102893373B (enExample)
TW (1) TW201222631A (enExample)
WO (1) WO2011145012A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120309172A1 (en) * 2011-05-31 2012-12-06 Epowersoft, Inc. Epitaxial Lift-Off and Wafer Reuse
US10141197B2 (en) 2016-03-30 2018-11-27 Stmicroelectronics S.R.L. Thermosonically bonded connection for flip chip packages
GB2586862B (en) * 2019-09-06 2021-12-15 Plessey Semiconductors Ltd LED precursor incorporating strain relaxing structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004061944A1 (en) 2003-01-07 2004-07-22 S.O.I.Tec Silicon On Insulator Technologies Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
JP2007096330A (ja) * 2005-09-27 2007-04-12 Philips Lumileds Lightng Co Llc Ｉｉｉ−ｖ族発光デバイス
US20100025728A1 (en) * 2008-05-15 2010-02-04 Bruce Faure Relaxation and transfer of strained layers
WO2010036622A1 (en) * 2008-09-24 2010-04-01 S.O.I. Tec Silicon On Insulator Technologies Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same

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FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
FR2817394B1 (fr) 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6717213B2 (en) * 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
US7279718B2 (en) 2002-01-28 2007-10-09 Philips Lumileds Lighting Company, Llc LED including photonic crystal structure
US6774015B1 (en) * 2002-12-19 2004-08-10 International Business Machines Corporation Strained silicon-on-insulator (SSOI) and method to form the same
FR2851848B1 (fr) 2003-02-28 2005-07-08 Soitec Silicon On Insulator Relaxation a haute temperature d'une couche mince apres transfert
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7012279B2 (en) 2003-10-21 2006-03-14 Lumileds Lighting U.S., Llc Photonic crystal light emitting device
US20050205883A1 (en) 2004-03-19 2005-09-22 Wierer Jonathan J Jr Photonic crystal light emitting device
US6956247B1 (en) 2004-05-26 2005-10-18 Lumileds Lighting U.S., Llc Semiconductor light emitting device including photonic band gap material and luminescent material
US7442964B2 (en) 2004-08-04 2008-10-28 Philips Lumileds Lighting Company, Llc Photonic crystal light emitting device with multiple lattices
US7244630B2 (en) * 2005-04-05 2007-07-17 Philips Lumileds Lighting Company, Llc A1InGaP LED having reduced temperature dependence
US7273798B2 (en) * 2005-08-01 2007-09-25 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Gallium nitride device substrate containing a lattice parameter altering element
US8334155B2 (en) * 2005-09-27 2012-12-18 Philips Lumileds Lighting Company Llc Substrate for growing a III-V light emitting device
US7547908B2 (en) * 2006-12-22 2009-06-16 Philips Lumilieds Lighting Co, Llc III-nitride light emitting devices grown on templates to reduce strain
US20080259980A1 (en) * 2007-04-19 2008-10-23 Philips Lumileds Lighting Company, Llc Semiconductor Light Emitting Device Including Oxide Layer
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
TWI457984B (zh) * 2008-08-06 2014-10-21 Soitec Silicon On Insulator 應變層的鬆弛方法
JP5109912B2 (ja) * 2008-10-03 2012-12-26 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置
US8227791B2 (en) * 2009-01-23 2012-07-24 Invenlux Limited Strain balanced light emitting devices
WO2011022730A1 (en) * 2009-08-21 2011-02-24 The Regents Of The University Of California Anisotropic strain control in semipolar nitride quantum wells by partially or fully relaxed aluminum indium gallium nitride layers with misfit dislocations
US8105852B2 (en) * 2010-01-15 2012-01-31 Koninklijke Philips Electronics N.V. Method of forming a composite substrate and growing a III-V light emitting device over the composite substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004061944A1 (en) 2003-01-07 2004-07-22 S.O.I.Tec Silicon On Insulator Technologies Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
JP2007096330A (ja) * 2005-09-27 2007-04-12 Philips Lumileds Lightng Co Llc Ｉｉｉ−ｖ族発光デバイス
US20100025728A1 (en) * 2008-05-15 2010-02-04 Bruce Faure Relaxation and transfer of strained layers
WO2010036622A1 (en) * 2008-09-24 2010-04-01 S.O.I. Tec Silicon On Insulator Technologies Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE Transactions on Electron Devices, Vol. 52, No. 10, pp.2207-2214
Journal of Applied Physics, Vol. 85, No. 8, pp.4040-4044

Also Published As

Publication number Publication date
EP2572370A1 (en) 2013-03-27
CN102893373B (zh) 2016-07-20
US8536022B2 (en) 2013-09-17
TW201222631A (en) 2012-06-01
JP5848334B2 (ja) 2016-01-27
US20110284993A1 (en) 2011-11-24
CN102893373A (zh) 2013-01-23
JP2013528945A (ja) 2013-07-11
WO2011145012A1 (en) 2011-11-24
KR20130113337A (ko) 2013-10-15

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