KR101770877B1 - 실리콘 관통 비아를 사용한 집적 회로 구조물 - Google Patents

실리콘 관통 비아를 사용한 집적 회로 구조물 Download PDF

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KR101770877B1
KR101770877B1 KR1020137033346A KR20137033346A KR101770877B1 KR 101770877 B1 KR101770877 B1 KR 101770877B1 KR 1020137033346 A KR1020137033346 A KR 1020137033346A KR 20137033346 A KR20137033346 A KR 20137033346A KR 101770877 B1 KR101770877 B1 KR 101770877B1
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tsv
circuit
tsvs
interposer
active circuit
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KR20140039227A (ko
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아리푸르 라흐만
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자일링크스 인코포레이티드
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020137033346A 2011-06-27 2012-01-16 실리콘 관통 비아를 사용한 집적 회로 구조물 Active KR101770877B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/170,020 2011-06-27
US13/170,020 US8560982B2 (en) 2011-06-27 2011-06-27 Integrated circuit design using through silicon vias
PCT/US2012/021416 WO2013002844A1 (en) 2011-06-27 2012-01-16 Integrated circuit design using through silicon vias

Publications (2)

Publication Number Publication Date
KR20140039227A KR20140039227A (ko) 2014-04-01
KR101770877B1 true KR101770877B1 (ko) 2017-08-23

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KR1020137033346A Active KR101770877B1 (ko) 2011-06-27 2012-01-16 실리콘 관통 비아를 사용한 집적 회로 구조물

Country Status (6)

Country Link
US (1) US8560982B2 (https=)
EP (1) EP2724371B1 (https=)
JP (1) JP6009556B2 (https=)
KR (1) KR101770877B1 (https=)
CN (1) CN103688355B (https=)
WO (1) WO2013002844A1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8264065B2 (en) * 2009-10-23 2012-09-11 Synopsys, Inc. ESD/antenna diodes for through-silicon vias
US8766459B2 (en) * 2010-05-03 2014-07-01 Georgia Tech Research Corporation CMUT devices and fabrication methods
US8604619B2 (en) 2011-08-31 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via keep out zone formation along different crystal orientations
US20130132023A1 (en) * 2011-11-17 2013-05-23 Advanced Micro Devices, Inc. Structure for characterizing through-silicon vias and methods thereof
US8664768B2 (en) * 2012-05-03 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer having a defined through via pattern
US9026872B2 (en) * 2012-08-16 2015-05-05 Xilinx, Inc. Flexible sized die for use in multi-die integrated circuit
US9997443B2 (en) 2013-02-25 2018-06-12 Infineon Technologies Ag Through vias and methods of formation thereof
US8952500B2 (en) 2013-03-15 2015-02-10 IPEnval Consultant Inc. Semiconductor device
US8957504B2 (en) 2013-03-15 2015-02-17 IP Enval Consultant Inc. Integrated structure with a silicon-through via
US9030025B2 (en) 2013-03-15 2015-05-12 IPEnval Consultant Inc. Integrated circuit layout
US9547034B2 (en) 2013-07-03 2017-01-17 Xilinx, Inc. Monolithic integrated circuit die having modular die regions stitched together
US10610512B2 (en) 2014-06-26 2020-04-07 Island Breeze Systems Ca, Llc MDI related products and methods of use
US10713406B2 (en) * 2015-11-30 2020-07-14 The Regents Of The University Of California Multi-die IC layout methods with awareness of mix and match die integration
CN105866665B (zh) * 2016-03-31 2019-04-05 复旦大学 面向高性能SoC FPGA的功能遍历测试方法
US10497677B1 (en) 2017-02-09 2019-12-03 Xilinx, Inc. ESD protection in a stacked integrated circuit assembly
US10671792B2 (en) * 2018-07-29 2020-06-02 International Business Machines Corporation Identifying and resolving issues with plated through vias in voltage divider regions
US10700041B2 (en) * 2018-09-21 2020-06-30 Facebook Technologies, Llc Stacking of three-dimensional circuits including through-silicon-vias
US11114429B2 (en) 2019-04-23 2021-09-07 Xilinx, Inc. Integrated circuit device with electrostatic discharge (ESD) protection
JP7462269B2 (ja) * 2020-05-19 2024-04-05 パナソニックＩｐマネジメント株式会社 半導体装置及び半導体装置の製造方法
JP7434118B2 (ja) * 2020-09-11 2024-02-20 ルネサスエレクトロニクス株式会社 半導体装置
CN116344441B (zh) * 2023-02-03 2024-01-12 深圳华芯星半导体有限公司 一种芯片封装方法及计算机可读存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004342724A (ja) 2003-05-14 2004-12-02 Sony Corp 半導体装置およびその製造方法
JP2009194363A (ja) 2008-01-18 2009-08-27 National Institute Of Advanced Industrial & Technology ３次元集積回路
US20110073917A1 (en) 2009-09-29 2011-03-31 Magic Technologies, Inc. Method of high density memory fabrication

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6913990B2 (en) * 2003-07-28 2005-07-05 Infineon Technologies Ag Method of forming isolation dummy fill structures
US7763965B2 (en) 2007-09-25 2010-07-27 International Business Machines Corporation Stress relief structures for silicon interposers
US8082537B1 (en) 2009-01-28 2011-12-20 Xilinx, Inc. Method and apparatus for implementing spatially programmable through die vias in an integrated circuit
US8146032B2 (en) * 2009-01-30 2012-03-27 Synopsys, Inc. Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs
US20100257495A1 (en) * 2009-04-06 2010-10-07 Chan-Liang Wu 3D-IC Verification Method
US8362622B2 (en) 2009-04-24 2013-01-29 Synopsys, Inc. Method and apparatus for placing transistors in proximity to through-silicon vias
US7969013B2 (en) * 2009-10-22 2011-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via with dummy structure and method for forming the same
US8264065B2 (en) 2009-10-23 2012-09-11 Synopsys, Inc. ESD/antenna diodes for through-silicon vias

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004342724A (ja) 2003-05-14 2004-12-02 Sony Corp 半導体装置およびその製造方法
JP2009194363A (ja) 2008-01-18 2009-08-27 National Institute Of Advanced Industrial & Technology ３次元集積回路
US20110073917A1 (en) 2009-09-29 2011-03-31 Magic Technologies, Inc. Method of high density memory fabrication

Also Published As

Publication number Publication date
EP2724371A1 (en) 2014-04-30
JP2014523645A (ja) 2014-09-11
JP6009556B2 (ja) 2016-10-19
WO2013002844A1 (en) 2013-01-03
EP2724371B1 (en) 2017-08-30
KR20140039227A (ko) 2014-04-01
CN103688355B (zh) 2016-06-01
US8560982B2 (en) 2013-10-15
US20120331435A1 (en) 2012-12-27
CN103688355A (zh) 2014-03-26

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